JP2017139369A - 素子チップの製造方法および電子部品実装構造体の製造方法ならびに電子部品実装構造体 - Google Patents
素子チップの製造方法および電子部品実装構造体の製造方法ならびに電子部品実装構造体 Download PDFInfo
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- JP2017139369A JP2017139369A JP2016019866A JP2016019866A JP2017139369A JP 2017139369 A JP2017139369 A JP 2017139369A JP 2016019866 A JP2016019866 A JP 2016019866A JP 2016019866 A JP2016019866 A JP 2016019866A JP 2017139369 A JP2017139369 A JP 2017139369A
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- element chip
- protective film
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- manufacturing
- solder
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 230000001681 protective effect Effects 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims description 43
- 229910000679 solder Inorganic materials 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 30
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 10
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005304 joining Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 abstract description 13
- 238000004380 ashing Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 51
- 239000010410 layer Substances 0.000 description 13
- 238000001020 plasma etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical group O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 238000009623 Bosch process Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
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- H—ELECTRICITY
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
- H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L2224/808—Bonding techniques
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- Dicing (AREA)
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Abstract
Description
1a 第1の面
1b 第2の面
1c 分割領域
2 素子領域
3 素子電極
4 絶縁膜
5 耐エッチング層
6 キャリア
10 素子チップ
10a 第1の面
10b 第2の面
10c 側面
12a,12b,12c 保護膜
15 プリント基板
16 ランド電極
17 半田
E 角部
C 窪み部
Claims (8)
- 分割領域で画定された複数の素子領域を有し少なくともその一部が絶縁膜で覆われた第1の面と、前記第1の面と反対側の第2の面とを備える基板を、前記分割領域で分割して複数の素子チップを製造する素子チップの製造方法であって、
前記第1の面の側がキャリアに支持されるとともに、前記素子領域と対向する前記第2の面の領域を覆い且つ前記分割領域と対向する前記第2の面の領域を露出させるように耐エッチング層が形成された前記基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第2の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第1の面に達するまでエッチングして、前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持されるとともに、前記素子チップの前記側面と前記第1の面とが成す角部に前記絶縁膜を露出させた状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを第2のプラズマに晒すことにより、前記角部に露出させた前記絶縁膜を後退させて窪み部を形成する窪み部形成工程と、
前記窪み部形成工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを保護膜形成用ガスを供給しながら発生させた第3のプラズマに晒すことにより、前記素子チップの前記第2の面、前記素子チップの前記側面および前記窪み部に保護膜を形成する保護膜形成工程と、を含む、素子チップの製造方法。 - 前記保護膜形成工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを第4のプラズマに晒すことにより、前記窪み部に形成された前記保護膜の少なくとも一部は残存させながら、前記素子チップの前記第2の面および前記側面に形成された前記保護膜を除去する保護膜除去工程をさらに含む、請求項1記載の素子チップの製造方法。
- 前記絶縁膜が有機膜である、請求項1または2のいずれかに記載の素子チップの製造方法。
- 前記保護膜がフルオロカーボンを主成分とする膜である、請求項1から3のいずれかに記載の素子チップの製造方法。
- 前記保護膜形成用ガスがフッ化炭素を含む、請求項4に記載の素子チップの製造方法。
- 請求項1から5のいずれかに記載の素子チップの製造方法によって形成された素子チップが前記第1の面に備える素子電極を、前記素子電極と半田により形成された接合部によってプリント基板に形成されたランド電極に接合して成る電子部品実装構造体の製造方法であって、
前記ランド電極にペースト状の半田を供給する半田ペースト供給工程と、
前記素子電極を対応する前記ランド電極に供給された半田ペーストに着地させて前記プリント基板に搭載する搭載工程と、
前記プリント基板を加熱して前記半田を溶融させて前記素子電極とランド電極とを半田接合する接合部を形成する溶融工程と、
前記プリント基板を冷却して溶融した前記半田を固化させる冷却工程とを含み、
前記溶融工程において、前記窪み部に形成された前記保護膜が、溶融した半田の前記側面への這い上がりを抑制する、電子部品実装構造体の製造方法。 - プリント基板に形成されたランド電極に素子チップに形成された素子電極を半田によって接合して成る電子部品実装構造体であって、
前記素子チップは、前記プリント基板と対向する面に形成された前記素子電極と、前記素子チップの側面の前記プリント基板側の角部に形成された窪み部と、前記窪み部を被覆する保護膜とを有し、
前記保護膜によって前記半田の前記側面への這い上がりが阻止されている、電子部品実装構造体。 - 前記保護膜がフルオロカーボンを主成分とする膜である、請求項7に記載の電子部品実装構造体。
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US11114387B2 (en) | 2017-02-15 | 2021-09-07 | Industrial Technology Research Institute | Electronic packaging structure |
US10607831B2 (en) | 2017-05-04 | 2020-03-31 | International Business Machines Corporation | Thiourea organic compound for gallium arsenide based optoelectronics surface passivation |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002093752A (ja) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP2008529258A (ja) * | 2005-01-24 | 2008-07-31 | 松下電器産業株式会社 | 半導体チップの製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3915992B2 (ja) * | 2004-06-08 | 2007-05-16 | ローム株式会社 | 面実装型電子部品の製造方法 |
JP2008218884A (ja) * | 2007-03-07 | 2008-09-18 | Citizen Holdings Co Ltd | 半導体装置およびその製造方法 |
US8637967B2 (en) * | 2010-11-15 | 2014-01-28 | Infineon Technologies Ag | Method for fabricating a semiconductor chip and semiconductor chip |
US8802545B2 (en) * | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
US8557682B2 (en) * | 2011-06-15 | 2013-10-15 | Applied Materials, Inc. | Multi-layer mask for substrate dicing by laser and plasma etch |
JP5833411B2 (ja) * | 2011-11-11 | 2015-12-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法ならびに液晶表示装置 |
US8748297B2 (en) * | 2012-04-20 | 2014-06-10 | Infineon Technologies Ag | Methods of forming semiconductor devices by singulating a substrate by removing a dummy fill material |
US9553021B2 (en) * | 2012-09-03 | 2017-01-24 | Infineon Technologies Ag | Method for processing a wafer and method for dicing a wafer |
JP5942212B2 (ja) * | 2013-05-13 | 2016-06-29 | パナソニックIpマネジメント株式会社 | 半導体素子およびその製造方法、半導体モジュールおよびその製造方法、並びに、半導体パッケージ |
JP6302644B2 (ja) * | 2013-11-11 | 2018-03-28 | 株式会社ディスコ | ウェーハの加工方法 |
JP6101227B2 (ja) * | 2014-03-17 | 2017-03-22 | 株式会社東芝 | プラズマダイシング方法およびプラズマダイシング装置 |
SG10201903242QA (en) * | 2014-10-13 | 2019-05-30 | Utac Headquarters Pte Ltd | Methods for singulating semiconductor wafer |
US9589812B2 (en) * | 2014-11-06 | 2017-03-07 | Fuji Xerox Co., Ltd. | Fabrication method of semiconductor piece |
JP5817905B1 (ja) * | 2014-12-15 | 2015-11-18 | 富士ゼロックス株式会社 | 半導体片の製造方法 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002093752A (ja) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP2008529258A (ja) * | 2005-01-24 | 2008-07-31 | 松下電器産業株式会社 | 半導体チップの製造方法 |
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---|---|---|---|---|
JP2019125723A (ja) * | 2018-01-17 | 2019-07-25 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6994646B2 (ja) | 2018-01-17 | 2022-01-14 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
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