CN107039292A - 元件芯片的制造方法、电子部件安装构造体及其制造方法 - Google Patents

元件芯片的制造方法、电子部件安装构造体及其制造方法 Download PDF

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CN107039292A
CN107039292A CN201710063033.4A CN201710063033A CN107039292A CN 107039292 A CN107039292 A CN 107039292A CN 201710063033 A CN201710063033 A CN 201710063033A CN 107039292 A CN107039292 A CN 107039292A
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element chip
face
diaphragm
manufacture method
substrate
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CN107039292B (zh
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针贝笃史
置田尚吾
松原功幸
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Abstract

一种元件芯片的制造方法、电子部件安装构造体及其制造方法，能够抑制安装过程中的导电性材料的爬升。将具有多个元件区域且元件面被绝缘膜(4)覆盖的基板分割而制造多个元件芯片(10)的元件芯片的制造方法中使用的等离子体处理工序中，通过将基板暴露于第一等离子体，将基板分割成元件芯片(10)，成为具备第一面(10a)、第二面(10b)及侧面(10c)的元件芯片(10)彼此隔开间隔地保持在载体(6)上且露出了绝缘膜(4)的状态，通过将这些元件芯片(10)暴露于灰化用的第二等离子体，使绝缘膜(4)后退而形成凹陷部(C)后，通过保护膜形成用的第三等离子体，用保护膜(12a)覆盖凹陷部(C)，抑制安装过程中导电性材料向侧面(10c)的爬升。

Description

元件芯片的制造方法、电子部件安装构造体及其制造方法
技术领域
本发明涉及将具有多个元件区域的基板按照每一元件区域进行分割来制造元件芯片的元件芯片的制造方法及将该元件芯片安装在基板上而成的电子部件安装构造体的制造方法及电子部件安装构造体。
背景技术
半导体元件等元件芯片从具有多个元件区域的晶片状的基板分割成单片而制造(例如参照专利文献1)。在该专利文献所示的现有技术中，首先，在形成了电路的晶片的表面粘付在背面研磨胶带上的状态下对晶片的背面进行研磨，进而，通过蚀刻对晶片进行薄化。然后，在相当于元件区域的部分形成抗蚀剂层进行遮盖，通过实施等离子体蚀刻，将晶片分离为单片的半导体元件。
现有技术文献
专利文献
专利文献1：日本特开2002-93752号公报
发明内容
如上述那样，从晶片状的基板切出的单片状的元件芯片除被实施封装而作为器件装置使用外，有时会以WLCSP(Wafer Level Chip Size Package、晶片级芯片尺寸封装)等元件芯片的形态直接送至电子部件安装工序。在这种情况下，元件芯片以使电路形成面直接接触接合用的焊糊或银膏等导电性材料的形式安装。
本发明的目的在于提供一种能够抑制安装过程中的导电性材料的爬升的元件芯片的制造方法及电子部件安装构造体的制造方法以及电子部件安装构造体。
本发明的元件芯片的制造方法，将具备第一面和第一面的相反侧的第二面的基板在分割区域进行分割来制造多个元件芯片，第一面具有用分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖，元件芯片的制造方法具有如下特征。即，包括：准备工序，准备基板，基板的第一面侧被载体支承，并且基板形成有耐蚀刻层，使得覆盖与元件区域对置的第二面的区域且使与分割区域对置的第二面的区域露出；和等离子体处理工序，在准备工序之后，对支承在载体上的基板实施等离子体处理。等离子体处理工序包括：分割工序；在分割工序之后进行的凹陷部形成工序；和在凹陷部形成工序之后进行的保护膜形成工序。分割工序中，将第二面暴露于第一等离子体，从而将未被耐蚀刻层覆盖的区域的基板在该基板的深度方向上蚀刻至到达第一面而将基板分割为元件芯片。并且成为具备第一面、第二面以及连结第一面和第二面的侧面的元件芯片彼此隔开间隔保持在载体上并且在元件芯片的侧面与第一面所形成的角部使绝缘膜露出的状态。凹陷部形成工序中，在彼此隔开间隔保持在载体上的状态下，将元件芯片暴露于第二等离子体，从而使在角部露出的绝缘膜后退而形成凹陷部。保护膜形成工序中，在彼此隔开间隔保持在载体上的状态下，将元件芯片暴露于供给保护膜形成用气体的同时而产生的第三等离子体，从而在元件芯片的第二面、元件芯片的侧面以及凹陷部形成保护膜。
本发明的电子部件安装构造体的制造方法，是通过本发明的元件芯片的制造方法形成而形成的元件芯片在第一面具备的元件电极通过由元件电极和焊料形成的接合部接合到形成在印刷基板的焊盘电极而成的电子部件安装构造体的制造方法，其具有如下特征。即，包括：焊料膏供给工序，对焊盘电极供给膏状的焊料；和搭载工序，使元件电极安放于供给到对应的焊盘电极的膏状的焊料，从而搭载到印刷基板。进而包括：熔融工序，对印刷基板进行加热而使焊料熔融，从而形成对元件电极和焊盘电极进行焊料接合的接合部；和冷却工序，对印刷基板进行冷却而使熔融的焊料固化。而且，在熔融工序中，形成在凹陷部的保护膜抑制熔融的焊料向侧面爬升。
本发明的电子部件安装构造体，通过焊料将形成在元件芯片的元件电极接合到形成在印刷基板的焊盘电极而成，其具有如下特征。即，元件芯片具有：元件电极，形成在与印刷基板对置的面；凹陷部，形成在元件芯片的侧面的印刷基板侧的角部；和保护膜，被覆凹陷部，通过保护膜阻止焊料向侧面爬升。
根据本发明，能够抑制安装过程中的导电性材料的爬升。
附图说明
图1A是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图1B是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图1C是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图2A是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图2B是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图2C是本发明的一实施方式的元件芯片的制造方法的工序说明图。
图3是本发明的一实施方式的元件芯片的制造方法中使用的等离子体蚀刻装置的结构说明图。
图4A是本发明的一实施方式的元件芯片的制造方法的工序说明中的放大说明图。
图4B是本发明的一实施方式的元件芯片的制造方法的工序说明中的放大说明图。
图4C是本发明的一实施方式的元件芯片的制造方法的工序说明中的放大说明图。
图5A是通过本发明的一实施方式的元件芯片的制造方法制造的元件芯片的结构说明图。
图5B是通过本发明的一实施方式的元件芯片的制造方法制造的元件芯片的结构说明图。
图6A是本发明的一实施方式的电子部件安装构造体的制造方法的工序说明图。
图6B是本发明的一实施方式的电子部件安装构造体的制造方法的工序说明图。
图6C是本发明的一实施方式的电子部件安装构造体的制造方法的工序说明图。
符号说明
1 基板
1a 第一面
1b 第二面
1c 分割区域
2 元件区域
3 元件电极
4 绝缘膜
5 耐蚀刻层
6 载体
10 元件芯片
10a 第一面
10b 第二面
10c 侧面
12a、12a*、12b、12c、12d 保护膜
15 印刷基板
16 焊盘电极
17 焊料
17* 焊料接合部
E 角部
C、C* 凹陷部
具体实施方式
在对本发明的实施方式进行说明之前，简单地对现有装置中的问题点进行说明。
如上述那样，在将WLCSP等元件芯片直接送至电子部件安装工序的情况下，元件芯片以使电路形成面直接接触在接合用的焊糊或银膏等导电性材料上的方式安装。在该安装过程中，有时会出现在搭载元件芯片时，被按压扩展的导电性材料不仅会浸染至电路形成面的接合部位，还浸染至元件芯片的侧面或背面的、所谓“爬升”的情况。这种导电性材料的爬升会成为相邻的电极间的短路或在元件芯片的侧面形成不需要的电路而招致消耗电流的增大等、各种不良的原因。因此，要求抑制这种安装过程中的导电性材料的爬升。
接下来，参照附图对本发明的实施方式进行说明。首先，参照图1A～图1C及图2A～图2C对本实施方式的元件芯片的制造方法进行说明。此处所示的元件芯片的制造方法为，将具备具有以分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖的第一面、和该第一面的相反侧的第二面的基板在分割区域进行分割，来制造多个元件芯片。
如图1A所示，基板1为在第一面1a上形成多个元件芯片10(参照图1C)的晶片状的基板。在基板1中，形成元件部的元件面即第一面1a被由聚酰亚胺等有机膜构成的绝缘膜4覆盖，在第一面1a上设定有以分割区域1c划分的多个元件区域2。在各个元件区域2中，连接用的多个元件电极3以从绝缘膜4突出的方式、或者以至少一部分从设在绝缘膜4上的开口露出的方式形成。基板1被送至用于制造元件芯片的准备工序，如以下说明的那样，进行掩膜形成和载体6的支承。作为载体6，可以示例由切割架保持的切割胶带、或在保持面6a上具备粘接层7的支承基板。
在该准备工序中，如图1B所示，在第二面1b上通过在等离子体切割中具有作为掩膜的功能的抗蚀剂掩模或表面保护膜等形成耐蚀刻层5。即，在第二面1b上，形成耐蚀刻层5，使得覆盖与元件区域2对置的第二面1b的区域且使与分割区域1c对置的第二面1b的区域露出。另外，通过将元件电极3的前端面部分地埋入载体6的粘接层7，从而基板1的第一面1a侧支承在载体6的保持面6a上。此外，准备工序中的掩膜形成可以在载体6的支承之前进行，也可以在载体6的支承之后进行。
这样，在进行了准备工序后，为了对支承在载体6上的基板1实施等离子体处理，载体6被送至等离子体处理工序。对于在该等离子体处理工序中使用的等离子体蚀刻装置20的结构，参照图3进行说明。在图3中，作为真空容器的腔体21的内部为用于进行等离子体处理的处理室21a，在处理室21a的底部配置有载置支承作为处理对象的基板1的载体6的载置台22。在腔体21的顶部的上表面配置了作为上部电极的天线23，天线23与第一高频电源部24电连接。处理室21a内的载置台22还具有作为用于等离子体处理的下部电极的功能，载置台22与第二高频电源部25电连接。
在腔体21上经由排气口21c连接了真空排气部27，通过驱动真空排气部27，处理室21a内被真空排气。而且，处理室21a经由气体导入口21b连接等离子体产生用气体供给部26。在本实施方式所示的等离子体蚀刻装置20中，根据等离子体处理的目的，能够选择性地供给多种等离子体产生用气体。在此，作为等离子体产生用气体的种类，可以选择第一气体26a、第二气体26b、第三气体26c及第四气体26d。
作为第一气体26a，可以使用SF6等、以硅为对象的蚀刻效果优异的气体。在本实施方式中，第一气体26a用于产生通过等离子体蚀刻对基板1进行分割的第一等离子体P1。第二气体26b为氧气，在本实施方式中，以结束掩膜功能后的耐蚀刻层5的除去、用于形成凹陷部C(参照图2A～图2C及图4A～图4C)的绝缘膜4的部分除去等、除去有机膜的目的使用。
第三气体26c为通过等离子体处理形成皮膜的等离子体CVD用的气体，使用包含C4F8、C2F6、CF4、C6F6、C6F4H2、CHF3、CH2F2等氟化碳的气体。在本实施方式中，作为在分割基板1的元件芯片10的侧面、第二面1b、侧面10c、凹陷部C形成保护膜的保护膜形成用气体使用。而且，第四气体26d为保护膜蚀刻用气体，使用SF6气体、氧气或氩气等物理蚀刻效果优异的气体。在本实施方式中，用于除去上述保护膜中不需要的部分的溅射用途。
在等离子体蚀刻装置20的等离子体处理中，首先，将处理对象的基板1与载体6一起载置在载置台22上，驱动真空排气部27对处理室21a内进行真空排气。与此同时，将基于等离子体处理的目的的等离子体产生用气体通过等离子体产生用气体供给部26供给到处理室21a内，并维持为规定压力。而且，通过在该状态下，对天线23由第一高频电源部24供给高频电力，从而产生基于供给到处理室21a内的等离子体产生用气体的种类的等离子体。
此时，通过由第二高频电源部25对作为下部电极的载置台22施加偏置电压，从而能够发挥对处理室21a内产生的等离子体发挥促进向载置台22的方向的入射的偏压作用，能够加强向希望的特定方向的等离子体处理效果并进行各向异性蚀刻。
在等离子体处理工序中，首先，执行使用上述第一气体26a的第一等离子体P1的处理。如图1C所示，通过将基板1的第二面1b暴露于上述的第一等离子体P1，从而，将与未被耐蚀刻层5覆盖的区域、即图1A所示的分割区域1c对应的区域的基板1在该基板1的深度方向上蚀刻至到达第一面1a(参照箭头e)。而且，形成使各个元件芯片10隔开的蚀刻槽11(参照图2A)，将基板1分割成单片的元件芯片10。
即，通过该基板1的分割，具备在基板1的状态下为第一面1a的第一面10a、在基板1的状态下为第二面1b的第二面10b及连结第一面10a和第二面10b的侧面10c的元件芯片10彼此隔开间隔地保持在载体6上。而且，在该分割的同时，形成为在元件芯片10的侧面10c与第一面10a所形成的角部E露出绝缘膜4的端部的状态(分割工序)。
分割工序中的蚀刻条件能够根据基板1的材质适当地选择。在基板1为硅基板的情况下，在分割工序中的蚀刻中可以使用所谓的波希法(Bosch process)。在波希法中，通过依次反复进行沉积膜沉积步骤、沉积膜蚀刻步骤、和硅蚀刻步骤，能够使未被耐蚀刻层5覆盖的区域垂直于基板1的深度方向地掘进。
作为沉积膜沉积步骤的条件，例如，一边以150～250sccm供给C4F8作为原料气体，一边将处理室内的压力调整为15～25Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为0W，将处理时间设为5～15秒即可。作为沉积膜蚀刻步骤的条件，例如，一边以200～400sccm供给SF6作为原料气体，将处理室内的压力调整为5～15Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为100～300W，将处理时间设为2～10秒即可。在此，sccm为表示气体的流量的单位。即，1sccm为在0℃下，在1分钟内流过1cm3的1气压(标准状态)的气体的流量。
作为硅蚀刻步骤的条件，例如，一边以200～400sccm供给SF6作为原料气体，一边将处理室内的压力调整为5～15Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为50～200W，将处理时间设为10～20秒即可。而且，在这些条件中，通过反复进行沉积膜沉积步骤、沉积膜蚀刻步骤、及硅蚀刻步骤，从而能够以10μm/分钟的速度掘进硅基板。
然后，在上述的分割工序之后，在彼此隔开间隔地保持在载体6上的状态下，将元件芯片10暴露于第二等离子体P2。即，如图2A所示，在等离子体蚀刻装置20中，在处理室21a内产生使用第二气体26b的第二等离子体P2(灰化用等离子体)，通过灰化除去以树脂为主成分的耐蚀刻层5。由此，成为暴露出分割成单片的元件芯片10的第二面10b的状态。
与此同时，在该第二等离子体的等离子体处理中，通过用灰化部分地除去在角部E露出的由有机膜构成的绝缘膜4并使其后退，在角部E形成凹陷部C(凹陷部形成工序)。由此，如图4A所示，在元件芯片10中，通过在第一面10a与侧面10c所形成的角部E，部分地除去从蚀刻槽11(参照图2A)露出的绝缘膜4的端部并后退，从而形成凹陷部C。
这样，通过使用聚酰亚胺等有机膜作为绝缘膜4，能够通过等离子体处理的灰化等比较简单的方法形成凹陷部C。此外，也可以仅通过第一等离子体进行作为用于在角部E形成凹陷部C的凹陷部形成工序的等离子体处理。在该情况下，通过使用第一等离子体的等离子体处理，接着上述分割工序进行凹陷部形成。
灰化的条件能够根据耐蚀刻层5的材料恰当地选择。例如，在耐蚀刻层5为抗蚀膜的情况下，作为原料气体，一边供给150～300sccm氧气、0～50sccmCF4，一边将处理室内的压力调整为5～15Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为0～30W即可。在该条件下，可以以1μm/分钟左右的速度除去耐蚀刻层5、绝缘膜4。
接下来，在上述凹陷部形成工序之后，如图2B所示，执行保护膜形成工序。即，在等离子体蚀刻装置20中，在彼此隔开间隔地保持在载体6上的状态下，将元件芯片10暴露于一边在处理室21a内供给作为保护膜形成用气体(包含氟化碳的气体)的第三气体26c一边产生的第三等离子体P3中。由此，如图4B所示，在元件芯片10的第二面10b、侧面10c上分别形成保护膜形成用气体中的氟化碳在等离子体中被分解，其后沉积并被膜化的、由以包含氟和碳的碳氟化合物为主成分的膜构成的保护膜12b、12c。与此同时，在通过凹陷部形成工序形成的凹陷部C内，也以同样组成的保护膜12a填充凹陷部C内的方式形成。
由于形成在凹陷部C内的保护膜12a以抑制将元件芯片10直接接合在封装基板等上的安装过程中的导电性材料的爬升为目的形成，因此，优选吸湿性少且组成致密的保护膜。在本实施方式中，由于使用包含氟化碳的保护膜形成用气体作为用于这些保护膜的形成的第三等离子体P3的原料气体，因此，能够形成吸湿性少组成致密且粘着性优异的由碳氟化合物膜构成的保护膜。此外，在该保护膜形成工序中，对载置载体6的载置台22(参照图3)施加高频偏压。由此，促进向元件芯片10的离子的入射，能够形成更为致密且粘着性高的保护膜。
作为保护膜的形成条件，例如，作为原料气体，一边供给150sccm的C4F8、50sccm的He，一边将处理室内的压力调整为15～25Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为50～150W即可。在该条件下，通过进行300秒的处理，从而能够形成厚度3μm的保护膜。在本实施方式中，作为原料气体，使用氟化碳与氦气的混合气体，这是因为，通过混合氦气，从而能够促进等离子体中的原料气体的离解，作为其结果，能够形成致密且粘着性高的保护膜。
此外，在上述的条件例中，He流量相对原料气体的全流量的比率为25％(＝50/(150+50)×100)。如以下说明的那样，该比率优选为10％～80％之间。即，若He流量相对原料气体的全流量的比率大于10％，则容易促进等离子体中的原料气体的离解，作为其结果，更容易形成致密且粘着性高的保护膜。另一方面，若He流量相对原料气体的全流量的比率大于80％，则由于原料气体中C4F8所占的比率减少，因此，有助于保护膜形成的等离子体中的成分(C、F及这些化合物)向基板表面的供给不足，基板表面中的保护膜的沉积速度变缓，生产性降低。
接下来，执行用于除去通过保护膜形成工序形成的保护膜中不需要的部分的保护膜除去工序。在上述的保护膜形成工序中，也在侧面10c及第二面10b上与元件芯片10的第一面10a中的凹陷部C一起形成保护膜12b(参照图4B)。在本实施方式中，由于不需要这些保护膜12b，12c，因此，进行使用用于除去这些保护膜的第四等离子体P4的等离子体处理。
即，在等离子体蚀刻装置20中，在处理室21a内，一边供给作为以氩气、氧气为成分的保护膜蚀刻用气体的第四气体26d一边产生第四等离子体P4。而且，如图2C所示，在彼此隔开间隔地保持在载体6上的状态下，将元件芯片10暴露于第四等离子体P4中。由此，一边残留形成在凹陷部C内的保护膜12a的至少一部分，一边通过第四等离子体P4的蚀刻作用除去元件芯片10中暴露在上表面的第二面10b上所形成的保护膜12b、和形成在侧面10c上的保护膜12c。
由此，如图4C所示，元件芯片10的第二面10b及侧面10c为暴露出的状态，也除去附着在载体6的上表面上的保护膜中、元件芯片10上未覆盖的范围的保护膜12d(参照图2B)。由此，在保护膜除去工序后的元件芯片10中，成为仅在凹陷部C内残留保护膜12a的状态。
作为保护膜除去的条件，例如，作为原料气体，一边供给150～300sccm的Ar、0～150sccm的O2，一边将处理室内的压力调整为0.2～1.5Pa，将从第一高频电源部24向天线23的投入电力设为1500～2500W，将从第二高频电源部25向下部电极的投入电力设为150～300W即可。在该条件下，能够以0.5μm/分钟左右的速度对暴露在上表面的保护膜进行蚀刻。
图5A及图5B表示通过这种制造过程制造的元件芯片10。即，如图5A所示，元件芯片10具有被绝缘膜4覆盖的第一面10a，在第一面10a上形成有从绝缘膜4突出的元件电极3。在第一面10a与侧面10c所形成的角部E，设有覆盖通过绝缘膜4后退形成的凹陷部C的保护膜12a。
此外，图5B表示在形成凹陷部C的过程中，形成不仅除去了绝缘膜4还部分地除去了在元件芯片10的侧面10c与绝缘膜4的端部相邻的元件芯片10的凹陷部C*的示例。即，在第一面10a与侧面10c形成的角部E，通过绝缘膜4后退，并且在侧面10c部分地除去与绝缘膜4的端部相邻的区域，从而形成凹陷部C*。而且，凹陷部C*与图5A所示的例同样地被保护膜12a*覆盖。
具有这种结构的元件芯片10如以下说明的那样，在不经树脂封装等工序，通过焊料接合直接安装在印刷基板等上形成电子部件安装构造体的情况下，具有抑制第一面10a中的焊糊等导电性材料的浸润扩展，防止导电性材料的爬升的效果。
以下，参照图6A～图6C，对将通过上述的元件芯片的制造方法形成的元件芯片10焊料接合在形成在印刷基板上的焊盘电极而成的电子部件安装构造体及电子部件安装构造体的制造方法进行说明。在图6A中，在印刷基板15的上表面，与上述结构的元件芯片10的连接用的元件电极3对应地形成焊盘电极16。在焊盘电极16上搭载元件芯片10之前，供给膏状的焊料17(或者焊料膏)(焊料膏供给工序)。
在焊料膏供给工序后的印刷基板15上搭载元件芯片10(搭载工序)。即使元件芯片10的元件电极3与对应的焊盘电极16对位，如图6B所示，使元件电极3安放在焊盘电极16上的焊料17中。由此，元件芯片10搭载在印刷基板15上。
接下来，搭载工序后的印刷基板15被送至回流焊工序，在此，进行用于焊料的接合的加热。即，对印刷基板15进行加热，使焊料17熔融，将元件电极3和焊盘电极16焊料接合在一起(熔融工序)。然后，其后，对印刷基板15进行冷却，使熔融的焊料冷却固化(冷却工序)。由此，如图6C所示，形成通过焊料使元件电极3和焊盘电极16接合在一起的焊料接合部17*。
这样，形成通过焊料17将形成在元件芯片10上的元件电极3接合在形成在印刷基板15上的焊盘电极16上而成的电子部件安装构造体。在该电子部件安装构造体中，元件芯片10具有：形成在与印刷基板15对置的面上的元件电极3、形成在元件芯片10的侧面的印刷基板15侧的角部E上的凹陷部C、和被覆凹陷部C的保护膜12a。而且，通过保护膜12a阻止焊料17向侧面10c的爬升。
即，在凹陷部C中，由于残留有保护膜12a，因此，在熔融工序中使焊料17熔融的熔融焊料与保护膜12a接触。由碳氟化合物膜构成的保护膜12a的表面性状具有抑制熔融焊料的浸润扩展的特性。据此，在熔融工序中使焊料17熔融的熔融焊料不沿第一面10a扩展地在元件电极3与焊盘电极16的周围冷却固化，形成良好的焊料接合部17*。即，在上述的熔融工序中，形成在凹陷部C的保护膜12a抑制熔融的焊料17向侧面10c的爬升。
由此，在将元件芯片10经由焊料17等导电性材料接合在印刷基板15等安装对象物上的安装过程中，能够排除可能会因焊料17向侧面10c的爬升而产生的各种不良的原因而提高安装品质。例如能够排除相邻的电极间的短路、或在元件芯片10的侧面10c形成不需要的电路引起的消耗电流的增大等而提高安装品质。
本发明的元件芯片的制造方法及电子部件安装构造体的制造方法以及电子部件安装构造体具有能够抑制安装过程中的导电性材料的爬升这一效果，在按照每一元件区域对具有多个元件区域的基板进行分割来制造元件芯片的领域中是有用的。

Claims (8)

1.一种元件芯片的制造方法，将具备第一面和所述第一面的相反侧的第二面的基板在分割区域进行分割来制造多个元件芯片，所述第一面具有用所述分割区域划分的多个元件区域且至少其一部分被绝缘膜覆盖，所述元件芯片的制造方法包括：
准备工序，准备所述基板，所述基板的所述第一面侧被载体支承，并且所述基板形成有耐蚀刻层，使得覆盖与所述元件区域对置的所述第二面的区域且使与所述分割区域对置的所述第二面的区域露出；和
等离子体处理工序，在所述准备工序之后，对支承在所述载体上的所述基板实施等离子体处理，
所述等离子体处理工序包括：
分割工序，将所述第二面暴露于第一等离子体，从而将未被所述耐蚀刻层覆盖的区域的所述基板在该基板的深度方向上蚀刻至到达所述第一面而将所述基板分割为元件芯片，并成为具备所述第一面、所述第二面以及连结所述第一面和所述第二面的侧面的元件芯片彼此隔开间隔保持在所述载体上并且在所述元件芯片的所述侧面与所述第一面所形成的角部使所述绝缘膜露出的状态；
凹陷部形成工序，在所述分割工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于第二等离子体，从而使在所述角部露出的所述绝缘膜后退而形成凹陷部；
保护膜形成工序，在所述凹陷部形成工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于供给保护膜形成用气体的同时而产生的第三等离子体，从而在所述元件芯片的所述第二面、所述元件芯片的所述侧面以及所述凹陷部形成保护膜。
2.根据权利要求1所述的元件芯片的制造方法，还包括：保护膜除去工序，在所述保护膜形成工序之后，在彼此隔开间隔保持在所述载体上的状态下，将所述元件芯片暴露于第四等离子体，从而在使形成在所述凹陷部的所述保护膜的至少一部分残留的同时除去形成在所述元件芯片的所述第二面和所述侧面的所述保护膜。
3.根据权利要求1所述的元件芯片的制造方法，所述绝缘膜为有机膜。
4.根据权利要求1所述的元件芯片的制造方法，所述保护膜是以碳氟化合物为主成分的膜。
5.根据权利要求4所述的元件芯片的制造方法，所述保护膜形成用气体包含氟化碳。
6.一种电子部件安装构造体的制造方法，所述电子部件安装构造体是将利用权利要求1～5中的任一项所述的元件芯片的制造方法而形成的元件芯片在所述第一面具备的元件电极通过由所述元件电极和焊料形成的接合部接合到形成在印刷基板的焊盘电极而成的，所述电子部件安装构造体的制造方法包括：
焊料膏供给工序，对所述焊盘电极供给膏状的焊料；
搭载工序，使所述元件电极安放于供给到对应的所述焊盘电极的膏状的焊料，从而搭载到所述印刷基板；
熔融工序，对所述印刷基板进行加热而使所述焊料熔融，从而形成对所述元件电极和焊盘电极进行焊料接合的接合部；和
冷却工序，对所述印刷基板进行冷却而使熔融的所述焊料固化，
在所述熔融工序中，形成在所述凹陷部的所述保护膜抑制熔融的焊料向所述侧面爬升。
7.一种电子部件安装构造体，通过焊料将形成在元件芯片的元件电极接合到形成在印刷基板的焊盘电极而成，
所述元件芯片具有：所述元件电极，形成在与所述印刷基板对置的面；凹陷部，形成在所述元件芯片的侧面的所述印刷基板侧的角部；和保护膜，被覆所述凹陷部，
通过所述保护膜阻止所述焊料向所述侧面爬升。
8.根据权利要求7所述的电子部件安装构造体，所述保护膜是以碳氟化合物为主成分的膜。
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