JP2008529258A - 半導体チップの製造方法 - Google Patents
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Abstract
Description
プラズマ中のイオンにより当該露呈された絶縁膜上に電荷を帯電させた状態にて、上記プラズマエッチングを継続して行うことで、上記各々の素子形成領域において上記絶縁膜に接するそれぞれの角部の除去を行い、
その後、当該露呈された絶縁膜を除去して、上記各々の素子形成領域を個別に分割し、その結果、個片化された上記半導体素子を含む半導体チップを製造する半導体チップの製造方法を提供する。
プラズマ中のイオンにより上記露呈された絶縁膜上に電荷を帯電させた状態にて、上記プラズマエッチングを継続して行うことで、上記各々の素子形成領域において上記絶縁膜に接するそれぞれの角部の除去を行いながら、当該露呈された絶縁膜の除去を行い、上記各々の素子形成領域を個別に分割し、その結果、個片化された上記半導体素子を含む半導体チップを製造する半導体チップの製造方法を提供する。
プラズマ中のイオンにより当該露呈された絶縁性保護シート上に電荷を帯電させた状態で、上記プラズマエッチングを継続して行うことで、当該それぞれの半導体チップにおいて上記絶縁性保護シートに接するそれぞれの角部の除去を行う半導体チップの製造方法を提供する。
上記方形状の上記一方の面における全ての稜線が除去されている半導体チップを提供する。
(プラズマ処理装置の構成)
本発明の第1の実施形態にかかる半導体チップの製造方法において半導体ウェハの分割に用いられるプラズマ処理装置101の構成を模式的に示す模式構成図を図1に示す。なお、図1は、プラズマ処理装置101の縦断面を示す模式構成図である。このプラズマ処理装置101は、複数の半導体素子が回路形成面(第1の面)に形成された半導体ウェハを半導体素子を含む半導体チップの個片に分割することで、それぞれの半導体チップを製造する装置である。
次にこのような構成を有するプラズマ処理装置101における制御系の構成について、図4に示す制御系のブロック図を用いて以下に説明する。
次に、本第1実施形態において用いられるプラズマエッチング処理方法の原理について、図5及び図6に示す半導体ウェハ6における分割領域付近の部分拡大模式説明図を用いて以下に説明する。
次に、このような構成を有するプラズマ処理装置101を用いて行われる半導体チップの製造方法およびこの半導体チップの製造方法の過程において実行される半導体ウェハの分割方法(プラズマダイシング処理)について、以下に説明する。また、半導体ウェハの分割方法おける一連の手順を示すフローチャートを図7に示し、さらに、半導体チップの製造方法における一連の処理内容を説明するための模式説明図を図8A〜図8E及び図9A〜図9Eに示し、これらの図面を主に参照しながら以下に説明を行う。
なお、本発明は上記実施形態に限定されるものではなく、その他種々の態様で実施できる。例えば、本発明の第2の実施形態にかかる半導体チップの製造方法について、図13A〜図13E及び図14A〜図14Dに示す模式説明図を用いて以下に説明する。
次に、本発明の第3の実施形態にかかる半導体チップの製造方法について、図16A〜図16E及び図17A〜図17Dに示す模式説明図を用いて以下に説明する。本第3実施形態の半導体チップの製造方法においては、上記第1実施形態及び上記第2実施形態とは異なり、絶縁性を有する保護シートを、分割領域R2に配置される絶縁膜として用いて、ノッチ形成等を行うものである。なお、以降においては、この異なる点についてのみ説明を行うものとする。また、本第3実施形態に半導体チップの製造方法は、上記第1実施形態において用いられたプラズマ処理装置101において行うことができる。従って、プラズマ処理装置101の構成等の説明については省略するものとする。
本発明は、添付図面を参照しながら好ましい実施形態に関連して充分に記載されているが、この技術の熟練した人々にとっては種々の変形や修正は明白である。そのような変形や修正は、添付した請求の範囲による本発明の範囲から外れない限りにおいて、その中に含まれると理解されるべきである。
2005年1月24日に出願された日本国特許出願No.2005−15362号の明細書、図面、及び特許請求の範囲の開示内容は、全体として参照されて本明細書の中に取り入れられるものである。
Claims (9)
- 分割領域により画定される複数の素子形成領域内に配置された半導体素子と、上記分割領域に配置された絶縁膜とがその第1の面において形成され、当該第1の面とは反対側の面である第2の面に当該分割領域を画定するためのマスクが配置された半導体ウェハに対して、上記第2の面よりプラズマエッチングを施すことにより、上記分割領域に相当する部分を除去してエッチング底部より上記絶縁膜を露呈させ、
プラズマ中のイオンにより当該露呈された絶縁膜上に電荷を帯電させた状態にて、上記プラズマエッチングを継続して行うことで、上記各々の素子形成領域において上記絶縁膜に接するそれぞれの角部の除去を行い、
その後、当該露呈された絶縁膜を除去して、上記各々の素子形成領域を個別に分割し、その結果、個片化された上記半導体素子を含む半導体チップを製造する半導体チップの製造方法。 - 上記除去される上記露呈された絶縁膜は、上記半導体ウェハの上記第1の面において酸化シリコン(SiO2)により形成された膜である請求項1に記載の半導体チップの製造方法。
- 上記除去される上記露呈された絶縁膜は、上記半導体ウェハの上記第1の面において形成された上記それぞれの半導体素子の表面を保護するようにポリイミド(PI)により形成された表面保護膜である請求項1に記載の半導体チップの製造方法。
- 分割領域により画定される複数の素子形成領域内に配置された半導体素子と、上記分割領域に配置された絶縁膜とがその第1の面において形成され、当該第1の面とは反対側の面である第2の面に当該分割領域を画定するためのマスクが配置された半導体ウェハに対して、上記第2の面よりプラズマエッチングを施すことにより、上記分割領域に相当する部分を除去してエッチング底部より上記絶縁膜を露呈させ、
プラズマ中のイオンにより上記露呈された絶縁膜上に電荷を帯電させた状態にて、上記プラズマエッチングを継続して行うことで、上記各々の素子形成領域において上記絶縁膜に接するそれぞれの角部の除去を行いながら、当該露呈された絶縁膜の除去を行い、上記各々の素子形成領域を個別に分割し、その結果、個片化された上記半導体素子を含む半導体チップを製造する半導体チップの製造方法。 - 上記除去される上記露呈された絶縁膜は、上記半導体ウェハの上記第1の面において形成された上記それぞれの半導体素子の表面を保護するように窒化シリコン(Si3N4)により形成された表面保護膜である請求項4に記載の半導体チップの製造方法。
- 分割領域により画定される複数の素子形成領域内に配置された半導体素子が形成されたその第1の面に、絶縁性を有する保護シートが貼り付けられて、当該第1の面とは反対側の面である第2の面に当該分割領域を画定するためのマスクが配置された半導体ウェハに対して、上記第2の面よりプラズマエッチングを施すことにより、上記分割領域に相当する部分を除去してエッチング底部より上記絶縁性保護シートを露呈させて、上記各々の素子形成領域を個別に分割し、その結果、個片化された上記半導体素子を含む半導体チップを製造し、
プラズマ中のイオンにより当該露呈された絶縁性保護シート上に電荷を帯電させた状態で、上記プラズマエッチングを継続して行うことで、当該それぞれの半導体チップにおいて上記絶縁性保護シートに接するそれぞれの角部の除去を行う半導体チップの製造方法。 - 上記プラズマエッチングを継続して行うことで、上記半導体チップの上記それぞれの角部の除去を行った後、上記半導体ウェハの上記第1の面より上記絶縁性保護シートを剥離して除去する請求項6に記載の半導体チップの製造方法。
- 複数の半導体素子がその一方の面に形成された半導体ウェハを当該半導体素子の個片に分割して得られる略方形状を有する半導体チップであって、
上記方形状の上記一方の面における全ての稜線が除去されている半導体チップ。 - 上記方形状の上記一方の面における上記それぞれの稜線に相当する部分において、湾曲凸面部が形成されている請求項8に記載の半導体チップ。
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