CN107180754A - 等离子体处理方法 - Google Patents
等离子体处理方法 Download PDFInfo
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- CN107180754A CN107180754A CN201710091515.0A CN201710091515A CN107180754A CN 107180754 A CN107180754 A CN 107180754A CN 201710091515 A CN201710091515 A CN 201710091515A CN 107180754 A CN107180754 A CN 107180754A
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Abstract
提供一种等离子体处理方法,能够以简易的工序实现精细的图案化。等离子体处理方法包括:粘附工序,在具备第一主面和第一主面的相反侧的第二主面的基板的第一主面粘附树脂膜;以及图案化工序,对树脂膜进行图案化,从而形成具有使基板的被处理区域露出的开口部的掩模。而且,等离子体处理方法包括:第一等离子体工序,在包含第一气体的减压环境中生成第一气体的第一等离子体,并使掩模暴露于第一等离子体,从而减少掩模与第一主面之间的空隙。进而,等离子体处理方法包括:第二等离子体工序,在包含第二气体的环境中用第二气体生成第二等离子体,并使从开口部露出的被处理区域暴露于第二等离子体,从而对被处理区域进行蚀刻。
Description
技术领域
本公开涉及组合了对粘附在基板的主面的树脂膜进行图案化的工序和对基板进行等离子体处理的工序的等离子体处理方法。
背景技术
使用了层压掩模(例如,干膜抗蚀剂)的图案化用于简化半导体电路、电子电路等的制造工序,在多方面要求应用该图案化。但是,在将层压掩模粘附到基板的主面的工序中,在层压掩模与基板的主面之间容易介入空气,会不可避免地形成微小的空隙(参照专利文献1)。为了减少这种现象,需要在高度减压的环境中进行粘附工序,但是这会导致成本的上升、工序的复杂化。此外,层压掩模其本身在表面就具有微小的凹凸,在基板的主面也可能存在微小的凹凸。因此,原理上难以避免在层压掩模与基板的主面之间形成空隙的现象。
在不要求精细的蚀刻的领域中,层压掩模与基板的主面之间的微小的空隙不会成为问题。但是,在要求精细的蚀刻的情况下,在存在空隙的区域中,将成为掩模的至少一部分从基板的主面上浮的状态。因此,在后续的蚀刻工序中,基板的额外的部分会被蚀刻,容易产生最终产品的不良。
现有技术文献
专利文献
专利文献1:日本特开平3-141358号公报
发明内容
本公开涉及的发明的目的在于,以简易的工序、用精细的图案对基板进行蚀刻。
本公开涉及的发明的一个方面涉及等离子体处理方法,包括以下的工序。即,该等离子体处理方法包括:粘附工序,在具备第一主面和第一主面的相反侧的第二主面的基板的第一主面粘附树脂膜;以及图案化工序,对树脂膜进行图案化,从而形成具有使基板的被处理区域露出的开口部的掩模。此外,等离子体处理方法包括:第一等离子体工序,在包含第一气体的减压环境中生成第一气体的第一等离子体,并使掩模暴露于所述第一等离子体,从而减少掩模与第一主面之间的空隙。进而,等离子体处理方法包括:第二等离子体工序,在包含第二气体的环境中用第二气体生成第二等离子体,并使从开口部露出的被处理区域暴露于第二等离子体,从而对被处理区域进行蚀刻。
发明效果
根据本公开涉及的发明的等离子体处理方法,即使在将树脂膜粘附到基板的主面时有微小的空隙介于树脂膜与基板的主面之间的情况下,也能够用精细的图案对基板进行蚀刻。
附图说明
图1是示意性地示出在本公开的实施方式涉及的等离子体处理方法中使用的等离子体处理装置的一个例子的构造的概略剖视图。
图2A是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图2B是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图2C是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图2D是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图2E是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图2F是示意性地示出本公开的实施方式涉及的等离子体处理方法的一个工序的工序图。
图3A是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
图3B是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
图3C是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
图3D是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
图3E是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
图3F是示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的一个工序的工序图。
符号说明
10、10A:基板(半导体基板)
10S、10Sa:第一主面
10R:第二主面
R1:元件区域
R2:被处理区域
11、11A:元件芯片
20:运输载体
21:框架
22:保持片
23:空隙
24:凹部
30:树脂膜
30M:掩模
30W:开口部
200:等离子体处理装置
203:真空腔
203a:气体导入口
203b:排气口
208:电介质构件
209:天线
210A:第一高频电源
210B:第二高频电源
211:载置台
212:工艺气体源
213:灰化气体源
214:减压机构
215:电极层
216:金属层
217:基台
218:外周部
219:ESC电极
220:高频电极部
221:升降杆
222:支承部
223A、223B:升降机构
224:盖
224W:窗部
225:冷媒循环装置
226:直流电源
227:冷媒流路
228:控制装置
229:外周环
具体实施方式
本公开的实施方式涉及的等离子体处理方法包括在具备第一主面及其相反侧的第二主面的基板的第一主面粘附树脂膜的工序(粘附工序)。粘附工序并不是涂敷液体状的抗蚀剂而形成树脂层的工序,而是将预先准备的树脂膜粘附到基板的第一主面的工序。此时,在树脂膜与第一主面之间可能会形成微小的空隙,但是能够在后续的第一等离子体工序中使空隙减少,因此无需在减压环境中进行粘附工序。
树脂膜只要具有能够附着到基板的第一主面的粘接性即可,树脂膜的种类、构造等没有特别限定。树脂膜可以只包括具有粘接性的粘接层,但是为了提高操作性,也可以具有基材片。通常,使用保持在基材片的粘接层,在将粘接层粘附到基板的第一主面之后,可剥掉基材片。在该情况下,树脂膜仅由粘接层构成。
树脂膜可以使用将聚乙烯醇(PVA)、丙烯酸系糊剂等作为基底材料的不具有感光性的粘接层,也可以使用具有感光性的粘接层(抗蚀剂层)。其中,尤其是保持在基材片的抗蚀剂层(干膜抗蚀剂),因为各种种类在市面上均有销售,所以能够容易地得到。
基材片例如可使用聚酯膜。在是市面上销售的干膜抗蚀剂的情况下,粘接层具有被覆盖膜覆盖的三层构造。覆盖膜例如可使用聚乙烯膜。另外,关于基材片的材质,除了上述的聚酯以外,也可以是聚氯乙烯(PVC)、聚乙烯、聚对苯二甲酸乙二醇酯等。
作为蚀刻的对象的基板可以是各种电路构件,因此没有特别限定,可举出像硅晶片那样的半导体基板、像可挠性印刷基板那样的树脂基板、陶瓷基板等。作为构成半导体基板的半导体,例如可举出硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。
半导体基板可以在其第一主面具有电路层。电路层至少包括绝缘膜,除此以外,还可以包括金属材料、树脂保护层、电极焊盘等。也可以作为与布线用的金属材料的层叠体(多层布线层)而包括绝缘膜。绝缘膜例如包含二氧化硅(SiO2)、氮化硅(Si3N4)、低介电常数膜(Low-k膜)、聚酰亚胺等的树脂膜、钽酸锂(LiTaO3)、铌酸锂(LiNbO3)等。
接下来,进行对树脂膜进行图案化而在树脂膜形成使基板的被处理区域露出的开口部的工序(图案化工序)。图案化工序是用树脂膜形成具有开口部的掩模的工序,其方法没有特别限定。
在使用干膜抗蚀剂的情况下,在图案化工序中,例如可以通过湿式蚀刻除去树脂膜的与掩模的开口部对应的部分。湿式蚀刻是如下的工序,即,在用所希望的图案对粘附在基板的第一主面的树脂膜或抗蚀剂层进行曝光之后,将抗蚀剂层浸在蚀刻液中而形成具有开口部的掩模。抗蚀剂层的类型可以是正型,也可以是负型。
在使用不具有感光性的树脂膜或粘接层的情况下,在图案化工序中,例如可以利用激光进行划刻而除去树脂膜或粘接层的与掩模的开口部对应的部分。
接下来,在具有通过图案化形成的掩模的基板的周围形成包含第一气体的减压环境。接下来,进行如下工序(第一等离子体工序),即,生成第一气体的第一等离子体,并使掩模暴露于第一等离子体,从而减少掩模与第一主面之间的空隙。通过使掩模在减压环境中暴露于第一等离子体,从而空气至少会从存在于掩模的开口部的附近的空隙内流出,可矫正掩模从基板的第一主面的上浮。由此,可提高基板的第一主面与掩模的密接性。因而,在后续的蚀刻工序中,可抑制基板的额外的部分的蚀刻,能够进行精细的蚀刻。如果在掩模在掩模的开口部的附近从基板的第一主面上浮的状态下进行蚀刻,则在第一主面的与掩模分离的部分也会进行蚀刻,难以进行精细的蚀刻。
在第一等离子体工序中,优选使掩模的至少一部分软化。由此,可进一步提高基板的第一主面与掩模的密接性。为此,可以用第一等离子体对掩模进行加热,直至掩模的至少一部分达到软化温度以上。在掩模为粘接层或抗蚀剂层的情况下,希望控制第一等离子体对掩模进行加热,使得掩模的温度为60℃~110℃,优选为80℃~100℃。根据需要,也可以对第一等离子体施加朝向基板的方向的偏置。
第一气体优选不具有化学作用。因而,第一气体优选包含选自由氩、氧、氮以及氦构成的组的至少一种。此时,包含第一气体的减压环境的压力例如可以为0.1Pa~100Pa,优选为0.5Pa~20Pa。
接下来,在第一等离子体处理后的基板的周围形成包含第二气体的环境。接下来,进行如下工序(第二等离子体工序),即,用第二气体生成第二等离子体,并使从开口部露出的被处理区域暴露于第二等离子体,从而对被处理区域进行蚀刻。此时,在相同的空间内连续进行第一等离子体工序和第二等离子体工序将更有效,是优选的。第一等离子体工序和第二等离子体工序例如在干式蚀刻装置具备的腔的内侧的处理空间中进行。
第二气体可以与第一气体相同,也可以不同。即,可以用与第一等离子体相同的条件产生第二等离子体。但是,通常减少掩模与第一主面之间的空隙所需的第一等离子体的条件与对被处理区域进行蚀刻所需的第二等离子体的条件不同。第二气体的种类、压力、第二等离子体的条件等可根据进行蚀刻的基板的种类适宜地进行选择。
在第二等离子体工序中,例如利用第二等离子体将被处理区域从第一主面蚀刻至第二主面,从而将基板单片化。这样的工序适合于例如使用干式蚀刻装置的半导体基板的等离子体切割。
以下,参照附图对本发明的实施方式涉及的等离子体处理方法的一个例子进行说明。首先,参照图1对进行第一等离子体工序和第二等离子体工序时使用的等离子体处理装置的一个例子进行说明。但是,等离子体处理装置不限定于此。
等离子体处理装置200具备真空腔203,在真空腔203的内侧的处理空间具备载置台211。在真空腔203设置有气体导入口203a和排气口203b。在气体导入口203a分别连接有工艺气体源212和灰化气体源213。在排气口203b连接有减压机构214,减压机构214包括对真空腔203内的气体进行排气而进行减压的真空泵。
在载置台211载置保持在运输载体20的基板10。运输载体20由环状的框架21和保持片22构成,框架21对保持片22的周围进行固定。保持片22具有用于粘附基板10的第二主面的粘接面。在载置台211的外周配置有通过升降机构223A进行升降驱动的多个支承部222,搬入到真空腔203内的运输载体20交接给支承部222,并搭载到载置台211上。
在载置台211的上方配置有至少覆盖框架21并且具有使基板10露出的窗部224W的盖224。盖224与多个升降杆221连结,并通过升降机构223B进行升降驱动。真空腔203的上部被电介质构件208封闭,在电介质构件208的上方作为上部电极而配置有天线209。天线209与第一高频电源210A连接。
载置台211具备从上方依次配置的电极层215、金属层216以及基台117,它们被外周部218包围,在外周部218的上表面配置有保护用的外周环229。在电极层215的内部配置有静电吸附用的电极部(ESC电极)219和与第二高频电源210B连接的高频电极部220。ESC电极219与直流电源226连接。通过对高频电极部220施加高频电力,从而能够一边施加偏置电压一边进行第一等离子体工序和/或第二等离子体工序。在金属层216内形成有用于冷却载置台211的冷媒流路227,冷媒通过冷媒循环装置225进行循环。
控制装置228对包括第一高频电源210A、第二高频电源210B、工艺气体源212、灰化气体源213、减压机构214、冷媒循环装置225、升降机构223A、升降机构223B以及静电吸附机构的等离子体处理装置200的动作进行控制。
接下来,参照图2所示的示意性的方案对本发明的实施方式涉及的等离子体处理方法的一个例子进行说明。在此,对作为基板而使用硅晶片那样的半导体基板且在第二等离子体工序中将半导体基板单片化的情况进行说明。但是,本发明涉及的等离子体处理方法不限定于此。
首先,准备半导体基板10(图2A)。半导体基板10具备多个元件区域R1和划分多个元件区域R1的被处理区域R2。半导体基板10的第一主面10S的相反侧的第二主面10R可以从该时间点起就粘附到运输载体20的保持片22,但是是否粘附到保持片22是任意的。半导体基板10可以是保持在保持片22的状态,也可以不保持在保持片22。
半导体基板10的大小没有特别限定,例如最大直径为50mm~300mm左右。半导体基板10的形状也没有特别限定,例如是圆形、方形。绝缘膜或多层布线层的厚度没有特别限定,例如是2~10μm。可以在半导体基板10设置定向平面(orientation flat)、凹口等缺口(均未图示)。可以在元件区域R1的表面形成半导体电路、电子部件元件、MEMS等的电路层(均未图示)。
接下来,进行在半导体基板10的第一主面10S粘附树脂膜30的工序(图2B)。树脂膜30其本身在表面具有微小的凹凸,在半导体基板10的主面10S也可能存在微小的凹凸。因此,在树脂膜30与半导体基板10的第一主面10S之间会不可避免地形成空隙23。在第一主面10S粘附树脂膜30的工序无需在减压环境中进行,但是也可以在例如0.1Pa~100Pa左右的减压环境中进行。
接下来,进行用树脂膜30形成具有使半导体基板10的被处理区域R2露出的开口部30W的掩模30M的图案化工序(图2C)。在树脂膜30具有基材片和粘接层的情况下,可以在将树脂膜30粘附到基板的第一主面之后剥掉基材片,仅用粘接层形成掩模30M。
在图案化工序中,树脂膜或粘接层30中的覆盖被处理区域R2的部分被除去,从而形成开口部30W。在图案化工序中,例如,利用激光进行划刻,从而可除去树脂膜30的覆盖被处理区域R2的部分。另外,如果是半导体基板10未保持在保持片22的状态,则也可以在用给定的图案对树脂膜30进行曝光之后进行用蚀刻液进行显影的湿式蚀刻工序。
通过图案化工序,形成在元件区域R1覆盖第一主面10S且在被处理区域R2使第一主面10S露出的掩模30M。掩模30M的厚度例如能够设为5μm~80μm。被处理区域R2的最小宽度(即,开口部30W的最小宽度)取决于掩模的厚度、掩模的种类、图案化方法等,例如为20μm~40μm。
接下来,具有掩模30M的半导体基板10以保持在运输载体20的保持片22的状态搬入到如图1所示的等离子体处理装置具备的真空腔203的内侧的处理空间,并载置到载置台211上。
(第一等离子体工序)
接下来,从工艺气体源212经由气体导入口203a对真空腔203内的处理空间导入第一气体。第一气体的组成没有特别限定,但是例如优选为氩气。
当对ESC电极219供给电力时,保持片22密接于载置台211。接下来,当从第一高频电源210A对隔着电介质构件208配置在上部的天线209供给电力时,会生成磁场,由第一气体生成第一等离子体。此时,处理空间内的压力可以设定为例如0.1Pa~100Pa。通过在减压环境中利用第一等离子体对掩模30M进行加热,从而如图2D所示,介于掩模30M与半导体基板10的第一主面10S之间的空隙减少或被除去,可提高掩模30M与第一主面10S的密接性。
(第二等离子体工序)
继第一等离子体工序之后,从工艺气体源212经由气体导入口203a对真空腔203的内侧的处理空间导入第二气体。接下来,当从第一高频电源210A对天线209供给电力时,会生成磁场,由第二气体生成第二等离子体。第二等离子体工序是对被处理区域R2进行蚀刻而对半导体基板10进行切割而进行单片化的工序。
第二等离子体工序中的蚀刻条件能够根据半导体基板10的材质而适宜地进行选择。在半导体基板10为硅的情况下,能够使用所谓的波希法对被处理区域R2进行蚀刻。在波希法中,依次重复沉积膜形成步骤、沉积膜蚀刻步骤、以及硅蚀刻步骤。由此,能够在深度方向上挖入被处理区域R2。
在沉积膜形成步骤中,例如可以作为原料气体以150~250sccm供给C4F8,同时将处理空间内的压力调整为15Pa~25Pa,并且将第一高频电源210A对天线209的投入功率设为1500~2500W,将第二高频电源210B对高频电极部220的投入功率设为0W,将处理时间设为5~15秒。另外,sccm是流量的单位,1sccm是一分钟流过1cm3的标准状态(0℃、一个大气压)的气体的量。
在沉积膜蚀刻步骤中,例如,可以作为原料气体以200~400sccm供给SF6,同时将处理空间内的压力调整为5Pa~15Pa,并且将第一高频电源210A对天线209的投入功率设为1500~2500W,将第二高频电源210B对高频电极部220的投入功率设为100~300W,将处理时间设为2~10秒。
在硅蚀刻步骤中,例如,可以作为原料气体以200~400sccm供给SF6,同时将处理空间内的压力调整为5Pa~15Pa,并且将第一高频电源210A对天线209的投入功率设为1500~2500W,将第二高频电源210B对高频电极部220的投入功率设为50~200W,将处理时间设为10~20秒。
通过以上述的条件重复沉积膜形成步骤、沉积膜蚀刻步骤、以及硅蚀刻步骤,从而能够以例如10μm/分钟的速度挖入硅基板。
优选一边对ESC电极219施加电压而使保持片22吸附于载置台211一边进行第二等离子体工序。半导体基板10的被处理区域R2被第二等离子体从第一主面10S蚀刻至第二主面10R,从而被单片化。即,半导体基板10通过第二等离子体工序被分割为具备元件区域R1的多个元件芯片11(图2E)。
(灰化工序)
接下来,可以进行除去掩模30M的灰化工序(图2F)。能够在进行了第二等离子体工序的处理空间内继续进行灰化工序。灰化用的工艺气体(例如,氧气)从灰化气体源213经由气体导入口203a导入到处理空间内。当对维持为给定压力的处理空间内供给高频电力时,会产生等离子体,可从元件芯片11的表面除去掩模30M。
接下来,图3示意性地示出本公开的实施方式涉及的另一个等离子体处理方法的方案。本发明涉及的等离子体处理方法是在对如图3A所示地在第一主面10Sa具有多个凹凸的基板10A进行蚀刻的情况下有用的处理。
在基板10A在第一主面10Sa具有多个凹凸的情况下,在将树脂膜30粘附到第一主面10Sa时,在树脂膜30与第一主面10Sa之间会由于许多的凹部24而形成许多的空隙(图3B)。当在这样的状态下对树脂膜30进行图案化时,形成的掩模30M与基板10A的第一主面10Sa的接合区域会非常小,掩模30M的上浮程度会增大(图3C)。如果在该时间点通过第一等离子体工序对掩模30M进行加热,则如图3D所示,会产生掩模30M的一部分(特别是粘接层)软化而填充到第一主面10Sa的凹部24的现象。由此,可显著提高掩模30M与第一主面10Sa的密接性。因而,接下来进行的第二等离子体工序不会受到多个凹凸的影响,基板10A不易被额外地蚀刻(图3E)。在该情况下,如果进行灰化工序,则由填充到第一主面10Sa的掩模30M构成的构件也会被除去,因此可得到维持了初始的第一主面10Sa的凹凸的元件芯片11A(图3F)。
本发明的等离子体处理方法例如在粘附干膜抗蚀剂那样的树脂膜而形成掩模并且接着用精细的图案进行蚀刻的情况下是有用的。
Claims (8)
1.一种等离子体处理方法,包括:
粘附工序,在具备第一主面和所述第一主面的相反侧的第二主面的基板的所述第一主面粘附树脂膜;
图案化工序,对所述树脂膜进行图案化,形成具有使所述基板的被处理区域露出的开口部的掩模;
第一等离子体工序,在包含第一气体的减压环境中生成所述第一气体的第一等离子体,并使所述掩模暴露于所述第一等离子体,从而减少所述掩模与所述第一主面之间的空隙;以及
第二等离子体工序,在包含第二气体的环境中用所述第二气体生成第二等离子体,并使从所述开口部露出的所述被处理区域暴露于所述第二等离子体,从而对所述被处理区域进行蚀刻。
2.根据权利要求1所述的等离子体处理方法,所述第一等离子体工序包括用所述第一等离子体对所述掩模进行加热而使所述掩模的至少一部分软化的步骤。
3.根据权利要求1所述的等离子体处理方法,所述第一气体包含从由氩、氧、氮以及氦构成的组中选择的至少一种。
4.根据权利要求1所述的等离子体处理方法,包含所述第一气体的减压环境的压力为0.1Pa~100Pa。
5.根据权利要求1所述的等离子体处理方法,所述第一等离子体工序和所述第二等离子体工序在相同的空间内连续地进行。
6.根据权利要求1所述的等离子体处理方法,所述图案化工序包括通过湿式蚀刻除去所述树脂膜的与所述开口部对应的部分的步骤。
7.根据权利要求1所述的等离子体处理方法,所述图案化工序包括利用激光进行划刻而除去所述树脂膜的与所述开口部对应的部分的步骤。
8.根据权利要求1~7中的任一项所述的等离子体处理方法,所述第二等离子体工序包括将所述被处理区域从所述第一主面蚀刻至所述第二主面而将所述基板单片化的步骤。
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