JP2017139045A - 電力スイッチ回路 - Google Patents
電力スイッチ回路 Download PDFInfo
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- JP2017139045A JP2017139045A JP2017006130A JP2017006130A JP2017139045A JP 2017139045 A JP2017139045 A JP 2017139045A JP 2017006130 A JP2017006130 A JP 2017006130A JP 2017006130 A JP2017006130 A JP 2017006130A JP 2017139045 A JP2017139045 A JP 2017139045A
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- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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Abstract
Description
Claims (15)
- 電力スイッチ回路であって、
第1のトランジスタであり、前記第1のトランジスタの第1のソース/ドレイン端子は、第1の供給電圧を受け取り、前記第1のトランジスタの第2のソース/ドレイン端子は、ノードzと接続されており、前記第1のトランジスタのゲート端子は、第2の供給電圧を受け取り、前記第1のトランジスタのボディ端子は、前記ノードzと接続されており、出力信号が、前記ノードzから出力される、第1のトランジスタと、
第2のトランジスタであり、前記第2のトランジスタの第1のソース/ドレイン端子は、前記第2の供給電圧を受け取り、前記第2のトランジスタの第2のソース/ドレイン端子は、前記ノードzと接続されており、前記第2のトランジスタのゲート端子は、前記第1の供給電圧を受け取り、前記第2のトランジスタのボディ端子は、前記ノードzと接続されている、第2のトランジスタと、
バイアス電圧と前記ノードzとの間に接続されている電流源と
を備え、
前記第1の供給電圧が前記第2の供給電圧よりも低い場合、前記第1の供給電圧が前記出力信号として選択され、前記第1の供給電圧が前記第2の供給電圧よりも高い場合、前記第2の供給電圧が前記出力信号として選択され、前記第1の供給電圧が前記第2の供給電圧に等しい場合、前記バイアス電圧が前記出力信号として選択される、電力スイッチ回路。 - 前記バイアス電圧は前記第1の供給電圧に等しく、または、前記バイアス電圧は前記第2の供給電圧に等しく、前記第1のトランジスタおよび前記第2のトランジスタはn型トランジスタであり、前記電流源は弱電流源である、請求項1に記載の電力スイッチ回路。
- 電力スイッチ回路であって、
第1のトランジスタであり、前記第1のトランジスタの第1のソース/ドレイン端子は、第1の供給電圧を受け取り、前記第1のトランジスタの第2のソース/ドレイン端子は、ノードzと接続されており、前記第1のトランジスタのゲート端子は、第2の供給電圧を受け取り、前記第1のトランジスタのボディ端子は、前記ノードzと接続されており、出力信号が、前記ノードzから出力される、第1のトランジスタと、
第2のトランジスタであり、前記第2のトランジスタの第1のソース/ドレイン端子は、前記第2の供給電圧を受け取り、前記第2のトランジスタの第2のソース/ドレイン端子は、前記ノードzと接続されており、前記第2のトランジスタのゲート端子は、前記第1の供給電圧を受け取り、前記第2のトランジスタのボディ端子は、前記ノードzと接続されている、第2のトランジスタと、
第3のトランジスタであり、前記第3のトランジスタの第1のソース/ドレイン端子は、バイアス電圧を受け取り、前記第3のトランジスタの第2のソース/ドレイン端子は、前記ノードzと接続されており、前記第3のトランジスタのゲート端子は、シフト信号を受信し、前記第3のトランジスタのボディ端子は、前記ノードzと接続されている、第3のトランジスタと、
前記第1の供給電圧および前記第2の供給電圧を受け取り、出力電圧を生成する自動選択回路であり、前記第1の供給電圧が前記第2の供給電圧よりも低い場合、前記第1の供給電圧が前記出力電圧として選択され、前記第1の供給電圧が前記第2の供給電圧よりも高い場合、前記第2の供給電圧が前記出力電圧として選択される、自動選択回路と、
制御信号および前記自動選択回路の前記出力電圧に従って、前記制御信号を前記シフト信号に変換するためのレベルシフタと
を備える、電力スイッチ回路。 - 前記バイアス電圧は前記第1の供給電圧に等しく、または、前記バイアス電圧は前記第2の供給電圧に等しく、前記第1のトランジスタ、前記第2のトランジスタおよび前記第3のトランジスタはn型トランジスタである、請求項3に記載の電力スイッチ回路。
- 前記自動選択回路は、
第4のトランジスタであって、前記第4のトランジスタの第1のソース/ドレイン端子は、前記第1の供給電圧を受け取り、前記第4のトランジスタの第2のソース/ドレイン端子は、前記出力電圧を生成し、前記第4のトランジスタのゲート端子は、前記第2の供給電圧を受け取り、前記第4のトランジスタのボディ端子は、前記第4のトランジスタの前記第2のソース/ドレイン端子と接続されている、第4のトランジスタと、
第5のトランジスタであって、前記第5のトランジスタの第1のソース/ドレイン端子は、前記第2の供給電圧を受け取り、前記第5のトランジスタの第2のソース/ドレイン端子およびボディ端子は、前記第4のトランジスタの前記第2のソース/ドレイン端子と接続されており、前記第5のトランジスタのゲート端子は、前記第1の供給電圧を受け取る、第5のトランジスタと
を備える、請求項3に記載の電力スイッチ回路。 - 第4のトランジスタであって、前記第4のトランジスタの第1のソース/ドレイン端子およびボディ端子は、前記第1の供給電圧を受け取り、前記第4のトランジスタの第2のソース/ドレイン端子は、ノードaと接続されており、前記第4のトランジスタのゲート端子は、前記第2の供給電圧を受け取る、第4のトランジスタと、
第5のトランジスタであって、前記第5のトランジスタの第1のソース/ドレイン端子およびボディ端子は、前記第2の供給電圧を受け取り、前記第5のトランジスタの第2のソース/ドレイン端子は、ノードbと接続されており、前記第5のトランジスタのゲート端子は、前記第1の供給電圧を受け取る、第5のトランジスタと、
電圧源と前記ノードaとの間に接続されている第1の電流源と、
前記電圧源と前記ノードbとの間に接続されている第2の電流源と、
ANDゲートであって、前記ANDゲートの2つの入力端子はそれぞれ前記ノードaおよび前記ノードbと接続されており、前記ANDゲートの出力端子は前記制御信号を生成する、ANDゲートと
をさらに備える、請求項3に記載の電力スイッチ回路。 - 電力スイッチ回路であって、
第1のトランジスタであり、前記第1のトランジスタの第1のソース/ドレイン端子は、第1の供給電圧を受け取り、前記第1のトランジスタの第2のソース/ドレイン端子は、ノードwと接続されており、前記第1のトランジスタのゲート端子は、第1シフト信号を受信し、出力信号が、前記ノードwから出力される、第1のトランジスタと、
第2のトランジスタであり、前記第2のトランジスタの第1のソース/ドレイン端子は、前記第2の供給電圧を受け取り、前記第2のトランジスタの第2のソース/ドレイン端子は、前記ノードwと接続されており、前記第2のトランジスタのゲート端子は、第2のシフト信号を受信する、第2のトランジスタと、
前記第1の供給電圧および前記第2の供給電圧を受け取り、出力電圧を生成する第1の自動選択回路であり、前記第1の供給電圧が前記第2の供給電圧よりも低い場合、前記第1の供給電圧が前記出力電圧として選択され、前記第1の供給電圧が前記第2の供給電圧よりも高い場合、前記第2の供給電圧が前記出力電圧として選択される、第1の自動選択回路と、
第1の制御信号および前記第1の自動選択回路の前記出力電圧に従って、前記第1の制御信号を前記第1のシフト信号に変換するための第1のレベルシフタと、
第2の制御信号および前記第1の自動選択回路の前記出力電圧に従って、前記第2の制御信号を前記第2のシフト信号に変換するための第2のレベルシフタと
を備える、電力スイッチ回路。 - 前記第1のトランジスタおよび前記第2のトランジスタはn型トランジスタである、請求項7に記載の電力スイッチ回路。
- 前記第1の自動選択回路は、
第3のトランジスタであって、前記第3のトランジスタの第1のソース/ドレイン端子は、前記第1の供給電圧を受け取り、前記第3のトランジスタの第2のソース/ドレイン端子は、前記出力電圧を生成し、前記第3のトランジスタのゲート端子は、前記第2の供給電圧を受け取り、前記第3のトランジスタのボディ端子は、前記第3のトランジスタの前記第2のソース/ドレイン端子と接続されている、第3のトランジスタと、
第4のトランジスタであって、前記第4のトランジスタの第1のソース/ドレイン端子は、前記第2の供給電圧を受け取り、前記第4のトランジスタの第2のソース/ドレイン端子およびボディ端子は、前記第3のトランジスタの前記第2のソース/ドレイン端子と接続されており、前記第4のトランジスタのゲート端子は、前記第1の供給電圧を受け取る、第4のトランジスタと
を備える、請求項7に記載の電力スイッチ回路。 - 前記第1の供給電圧および前記出力信号を受け取り、前記第1のトランジスタのボディ端子に対する第1のボディ電圧を生成する第2の自動選択回路であって、前記第1の供給電圧が前記出力信号よりも低い場合、前記第1の供給電圧が前記第1のボディ電圧として選択され、前記第1の供給電圧が前記出力信号よりも高い場合、前記出力信号が前記第1のボディ電圧として選択される、第2の自動選択回路と、
前記第2の供給電圧および前記出力信号を受け取り、前記第2のトランジスタのボディ端子に対する第2のボディ電圧を生成する第3の自動選択回路であって、前記第2の供給電圧が前記出力信号よりも低い場合、前記第2の供給電圧が前記第2のボディ電圧として選択され、前記第2の供給電圧が前記出力信号よりも高い場合、前記出力信号が前記第2のボディ電圧として選択される、第3の自動選択回路と
をさらに備える、請求項7に記載の電力スイッチ回路。 -
第3のトランジスタであって、前記第3のトランジスタの第1のソース/ドレイン端子は、バイアス電圧を受け取り、前記第3のトランジスタの第2のソース/ドレイン端子は、前記ノードwと接続されており、前記第3のトランジスタのゲート端子は、第3のシフト信号を受信する、第3のトランジスタと、
第3の制御信号および前記出力電圧に従って、前記第3の制御制御信号を前記第3のシフト信号に変換するための第3のレベルシフタと
をさらに備え、
前記第1の制御信号および前記第2の制御信号が第1の論理レベル状態にあるとき、前記第3の制御信号は第2の論理レベル状態にある、請求項7に記載の電力スイッチ回路。 - 前記バイアス電圧は前記第1の供給電圧に等しく、または、前記バイアス電圧は前記第2の供給電圧に等しい、請求項11に記載の電力スイッチ回路。
- 第4のトランジスタであって、前記第4のトランジスタの第1のソース/ドレイン端子およびボディ端子は、前記第1の供給電圧を受け取り、前記第4のトランジスタの第2のソース/ドレイン端子は、ノードcと接続されており、前記第4のトランジスタのゲート端子は、前記第2の供給電圧を受け取る、第4のトランジスタと、
第5のトランジスタであって、前記第5のトランジスタの第1のソース/ドレイン端子およびボディ端子は、前記第2の供給電圧を受け取り、前記第5のトランジスタの第2のソース/ドレイン端子は、ノードdと接続されており、前記第5のトランジスタのゲート端子は、前記第1の供給電圧を受け取る、第5のトランジスタと、
電圧源と前記ノードcとの間に接続されている第1の電流源と、
前記電圧源と前記ノードdとの間に接続されている第2の電流源と、
ANDゲートであって、前記ANDゲートの2つの入力端子はそれぞれ前記ノードcおよび前記ノードdと接続されており、前記ANDゲートの出力端子は前記第3の制御信号を生成する、ANDゲートと
をさらに備える、請求項11に記載の電力スイッチ回路。 - 弱電流源をさらに備え、前記弱電流源は、バイアス電圧と前記ノードwとの間に接続されている、請求項7に記載の電力スイッチ回路。
- 前記バイアス電圧は前記第1の供給電圧に等しく、または、前記バイアス電圧は前記第2の供給電圧に等しい、請求項14に記載の電力スイッチ回路。
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