JP2012195594A - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 230000015556 catabolic process Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 23
- 239000010408 film Substances 0.000 description 214
- 239000010409 thin film Substances 0.000 description 86
- 239000010410 layer Substances 0.000 description 45
- 238000010586 diagram Methods 0.000 description 44
- 238000000034 method Methods 0.000 description 37
- 238000006243 chemical reaction Methods 0.000 description 27
- 239000012535 impurity Substances 0.000 description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 20
- 230000000694 effects Effects 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- -1 Phosphorus ions Chemical class 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- 238000012546 transfer Methods 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 230000001133 acceleration Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 229910015900 BF3 Inorganic materials 0.000 description 5
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 3
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012966 insertion method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000004335 scaling law Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101100171060 Caenorhabditis elegans div-1 gene Proteins 0.000 description 1
- 102100026038 Lens fiber membrane intrinsic protein Human genes 0.000 description 1
- 101710115990 Lens fiber membrane intrinsic protein Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L21/8232—Field-effect technology
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Abstract
【解決手段】同一Si基板上に少なくともソース・ゲート間又はドレイン・ゲート間に流れるトンネル電流の大きさが異なる複数種類のMOSトランジスタを設け、当該複数種類のMOSトランジスタの内、トンネル電流が大きい少なくとも1つのMOSトランジスタで構成された主回路と、トンネル電流が小さい少なくとも1つのMOSトランジスタで構成され、主回路と2つの電源の少なくとも一方の間に挿入した制御回路を有し、制御回路に供給する制御信号で主回路を構成するソース・ゲート間又はドレイン・ゲート間に電流が流れることの許容/不許容を制御し、待機時間中に主回路のINとOUTの論理レベルが異なる際のIN−OUT間リーク電流を防止するスイッチを主回路のIN又はOUTに設ける。
【選択図】図14
Description
各MOSトランジスタのしきい値が所望の値になるようにイオン打ち込みを行なった後、全面に厚さ10nmのシリコンの熱酸化膜105を形成し、続いて厚さ120 nmのポリシリコン層106を全面に被着する。106全面にリンイオンを導入して、ポリシリコン層106内部のリン平均濃度を1×1020/cm3以上に調整する。この時のリンイオン導入方法は、加速エネルギー40KeV程度で2×1015/cm2程度のイオン打ち込みを用いてもよく、あるいはボロン・ドープト・ポリシリコンを用いてもよい。続いて、全面に膜厚50nmのシリコン酸化膜からなるゲート電極保護膜107を被着する(a)。107の作用については、後述する。
続いて、ショートチャネル効果抑制のためのイオン打込みを行なうが、図が煩雑になることを防ぐためここでは記載を省略してある。そして層間絶縁膜116を形成した後、第1の金属配線層117をもって各トランジスタの端子を接続する(d)。必要に応じて、第2、第3の配線層を形成する。この薄いゲート酸化膜を有するMOSトランジスタは、電源電圧1.8Vという低電源電圧であっても、ゲート酸化膜にかかる電界は5MV/cm2以上となり、ゲートリーク電流は1×10―6A/cm2になる。この薄いゲート酸化膜を有するMOSトランジスタは、従来のスケーリング則に従って製造されており、主回路に使用するのに適している。尚、厚膜MOSトランジスタのゲート長は薄膜MOSトランジスタのゲート長、即ち、同一チップ内に存在するトランジスタの最小ゲート長よりも大きくすることが望ましい。厚膜MOSトランジスタのしきい値は薄膜MOSトランジスタのそれよりも高く設定する必要がある。しかし、同一のゲート長でゲート酸化膜のみを厚くすると、しきい値が低くなる傾向にあることがよく知られている。しきい値が低くなると、MOSトランジスタが完全にオフしない状態になりやすい、即ち、サブスレッショルド電流により、薄膜MOSトランジスタに電流が供給されてしまう。これでは本発明の効果を発揮できなくなる。この現象は、ソース・ドレインの距離を大きくする、即ち、ゲート長を大きくすることで解決できる。この方法は、一般に「スケーリング則」として呼び習わされてきた、MOSトランジスタの設計指針と整合性が良い。即ち、スケーリングしなかったMOSトランジスタを適用すれば十分である。但し、その分、面積が増大することは否めない。
n型シリコン基板5101上に、熱酸化膜300nmからなる素子分離絶縁領域5102、n型不純物層5103およびn型不純物層5104を形成する。5103および5104は平均濃度 1×1017/cm3程度であり、本来、同一チップ内に存在するp型MOSトランジスタ(薄膜、厚膜共)との素子分離に必要な領域である。5103および5104への不純物導入方法は特に問わない。
各MOSトランジスタのしきい値が所望の値になるようにイオン打ち込みを行なった後、全面に厚さ10nmのシリコンの熱酸化膜5105を形成し、続いて厚さ120 nmのポリシリコン層5106を全面に被着する。6106全面にボロンイオンを導入して、ポリシリコン層5106内部のボロン平均濃度を 1×1020/cm3以上に調整する。この時のボロンイオン導入方法は、加速エネルギー40KeV程度で2×1015/cm2程度のイオン打ち込みを用いてもよく、あるいはボロン・ドープト・ポリシリコンを用いてもよい。続いて、全面に膜厚50nmのシリコン酸化膜からなるゲート電極保護膜5107を被着する(a)。
図12に示すように待機時間中にIN=OUT=‘H’であることがわかっていれば、Vss側のみにスイッチMN1を挿入すればよく、Vdd側には不要である。
Claims (8)
- 第1導電型の第1MOSトランジスタと、上記第1導電型と導電型が異なる第2導電型の第2MOSトランジスタとを有する論理回路と、
上記第1及び第2MOSトランジスタのゲート絶縁膜厚より厚いゲート絶縁膜厚を有する上記第2導電型の第3MOSトランジスタとを有し、
上記第1MOSトランジスタのソースが第1電源線に接続され、上記第1MOSトランジスタのドレイン及び上記第2MOSトランジスタのドレインが出力ノードに接続され、上記第2MOSトランジスタのソースが上記第3MOSトランジスタのドレインに接続され、上記第3MOSトランジスタのソースが第2電源線に接続され、
上記第1電源線及び上記第2電源線の間に接続され、上記論理回路の出力情報を保持するホールド回路と、
上記出力ノードと上記ホールド回路の間にソース・ドレイン経路を形成するように接続され、上記第1及び第2MOSトランジスタのゲート絶縁膜厚より厚いゲート絶縁膜を有する第4MOSトランジスタを有するスイッチ回路とを具備し、
上記第4MOSトランジスタは、上記第3MOSトランジスタがオフ状態のときに、オフ状態となり、上記第3MOSトランジスタがオン状態のときに、オン状態となり、
上記第3MOSトランジスタがオフ状態のとき上記第1MOSトランジスタのソースと上記第1電源線の間は通電状態にあり、
上記ホールド回路は、上記第3及び第4MOSトランジスタがオフ状態の場合においても、上記第1電源線及び上記第2電源線からの動作電圧が供給されることを特徴とする半導体集積回路装置。 - 第1導電型の第1MOSトランジスタと、上記第1導電型と導電型が異なる第2導電型の第2MOSトランジスタとを有する論理回路と、
上記第1及び第2MOSトランジスタのゲート絶縁膜厚より厚いゲート絶縁膜厚を有する上記第2導電型の第3MOSトランジスタとを有し、
上記第1MOSトランジスタのソースが第1電源線に接続され、上記第1MOSトランジスタのドレイン及び上記第2MOSトランジスタのドレインが出力ノードに接続され、上記第2MOSトランジスタのソースが上記第3MOSトランジスタのドレインに接続され、上記第3MOSトランジスタのソースが第2電源線に接続され、
上記第1電源線及び上記第2電源線の間に接続され、上記論理回路の出力情報を保持するホールド回路と、
上記出力ノードと上記ホールド回路の間にソース・ドレイン経路を形成するように設けられ、上記第1及び第2MOSトランジスタのゲート絶縁膜厚より厚いゲート絶縁膜を有する第4MOSトランジスタを具備し、
上記第4MOSトランジスタは、上記第3MOSトランジスタがオン状態のときは、上記論理回路の出力を上記ホールド回路に伝達し、上記第3MOSトランジスタがオフ状態のときは、上記論理回路と上記ホールド回路間の経路を遮断するように制御されることを特徴とする半導体集積回路装置。 - 請求項1又は2において、
上記半導体集積回路装置の外部からの入力を受ける入出力回路を有し、
上記入出力回路は上記第1MOSトランジスタよりも高耐圧の第5MOSトランジスタを含んでおり、
上記第5MOSトランジスタのゲート絶縁膜は、上記第1及び第2MOSトランジスタのゲート絶縁膜厚よりも厚いことを特徴とする半導体集積回路装置。 - 請求項1乃至3のいずれかにおいて、
上記第3MOSトランジスタは、オン状態とされる場合に、上記第1MOSトランジスタのソースとゲートの間に印加される電圧よりも大きい電圧をゲートとソースの間に印加して駆動されることを特徴とする半導体集積回路装置。 - 請求項1乃至4の何れかにおいて、
上記論理回路は、複数の第2MOSトランジスタを含み、
上記第2MOSトランジスタのソースは第3電源線に接続され、
上記第3MOSトランジスタのソース・ドレイン経路は、上記第3電源線と上記第2電源線との間に接続されることを特徴とする半導体集積回路装置。 - 請求項1乃至5のいずれかにおいて、
上記第3及び第4MOSトランジスタのゲート長は、上記第1MOSトランジスタのゲート長よりも大きいことを特徴とする半導体集積回路装置。 - 請求項1乃至6のいずれかにおいて、
上記第4MOSトランジスタのゲート幅は、上記第1MOSトランジスタのゲート幅より大きいことを特徴とする半導体集積回路装置。 - 請求項1乃至7のいずれかにおいて、
上記第3MOSトランジスタと上記第4MOSトランジスタは、同じ制御信号により制御されることを特徴とする半導体集積回路装置。
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Also Published As
Publication number | Publication date |
---|---|
US20140252495A1 (en) | 2014-09-11 |
WO1997038444A1 (en) | 1997-10-16 |
US20150357248A1 (en) | 2015-12-10 |
TW382164B (en) | 2000-02-11 |
TW435007B (en) | 2001-05-16 |
US20030052371A1 (en) | 2003-03-20 |
US7781814B2 (en) | 2010-08-24 |
EP0951072A4 (en) | 2000-09-13 |
US9111909B2 (en) | 2015-08-18 |
JP5325317B2 (ja) | 2013-10-23 |
US6307236B1 (en) | 2001-10-23 |
US6500715B2 (en) | 2002-12-31 |
EP0951072A1 (en) | 1999-10-20 |
US8674419B2 (en) | 2014-03-18 |
US20050190608A1 (en) | 2005-09-01 |
US7427791B2 (en) | 2008-09-23 |
US20110012180A1 (en) | 2011-01-20 |
JP2010153891A (ja) | 2010-07-08 |
US20080297220A1 (en) | 2008-12-04 |
JP5232816B2 (ja) | 2013-07-10 |
US20010034093A1 (en) | 2001-10-25 |
EP0951072B1 (en) | 2009-12-09 |
DE69739692D1 (de) | 2010-01-21 |
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