JP2005051240A - 改善された半田ボールランドの構造を有する半導体パッケージ - Google Patents
改善された半田ボールランドの構造を有する半導体パッケージ Download PDFInfo
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- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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Abstract
【課題】本発明は、SMD型とNSMD型とを混合した半田ボールランド構造を採用にすることによって、半田ボールの脱落、パターンクラック(pattern crack)、並びに半田ボールランドの分離等の現象を防止することができ、且つ、基板に対する半田ボールの高い融着力のある信頼性を高いBGA半導体パッケージを提供する。
【解決手段】半導体パッケージは、平面を有する基板と、前記基板の平面に形成される複数の半田ボールランドと、複数の半田ボールランドに形成される半田ボールと、前記半田ボールランドを露出させる、前記半田ボールランドの半径より小さい半径を有する複数の開口領域を限定し、前記基板の平面を塗布するマスク層とを備える。
【選択図】図3
Description
図2A及び図2Bは、各々、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。図2A及び図2Bに示すように、BGA半導体パッケージ用(図示せず)基板の半田ボール実装面2の上に、半田ボールランド30が形成される。半田ボール実装面2の上に半田マスク36が塗布され、半田マスク36の塗布されていない領域には半田ボールランド30を露出させるマスク開口領域37が設けられる。
図3は、本発明の一実施形態によるBGA半導体パッケージの半田ボール実装面を示す平面図である。
図4は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
図5は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
図6は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
本発明によるBGA半導体パッケージは、SMD型とNSMD型とを混合した半田ボールランド構造を採用にすることによって、半田ボールの脱落、パターンクラック(pattern crack)、並びに半田ボールランドの分離等の現象を防止することができ、且つ、基板に対する半田ボールの高い融着力によりBGA半導体パッケージの信頼性を高めることができる。
A1 第1周縁部
A2 第2周縁部
2C 半田ボール実装面の中心
30 半田ボールランド
30b ランド端
30c ランドセンター
34 パターン連結部
36 半田マスク
37 開口領域
37a 第1開口端
37b 第2開口端
40 半田ボールランド
40a ランド端
40b ランド端
40c ランドセンター
44 パターン連結部
47 開口領域
50 半田ボールランド
50c ランドセンター
54 パターン連結部
57 開口領域
58 湾曲溝
59 直線溝
60 半田ボールランド
60cランドセンター
68 湾曲溝
69 直線溝
Claims (16)
- 平面を有する基板と、
前記基板の平面に形成され、
湾曲溝と、
前記湾曲溝の外縁に沿って放射状の形状に配置され半田ボールランドのランド端と開口領域の開口端との間の領域にまで延長され前記湾曲溝に通じる複数の直線溝と、ボールランドの半径と、を有する複数の半田ボールランドと、
前記複数のボールランドに形成される複数の接続ボールと、
前記半田ボールランドを露出させる、前記半田ボールランドの半径より小さい半径を有する複数の開口領域を限定し、前記基板の平面を塗布するマスク層と、を備える半導体パッケージにおいて、
前記湾曲溝の中心線は前記開口領域の半径より小さい湾曲溝の半径を有することを特徴とする半導体パッケージ。 - 前記湾曲溝は第3延長線を中心軸にして60゜〜180゜間である第5角度を形成し、前記第3延長線は前記平面の中心と前記半田ボールランドのランド中心とを連結することを特徴とする、請求項1に記載の半導体パッケージ。
- 前記第5角度は150゜であることを特徴とする、請求項2に記載の半導体パッケージ。
- 前記基板は、印刷回路基板、シリコン基板、並びにフレキシブル回路テープを備えることを特徴とする、請求項1に記載の半導体パッケージ。
- 中心点のある平面を有する基板と、
前記基板の平面に形成され第1周縁部及び第2周縁部を有する少なくとも一つの端子ランドと、
前記端子ランドに形成される少なくとも一つの接続端子と、
前記基板の平面に塗布され前記端子ランドを露出させる少なくとも一つの開口領域を限定するマスク層と、を備える半導体デバイスにおいて、
前記マスク層は前記端子ランドの第1周縁部上に塗布され、前記第2周縁部は前記マスク層の開口領域を通して露出することを特徴とする、半導体デバイス。 - 前記第1周縁部は前記基板の平面の中心側に向かい、前記第2周縁部は前記中心の反対側に向かうことを特徴とする、請求項5に記載の半導体デバイス。
- 前記接続端子は半田ボールを備えることを特徴とする、請求項5に記載の半導体デバイス。
- 前記基板は印刷回路基板、シリコン基板、並びにフレキシブル回路テープを備えることを特徴とする、請求項5に記載の半導体デバイス。
- 平面を有する基板と、
前記基板の平面に形成される複数の半田ボールランドと、
前記基板の平面に塗布され前記半田ボールランドを露出させる複数の開口領域を限定するマスク層と、
前記半田ボールランドに形成される複数の接続ボールと、
前記半田ボールランドのランドセンターを通して前記平面の中心から延長され、第1接点において前記半田ボールランドのランド端と接し、第2接点において前記開口領域の開口端と接する第1延長線と、
前記ランドセンターからスタートして前記第1延長線と反対側に延長され、第3接点において前記ランド端と接し、第4接点において前記開口領域の開口端と接する第2延長線と、を有する半導体パッケージにおいて、
前記第1接点と前記ランドセンターとの間の距離が第1距離で、前記第2接点とランドセンターとの間の距離が第2距離で、前記第1距離は前記第2距離より長く、
前記第3接点と前記ランドセンターとの間の距離が第3距離で、前記第4接点と前記ランドセンターとの間の距離が第4距離で、前記第3距離は前記第4距離より短いことを特徴とする、半導体パッケージ。 - 前記複数の半田ボールランドの各々は第1半径を有し、
前記開口領域の第1開口端は前記第1半径より大きい第2半径を有し、
前記開口領域の第2開口端は前記第1半径より小さい第3半径を有することを特徴とする、請求項9に記載の半導体パッケージ。 - 放射状の形状に配置される一対の第3開口端を更に備える半導体パッケージにおいて、
前記第1開口端は前記第2延長線を中心軸にして約160゜〜180゜間に第1角度を形成し、前記第2開口端は前記第1延長線を中心軸にして180゜〜300゜間に第2角度を形成することを特徴とする、請求項10に記載の半導体パッケージ。 - 前記第1角度は約150°であることを特徴とする、請求項11に記載の半導体パッケージ。
- 前記開口領域は第4半径を有し、前記半田ボールランドの第1ランド端は前記第4半径より小さい第5半径を有し、前記半田ボールランドの第2ランド端は前記第4半径より大きい第6半径を有することを特徴とする、請求項11に記載の半導体パッケージ。
- 前記第1ランド端は第2延長線を中心軸にして60゜〜180゜間の円弧を限定することを特徴とする、請求項13に記載の半導体パッケージ。
- 前記円弧が約150゜であることを特徴とする、請求項14に記載の半導体パッケージ。
- 前記基板は印刷回路基板、シリコン基板、並びにフレキシブル回路テープを備えることを特徴とする、請求項11に記載の半導体パッケージ。
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KR10-2003-0052328A KR100523330B1 (ko) | 2003-07-29 | 2003-07-29 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
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JP2009016637A Expired - Fee Related JP5090385B2 (ja) | 2003-07-29 | 2009-01-28 | 改善された半田ボールランドの構造を有する半導体パッケージ |
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JP2008277720A (ja) * | 2007-05-04 | 2008-11-13 | Powertech Technology Inc | 半導体チップパッケージ基板とそのソルダーパッド |
JP2009117862A (ja) * | 2003-07-29 | 2009-05-28 | Samsung Electronics Co Ltd | 改善された半田ボールランドの構造を有する半導体パッケージ |
JP2010245455A (ja) * | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 基板および半導体装置 |
JP2011066122A (ja) * | 2009-09-16 | 2011-03-31 | Murata Mfg Co Ltd | 回路基板 |
CN101499451B (zh) * | 2008-01-30 | 2012-08-22 | 三星电子株式会社 | 印刷电路板、半导体封装件、卡装置和*** |
WO2015198837A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2015198836A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
WO2015198838A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
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US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US7902679B2 (en) * | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US20060163729A1 (en) * | 2001-04-18 | 2006-07-27 | Mou-Shiung Lin | Structure and manufacturing method of a chip scale package |
US7416106B1 (en) * | 2003-09-29 | 2008-08-26 | Emc Corporation | Techniques for creating optimized pad geometries for soldering |
US8853001B2 (en) | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
TWI358776B (en) * | 2003-11-08 | 2012-02-21 | Chippac Inc | Flip chip interconnection pad layout |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
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Also Published As
Publication number | Publication date |
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KR20050013773A (ko) | 2005-02-05 |
JP4349988B2 (ja) | 2009-10-21 |
US7064435B2 (en) | 2006-06-20 |
US20050023683A1 (en) | 2005-02-03 |
KR100523330B1 (ko) | 2005-10-24 |
JP2009117862A (ja) | 2009-05-28 |
JP5090385B2 (ja) | 2012-12-05 |
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