JP5090385B2 - 改善された半田ボールランドの構造を有する半導体パッケージ - Google Patents
改善された半田ボールランドの構造を有する半導体パッケージ Download PDFInfo
- Publication number
- JP5090385B2 JP5090385B2 JP2009016637A JP2009016637A JP5090385B2 JP 5090385 B2 JP5090385 B2 JP 5090385B2 JP 2009016637 A JP2009016637 A JP 2009016637A JP 2009016637 A JP2009016637 A JP 2009016637A JP 5090385 B2 JP5090385 B2 JP 5090385B2
- Authority
- JP
- Japan
- Prior art keywords
- solder ball
- land
- substrate
- semiconductor package
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910000679 solder Inorganic materials 0.000 title claims description 161
- 239000004065 semiconductor Substances 0.000 title claims description 55
- 239000000758 substrate Substances 0.000 claims description 42
- 230000002093 peripheral effect Effects 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 description 6
- 230000004927 fusion Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010047700 Vomiting Diseases 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09809—Coaxial layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
図2A及び図2Bは、各々、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。図2A及び図2Bに示すように、BGA半導体パッケージ用(図示せず)基板の半田ボール実装面2の上に、半田ボールランド30が形成される。半田ボール実装面2の上に半田マスク36が塗布され、半田マスク36の塗布されていない領域には半田ボールランド30を露出させるマスク開口領域37が設けられる。
図3は、本発明の一実施形態によるBGA半導体パッケージの半田ボール実装面を示す平面図である。
図4は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
図5は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
図6は、本発明の一実施形態によるBGA半導体パッケージの半田ボールランドを示す平面図である。
本発明によるBGA半導体パッケージは、SMD型とNSMD型とを混合した半田ボールランド構造を採用にすることによって、半田ボールの脱落、パターンクラック(pattern crack)、並びに半田ボールランドの分離等の現象を防止することができ、且つ、基板に対する半田ボールの高い融着力によりBGA半導体パッケージの信頼性を高めることができる。
A1 第1周縁部
A2 第2周縁部
2C 半田ボール実装面の中心
30 半田ボールランド
30b ランド端
30c ランドセンター
34 パターン連結部
36 半田マスク
37 開口領域
37a 第1開口端
37b 第2開口端
40 半田ボールランド
40a ランド端
40b ランド端
40c ランドセンター
44 パターン連結部
47 開口領域
50 半田ボールランド
50c ランドセンター
54 パターン連結部
57 開口領域
58 円弧状の溝
59 直線状の溝
60 半田ボールランド
60cランドセンター
68 円弧状の溝
69 直線状の溝
Claims (11)
- 基板と、
前記基板上に形成され第1周縁部及び第2周縁部を有する少なくとも一つの端子ランドと、
前記端子ランドに形成される少なくとも一つの接続端子と、
前記基板上に塗布され前記端子ランドを露出させる少なくとも一つの開口領域を限定するマスク層と、を備える半導体デバイスにおいて、
前記第1周縁部は前記基板の中心側に位置し、前記第2周縁部は前記基板の中心側とは反対の側に位置しており、
前記マスク層は前記端子ランドの第1周縁部上に塗布され、前記第2周縁部は前記マスク層の開口領域を通して露出することを特徴とする、半導体デバイス。 - 前記接続端子は半田ボールを備えることを特徴とする、請求項1に記載の半導体デバイス。
- 前記基板は印刷回路基板、シリコン基板、並びにフレキシブル回路テープを備えることを特徴とする、請求項1に記載の半導体デバイス。
- 基板と、
前記基板上に形成され、第1周縁部及び第2周縁部を有する複数の半田ボールランドと、
前記基板上に塗布され前記半田ボールランドを露出させる複数の開口領域を限定するマスク層と、
前記半田ボールランドに形成される複数の接続ボールと、
前記半田ボールランドの中心を通して前記基板の表面の中心から延長され、前記基板の中心側に位置する第1接点において前記半田ボールランドのランド端と接し、第2接点において前記開口領域の開口端と接する第1延長線と、
前記半田ボールランドの中心からスタートして前記第1延長線と反対側に延長され、第3接点において前記ランド端と接し、第4接点において前記開口領域の開口端と接する第2延長線と、を有する半導体パッケージにおいて、
前記第1周縁部は前記マスク層によって被覆され、前記第2周縁部は前記マスク層の開口領域を通して露出されており、
前記第1接点と前記半田ボールランドの中心との間の距離が第1距離で、前記第2接点と半田ボールランドの中心との間の距離が第2距離で、前記第1距離は前記第2距離より長く、
前記第3接点と前記半田ボールランドの中心との間の距離が第3距離であり、前記第4接点と前記半田ボールランドの中心との間の距離が第4距離で、前記第3距離は前記第4距離より短いことを特徴とする、半導体パッケージ。 - 前記複数の半田ボールランドの各々は第1半径を有し、
前記開口領域の第1開口端は前記第1半径より大きい第2半径を有し、
前記開口領域の第2開口端は前記第1半径より小さい第3半径を有することを特徴とする、請求項4に記載の半導体パッケージ。 - 放射状の形状に配置される一対の第3開口端を更に備える半導体パッケージにおいて、前記第1開口端は前記第2延長線を中心軸にして約160°〜180°間に第1角度を形成し、前記第2開口端は前記第1延長線を中心軸にして180°〜300°間に第2角度を形成することを特徴とする、請求項5に記載の半導体パッケージ。
- 前記第1角度は約150°であることを特徴とする、請求項6に記載の半導体パッケージ。
- 前記開口領域は第4半径を有し、前記半田ボールランドの第1ランド端は前記第4半径より小さい第5半径を有し、前記半田ボールランドの第2ランド端は前記第4半径より大きい第6半径を有することを特徴とする、請求項4に記載の半導体パッケージ。
- 前記第1ランド端は第2延長線を中心軸にして60°〜180°間の円弧を限定することを特徴とする、請求項8に記載の半導体パッケージ。
- 前記円弧が約150°であることを特徴とする、請求項9に記載の半導体パッケージ。
- 前記基板は印刷回路基板、シリコン基板、並びにフレキシブル回路テープを備えることを特徴とする、請求項4に記載の半導体パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0052328A KR100523330B1 (ko) | 2003-07-29 | 2003-07-29 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
KR2003-052328 | 2003-07-29 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004213368A Division JP4349988B2 (ja) | 2003-07-29 | 2004-07-21 | 改善された半田ボールランドの構造を有する半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009117862A JP2009117862A (ja) | 2009-05-28 |
JP5090385B2 true JP5090385B2 (ja) | 2012-12-05 |
Family
ID=34101753
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004213368A Expired - Lifetime JP4349988B2 (ja) | 2003-07-29 | 2004-07-21 | 改善された半田ボールランドの構造を有する半導体パッケージ |
JP2009016637A Expired - Fee Related JP5090385B2 (ja) | 2003-07-29 | 2009-01-28 | 改善された半田ボールランドの構造を有する半導体パッケージ |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004213368A Expired - Lifetime JP4349988B2 (ja) | 2003-07-29 | 2004-07-21 | 改善された半田ボールランドの構造を有する半導体パッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US7064435B2 (ja) |
JP (2) | JP4349988B2 (ja) |
KR (1) | KR100523330B1 (ja) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US7902679B2 (en) * | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US20060163729A1 (en) * | 2001-04-18 | 2006-07-27 | Mou-Shiung Lin | Structure and manufacturing method of a chip scale package |
KR100523330B1 (ko) * | 2003-07-29 | 2005-10-24 | 삼성전자주식회사 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
US7416106B1 (en) * | 2003-09-29 | 2008-08-26 | Emc Corporation | Techniques for creating optimized pad geometries for soldering |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
KR101218011B1 (ko) * | 2003-11-08 | 2013-01-02 | 스태츠 칩팩, 엘티디. | 플립 칩 인터커넥션 패드 레이아웃 반도체 패키지 및 그 생산 방법 |
US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US8350384B2 (en) * | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8129841B2 (en) * | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8076232B2 (en) * | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
KR101237172B1 (ko) | 2003-11-10 | 2013-02-25 | 스태츠 칩팩, 엘티디. | 범프-온-리드 플립 칩 인터커넥션 |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US20060175711A1 (en) * | 2005-02-08 | 2006-08-10 | Hannstar Display Corporation | Structure and method for bonding an IC chip |
US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
JP2008535225A (ja) | 2005-03-25 | 2008-08-28 | スタッツ チップパック リミテッド | 基板上に狭い配線部分を有するフリップチップ配線 |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
US9258904B2 (en) * | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
KR100701695B1 (ko) * | 2005-06-21 | 2007-03-29 | 주식회사 하이닉스반도체 | 칩 사이즈 패키지 |
US7713782B2 (en) * | 2006-09-22 | 2010-05-11 | Stats Chippac, Inc. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps |
US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
TW200845332A (en) * | 2007-05-04 | 2008-11-16 | Powertech Technology Inc | Package substrate and its solder pad |
JP2009111279A (ja) * | 2007-10-31 | 2009-05-21 | Elpida Memory Inc | 半導体装置の配線基板、半導体装置、電子装置、マザーボード、半導体装置の配線基板の製造方法、マザーボードの製造方法、電子装置の製造方法 |
KR101407614B1 (ko) * | 2008-01-30 | 2014-06-13 | 삼성전자주식회사 | 인쇄회로기판, 반도체 패키지, 카드 및 시스템 |
US8349721B2 (en) | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
US7759137B2 (en) * | 2008-03-25 | 2010-07-20 | Stats Chippac, Ltd. | Flip chip interconnection structure with bump on partial pad and method thereof |
US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
US20090250814A1 (en) * | 2008-04-03 | 2009-10-08 | Stats Chippac, Ltd. | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof |
TWI379391B (en) * | 2008-05-05 | 2012-12-11 | Siliconware Precision Industries Co Ltd | Electronic carrier board |
US7897502B2 (en) | 2008-09-10 | 2011-03-01 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
KR20100079389A (ko) * | 2008-12-31 | 2010-07-08 | 삼성전자주식회사 | 베리어 패턴을 구비하는 볼 랜드 구조 |
US8659172B2 (en) | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
US8198186B2 (en) | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
US20100237500A1 (en) * | 2009-03-20 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site |
JP5107959B2 (ja) * | 2009-04-09 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | 基板 |
KR101383898B1 (ko) * | 2009-07-03 | 2014-04-10 | 삼성테크윈 주식회사 | 보강 패턴층을 가지는 반도체 기판 |
JP2011066122A (ja) * | 2009-09-16 | 2011-03-31 | Murata Mfg Co Ltd | 回路基板 |
US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
GB2479120A (en) * | 2010-03-26 | 2011-10-05 | Cambridge Display Tech Ltd | Organic electrolumunescent device having conductive layer connecting metal over well defining layer and cathode |
US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
TWI491347B (zh) * | 2012-10-24 | 2015-07-01 | Hon Hai Prec Ind Co Ltd | 散熱板及封裝殼體 |
JP5970348B2 (ja) * | 2012-11-16 | 2016-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20140168909A1 (en) * | 2012-12-19 | 2014-06-19 | Tieyu Zheng | Gapped attachment structures |
JP2015056561A (ja) * | 2013-09-12 | 2015-03-23 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP6547745B2 (ja) * | 2014-06-27 | 2019-07-24 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP6586952B2 (ja) * | 2014-06-27 | 2019-10-09 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP6544354B2 (ja) * | 2014-06-27 | 2019-07-17 | ソニー株式会社 | 半導体装置の製造方法 |
KR101973427B1 (ko) * | 2015-11-18 | 2019-04-29 | 삼성전기주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
JP6750872B2 (ja) * | 2016-09-01 | 2020-09-02 | キヤノン株式会社 | プリント配線板、プリント回路板及び電子機器 |
JP2019040924A (ja) * | 2017-08-22 | 2019-03-14 | 新光電気工業株式会社 | 配線基板及びその製造方法と電子装置 |
KR20220028310A (ko) | 2020-08-28 | 2022-03-08 | 삼성전자주식회사 | 배선 구조체, 이의 제조 방법 및 배선 구조체를 포함하는 반도체 패키지 |
US11569155B2 (en) | 2021-06-09 | 2023-01-31 | Western Digital Technologies, Inc. | Substrate bonding pad having a multi-surface trace interface |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5519580A (en) * | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
US5796589A (en) * | 1995-12-20 | 1998-08-18 | Intel Corporation | Ball grid array integrated circuit package that has vias located within the solder pads of a package |
KR100216839B1 (ko) * | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
DE19750073A1 (de) * | 1997-11-12 | 1999-05-20 | Bosch Gmbh Robert | Schaltungsträgerplatte |
JPH11195867A (ja) * | 1997-12-27 | 1999-07-21 | Sharp Corp | 印刷回路配線基板 |
JP3442648B2 (ja) * | 1998-03-12 | 2003-09-02 | 株式会社日立製作所 | ボールグリッドアレイ型半導体装置 |
US6324754B1 (en) * | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) * | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
TW429492B (en) * | 1999-10-21 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Ball grid array package and its fabricating method |
US6543128B2 (en) * | 1999-12-03 | 2003-04-08 | Siliconware Precision Industries Co., Ltd. | Ball grid array package and its fabricating process |
US6201305B1 (en) * | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
US6552436B2 (en) * | 2000-12-08 | 2003-04-22 | Motorola, Inc. | Semiconductor device having a ball grid array and method therefor |
US7173342B2 (en) * | 2002-12-17 | 2007-02-06 | Intel Corporation | Method and apparatus for reducing electrical interconnection fatigue |
KR100523330B1 (ko) * | 2003-07-29 | 2005-10-24 | 삼성전자주식회사 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
TWI234258B (en) * | 2003-08-01 | 2005-06-11 | Advanced Semiconductor Eng | Substrate with reinforced structure of contact pad |
-
2003
- 2003-07-29 KR KR10-2003-0052328A patent/KR100523330B1/ko not_active IP Right Cessation
-
2004
- 2004-06-25 US US10/877,733 patent/US7064435B2/en not_active Expired - Lifetime
- 2004-07-21 JP JP2004213368A patent/JP4349988B2/ja not_active Expired - Lifetime
-
2009
- 2009-01-28 JP JP2009016637A patent/JP5090385B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100523330B1 (ko) | 2005-10-24 |
KR20050013773A (ko) | 2005-02-05 |
JP2009117862A (ja) | 2009-05-28 |
US20050023683A1 (en) | 2005-02-03 |
JP4349988B2 (ja) | 2009-10-21 |
JP2005051240A (ja) | 2005-02-24 |
US7064435B2 (en) | 2006-06-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5090385B2 (ja) | 改善された半田ボールランドの構造を有する半導体パッケージ | |
US7224073B2 (en) | Substrate for solder joint | |
US5872399A (en) | Solder ball land metal structure of ball grid semiconductor package | |
US6736306B2 (en) | Semiconductor chip package comprising enhanced pads | |
US7565737B2 (en) | Manufacturing method of package substrate | |
US6448504B1 (en) | Printed circuit board and semiconductor package using the same | |
JP3679199B2 (ja) | 半導体パッケージ装置 | |
US8592968B2 (en) | Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method | |
US6250606B1 (en) | Substrate for semiconductor device, semiconductor device and manufacturing method thereof | |
US20020132462A1 (en) | Spherical semiconductor device and method for fabricating the same | |
JPH11111771A (ja) | 配線基板の接続方法、キャリア基板および配線基板 | |
KR100586697B1 (ko) | 솔더 조인트 특성이 개선된 반도체 패키지 | |
JP2007027576A (ja) | 半導体装置 | |
US5849609A (en) | Semiconductor package and a method of manufacturing thereof | |
JP2000243862A (ja) | インターポーザ基板 | |
JP2000124348A (ja) | Vlsiパッケージ | |
JP3875407B2 (ja) | 半導体パッケージ | |
KR200278534Y1 (ko) | 칩 크기 패키지 | |
KR100791575B1 (ko) | 테이프캐리어형 반도체 장치 | |
KR100331386B1 (ko) | 웨이퍼 레벨 패키지 | |
JP3978906B2 (ja) | Icパッケージ | |
JP2000068415A (ja) | チップスケ―ルパッケ―ジ素子の製造方法及びチップスケ―ルパッケ―ジ素子 | |
JP2005197496A (ja) | 回路基板及び回路基板の製造方法、並びに半導体パッケージ及び半導体パッケージの製造方法。 | |
KR20090001250A (ko) | 반도체 패키지 및 반도체 패키지의 접속 단자 형성 방법 | |
US20040124006A1 (en) | Built up lands |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110524 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110822 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120104 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120404 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120409 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120502 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120814 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120912 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150921 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5090385 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |