EP3469664A1 - Leitungsintegrierter halbleiterschalter und verfahren zu dessen herstellung - Google Patents

Leitungsintegrierter halbleiterschalter und verfahren zu dessen herstellung

Info

Publication number
EP3469664A1
EP3469664A1 EP17714166.0A EP17714166A EP3469664A1 EP 3469664 A1 EP3469664 A1 EP 3469664A1 EP 17714166 A EP17714166 A EP 17714166A EP 3469664 A1 EP3469664 A1 EP 3469664A1
Authority
EP
European Patent Office
Prior art keywords
flat part
flat
contact
semiconductor switch
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP17714166.0A
Other languages
German (de)
English (en)
French (fr)
Inventor
Simon BETSCHER
Wacim TAZARINE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Auto Kabel Management GmbH
Original Assignee
Auto Kabel Management GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Auto Kabel Management GmbH filed Critical Auto Kabel Management GmbH
Publication of EP3469664A1 publication Critical patent/EP3469664A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/06102Disposition the bonding areas being at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301Structure
    • H01L2224/3303Layer connectors having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/83411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps

Definitions

  • the subject matter relates to an in-line switch and a method of fabricating a line-integrated switch.
  • the positive battery line is increasingly formed by a so-called backbone cable.
  • a so-called backbone cable often has a flat conductor and extends along the longitudinal axis of a vehicle.
  • the object was the object of a
  • line-integrated switch to provide, which is physically small and can be used in particular in automotive applications.
  • the subject line-integrated switch is preferably used in automotive applications, in particular in conjunction with a
  • the subject matter is a first and a second flat part
  • the two flat parts can be formed, for example, as connection parts for flat conductors or other electrical conductors. It is also possible that at least one of the flat parts is formed as a flat conductor. Such a flat conductor may for example be formed in particular from a solid material and as
  • Battery line in particular as a power line, within a motor vehicle serve.
  • the cable cross-section of flat parts is usually designed to carry currents of more than 10 amps permanently.
  • the flat parts have an overlapping area. In this overlapping area, the flat parts lie one above the other.
  • a semiconductor switch is arranged between the flat parts, the flat parts being interconnected in a switching manner.
  • Semiconductor switch may be a MOSFET, IGBT or the like.
  • Semiconductor switch can be formed as a transistor, thyristor, triac of the like.
  • a semiconductor switch is characterized by having a connection between two line contacts, e.g. Drain and source, can switch.
  • the voltage between the switching contact and one of the line contacts, e.g. Source can be decisive for the connection between the
  • Line contacts becomes electrically conductive or not.
  • the line-integrated switch in a vehicle electrical system, it is possible, for example, to switch from a central point various outlets from a first lead to at least a second lead as needed. This can be useful in particular for the battery and energy management within the motor vehicle. Also, for safety reasons, an on-demand switching of individual branches of a main energy train may be useful.
  • the longitudinal axes of the flat parts may intersect in the overlapping area.
  • the longitudinal axes may, for example, at an angle, in particular at a right angle to each other. That is to say that a second flat part of an initial flat part formed as a battery lead is angled, preferably can branch off at right angles. This makes it possible to realize a very flexible distribution structure within a vehicle electrical system.
  • a first of the flat parts on a side facing the second of the flat parts is at least partially coated with an insulation, wherein in the insulation in a contact region
  • Semiconductor switch is connected in the contact region with the first flat part and can be connected, for example, with a second connection to the second flat part.
  • the semiconductor switch between the two flat conductors can be arranged electrically and can switch the electrical connection between these two.
  • a semiconductor switch may be metallically, in particular metallically coated, in the region of an upper side of its housing and / or in the region of an underside of its housing, at least in the region of a contact.
  • the second line contact may be on top of the
  • semiconductor switch be provided.
  • the semiconductor switch may be sandwiched between the two flat parts.
  • semiconductor switches are usually constructed so that the surfaces of both the switching contact and the two line contacts are as close as possible to a plane in the region of a first surface.
  • the second line contact in the form of a electrical coating of the semiconductor switch is formed as a heat sink.
  • This heat sink can be used objectively to be electrically connected to a flat part, so as to realize the sandwich-like structure between the two flat parts and the semiconductor switch.
  • the semiconductor switch is soldered to the semiconductor switch in the contact area with the first flat part. It is advantageous if the contact region is tinned. According to one embodiment, it is proposed that the first flat part is coated with an at least three-layered structure, wherein a conductive layer is guided between two insulating layers.
  • the respective layers may be adhesively bonded and / or adhesively bonded together. It is particularly useful if a first, applied directly to the flat part of a layer of a
  • the printed circuit board material may in particular be a so-called prepreg (Preimpregnated Fibers). This material is usually the carrier material for printed conductors.
  • the printed circuit board material can be adhesively applied directly to the flat part.
  • Printed circuit board material is applied a conductive layer.
  • the conductive layer is preferably a copper layer.
  • the conductive layer is preferably treated so that it forms printed conductors. This can be done in particular by a
  • the protective layer may be designed such that, in particular, contact pads and solder pads for discrete components are free of the protective varnish and release the material of the conductive layer. Then a discrete component can be soldered onto it.
  • the contact region may be coated so that it terminates substantially in the plane formed by the conductive layer and / or the protective layer.
  • the contact region can be metallically coated so that the metallic coating is always spaced from the conductive layer.
  • the semiconductor switch is provided with a
  • Conductor contact in particular a source or drain contact with the
  • a semiconductor switch may be used, in which both line contacts (in particular source, drain) and the switching contact (in particular gate) are arranged in one plane. If such a semiconductor switch is placed on the first flat part, then a conductor contact come into direct connection with the contact area and the switching contact in direct connection with the Contact pad on the conducting layer. These immediate connections are made by soldering.
  • the second conductor contact which lies in the plane of the first conductor contact, is deposited according to an embodiment on the insulating layer.
  • Insulation layer and / or the conductive layer or the conductor track of the conductive layer may be designed so that in the region in which this second conductor contact rests on the insulating layer, no contact with the conductor track or the flat part is possible. Thus, this conductor contact is insulated at its bearing surface relative to the flat part.
  • a semiconductor switch may, for cooling purposes, transfer the second conductor contact via a housing part to its surface opposite the first conductor contact.
  • This surface lies opposite the surface on which the first conductor contact and the switch contact are. This surface can be used to bring the semiconductor switch with its second conductor contact with the second flat part, in particular its connection area in contact, as will be described below.
  • a semiconductor switch directly his two
  • the second flat part is metallically coated at least in the overlapping area.
  • Coating may be a tin coating.
  • the metallic coating can form a connection region.
  • this connection region is on the surface of the second flat part, which faces the first flat part in the connected state.
  • contact area and connection area are located on mutually facing side of the first and second flat part.
  • the semiconductor switch is electrically contacted with the second flat part in the terminal region.
  • Semiconductor switch a connection between the two flat parts, which is switchable via the switching contact.
  • the electrical connection between the two flat parts can now be switched on and off.
  • a plurality of semiconductor switches are arranged in parallel between two flat parts in the manner described, so that their current carrying capacity is sufficient to carry the total current flowing between the two flat parts. Also, the power loss in each individual semiconductor switch is lower, so that the heat loss generated in each semiconductor switch can be sufficiently dissipated. This is particularly useful if the flat parts are used in the region of the power lines, in particular in the region of a battery line.
  • the flat parts can also be used in flat cables, for example B +, or a B-cables.
  • cables can be two-wire or multi-core, each wire can be formed by a flat part.
  • On opposite sides of the cable can each have one of the flat parts with a third flat part in the
  • the second flat part is coated on the side facing the first flat part with an insulator, in particular an insulating varnish. Also, the second flat part is preferably coated insulating, so that a contact of the second flat part with the first flat part or with discrete components which are soldered onto the conductor track of the conductive layer is prevented.
  • the flat parts are preferably formed of aluminum material.
  • E aluminum such as aluminum 99.5 can be used.
  • Aluminum is preferably annealed so that a good plastic
  • At least one of the flat parts is formed from a copper material.
  • a flat part made of copper material and a flat part made of aluminum material can be formed.
  • connection region on the second flat part can be provided by means of roll cladding on the flat part.
  • a contact pad is rolled on the flat part by means of roll cladding.
  • the flat conductor may be formed by the first and second flat part, which are connected to each other switchable by the semiconductor switch.
  • Connecting straps, connections with bolts, connections with holes or the like are formed. Then it may be useful if, for example, at one end of a flat conductor of the semiconductor switch with a connecting element formed as
  • Flat conductor which forms the first flat part and the connection element, which forms the second flat part, be parallel to each other.
  • the line contacts of the semiconductor switch are connected on the one hand to the contact region and on the other hand to the connection region.
  • a first line contact for example source
  • second line contact for example drain
  • a further aspect is a method for producing a line-integrated switch, in particular a line-integrated switch described above.
  • the contact area and the terminal area have mutually different heat capacities.
  • its heat capacity may be higher than that of the contact region.
  • a soldering is suitable.
  • a contact region of a second flat part can be connected to a second terminal of a semiconductor switch. Again, in particular, a soldering done. In this case, it may make sense that this connection takes place with a second energy input, which is less than the first energy input.
  • the contact region may have a lower heat capacity than the connection region. This can be, in particular, for the reason that the insulating layer and the conductive layer are applied to the flat part with the contact region, which are heat-insulating to a certain extent. In this case it may be sufficient to introduce a lower heating energy in the contact area to allow a soldering.
  • Switching contact of the semiconductor switch with test terminals are applied, whereas a second conductor contact is already connected to the connection area.
  • Conductor contact can be checked that a conductive connection between the conductor contacts is generated via the switching contact and thus there is a conductive transition between the second conductor contact and the flat part.
  • 1a is a plan view of a first flat part with a connection region according to an embodiment
  • Fig. Lb is a section through a flat part according to Fig. La;
  • Fig. 2a is a plan view of a second connection area with a
  • FIG. 2b shows a section through the second flat part according to FIG. 2a;
  • Fig. 3 is a section through an on-line switching element with the
  • Fig. 5 is a sectional view of a line-integrated switch according to a
  • Fig. 6 is a view of a compound of two flat parts with a
  • line-integrated switch according to an embodiment
  • 7 is a plan view of a flat conductor with different outlets, each with line-integrated switch according to a
  • Embodiment a sectional view of a flat cable with oppositely arranged line-integrated switches according to an embodiment
  • Fig. 1 shows a first flat part 2 in a plan view.
  • the first flat part 2 may for example be made of a copper material or an aluminum material.
  • a connection region 4 can be provided in a central region of the flat part 2.
  • the connection region 4 may be, for example, a metallic coating on the flat part 2.
  • the connection area 4 can by means of
  • the connection region 4 for example a copper element or a tin element, may be roll-laminated onto the flat part 2.
  • Fig. Lb shows the section Ib through the flat part 2. It can be seen that the flat part 2 is formed of a solid material. It can also be seen that the flat part 2 has a considerably greater material thickness than the metallic coating of the
  • the material thickness of the flat part 2 is at least ten times the material thickness of the connection region 4.
  • An insulating layer 6 can be applied to the flat part 2. Also the material thickness of the
  • Insulation layer 6 may be one tenth or less than the material thickness of the flat part 2. It can also be seen that the connection area 4 is free of the
  • Insulation layer 6 is.
  • the flat part 2 may be in its longitudinal extension between two and ten inches long and be formed for example as a connection element or as a flat conductor has a length of several tens of centimeters to over one meter. This is particularly useful when the flat part 2 is used as an energy backbone in a vehicle electrical system.
  • FIG. 2a shows a second flat part 8 in a plan view.
  • the second flat part 8 has a contact region 10.
  • the contact area 10 is directly on the
  • the contact region 10 may in particular be a metallic coating already described above.
  • a printed circuit board layer 12 on the flat part 8 with a conductive layer 14, a printed circuit or traces in the form of a printed circuit
  • FIG. 2b shows the section through the flat part 8 according to FIG. 2a. It can be seen that on the material of the flat part 8, first, a circuit board layer 12 is applied. The circuit board layer 12 may be glued to the flat part 10 or attached captively in some other way. Over the circuit board layer 12, a conductive layer 14 may be applied. The conductive layer 14 is preferably a copper layer. With the conductive layer 14, the printed circuit shown in Fig. 2a can be constructed. For this purpose, conventional methods for creating PCBs can be used. Over the conductive layer 14, an insulating layer 16 is provided.
  • the height of the contact region 10 may be selected so that it terminates preferably in a same plane as the insulating layer 16 or the conductive layer 12.
  • a semiconductor switch 18 can be placed on the flat part 8 and electrically connected to the contact region 10 with a conductor contact and with a switching contact with the printed circuit board layer 12, without stressing the semiconductor switch 18 mechanical stresses ,
  • the printed circuit board layer 12 is designed so that a contact pad is provided in the region of the boundary between the printed circuit board layer 12 and the contact region 10, on which a switching contact of the semiconductor switch can be placed and electrically contacted.
  • the switching contact of the semiconductor switch can be controlled via the circuit of the circuit board layer 12 and establish the conductive connection between the two conductor contacts of the semiconductor switch.
  • the insulating layer 16 as well as the conductive layer 14 in particular have a material thickness which is at least one tenth of the material thickness of the flat part 8 and / or the printed circuit board layer 12.
  • FIG. 3 shows the flat parts 2 and 8 in a sectional view, corresponding to FIGS. 2b and 1b. Between the flat parts 2 and 8, a semiconductor switch 18 is arranged. Of the Semiconductor switch 18 has, representative of conductor contacts of semiconductor switches, a source contact 20 and a drain contact 22. In addition, the
  • Semiconductor switch 18 representative of a switching contact of semiconductor switches, a gate contact 24. It can be seen that source contact 20, drain contact 22 and gate contact 24 are substantially in a plane to each other.
  • one of the conductor contacts in this case the drain contact 22 and the switching contact, in the present case the gate contact 24 is electrically connected to the contact region 10, respectively the conductive layer 14. This can be recognized by solder pads 26.
  • the gate contact 24 is electrically conductively connected via a solder pad 26 to a contact pad on the conductive layer 14.
  • the drain contact 22 is electrically conductively connected to the contact region 10 via a solder pad 26.
  • the drain contact 22 is preferably such that it lies directly above the contact region 10 in the connected state.
  • a connection between the drain contact 22 and the conductive layer 14 is preferably prevented by a circumferential gap between the contact region 10 and the conductive layer 14.
  • a source contact 20 may be provided on the opposite side of the drain contact 22. In the illustration, which is purely exemplary, this can be done by the source contact 20 from the plane with the drain contact 22 and the gate contact 24 via a housing cover of the molded
  • Semiconductor material of the semiconductor switch 18 is guided on the opposite side of the semiconductor switch 18.
  • Semiconductor switches can be equipped with such cooling elements as housing elements and thus allow a contacting of one of the conductor contacts via the cooling element.
  • the source contacts 20, which are in the plane with the drain contact 22 and the gate contact 24, are on the insulating layer 16. This leads to a stabilization of the semiconductor switch 18 between the flat parts 2 and 8.
  • the source contact 22 is electrically conductively connected to the connection region 4 via a solder pad 26.
  • Connection area 4 and the source contact 20 made. Here is the
  • Semiconductor switch 18 is placed with the source contact 20 lying on the connection area 4 in a soldering oven and there is the solder pad 26 between the
  • Connection area 4 and the source contact 20 made. Subsequently, this connection can be electrically tested, in which by activating the gate contact 24, a conductive connection between the source contact 20 and the drain contact 22 is made and it is checked whether the drain contact 22 is electrically connected to the flat part 2.
  • the flat part 8 can be positioned with its contact region 10 at the drain contact 22 and with the
  • Gate contact 24 and conductive layer 14 and contact area 10 and drain contact 22 are connected to Gate contact 24 and conductive layer 14 and contact area 10 and drain contact 22.
  • a lower heating energy for soldering can be introduced, which protects the semiconductor switch 18 and due to the lower
  • Heat capacity of the flat part 8 may be sufficient in the constellation shown.
  • Fig. 4 shows two flat parts 2, 8, which are formed as connection elements.
  • a flat part 2 may for example have a bore 2a which is suitable for receiving a bolt.
  • a contact part 8 may, for example, a bolt 8 a, the for example, is welded. Between the contact parts 2 and 8, a semiconductor switch 18 may be provided. Thus, the conductive connection between the flat parts 2 and 8 can be switched via the semiconductor switch 18.
  • the flat parts 2, 8 can be both or only one as a flat conductor with an extension of several tens of centimeters up to one meter. Another of the flat parts 2, 8 may for example be a connection element or a flat conductor.
  • a height offset 2b, 8b in the flat parts 2, 8 is provided in an area immediately in front of the semiconductor switch 18, for example, five to ten centimeters before the end of the respective flat part 2, 8. The height offset can amount to at least half the height of the semiconductor switch 18.
  • a height offset 2b, 8b can also be provided in only one of the flat parts 2, 8.
  • FIG. 6 shows a further embodiment.
  • a first flat part 2 can be
  • the flat conductor 2 may be insulated and be free from the insulation exclusively in the region of the connection to the second flat part 8.
  • the second flat part 8 can be electrically connected via a semiconductor switch 18 to the first flat part 2.
  • the longitudinal direction of the flat part 2 in the x direction can be at an angle to
  • Fig. 7 shows a further embodiment in which the flat part 2 is formed as a flat conductor.
  • the longitudinal direction of the flat part 2 is shown along the x-axis.
  • flat parts 8 can branch off at different points of the flat part 2, specifically in different longitudinal extension directions along different axes yi, y 2 , y 3 , y 4 . It can be seen, for example, that a flat part 8, which extends along the axis y 3 , is arranged on a surface of the flat part 2 opposite to another flat part 8.
  • the axis y 4 extends at an angle to the x axis.
  • Fig. 8 shows the possibility to provide an outlet on each surface of a flat part 2. It can be seen that a first semiconductor switch 18 connects the flat part 2 with a flat part 8 on a first surface and a second one
  • the flat part 2 connects with a flat part 8. As a result, outflows on both sides of the flat part 2 are possible.
  • On-board network potentials to be connected within a vehicle electrical system It is also possible for one of the flat conductors 2 'to be used as a B + conductor and another for the flat conductors 2 "as a ground return.
  • each of the flat parts 2 ', 2 " can be connected to a semiconductor switch 18', 18" and thus have an outlet to a flat part 8 ', 8 ".Thus it is possible to separate a great variety of potentials, in particular in an electrical system branching from each other to different consumers or components switchable.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Insulated Conductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
EP17714166.0A 2016-06-14 2017-03-22 Leitungsintegrierter halbleiterschalter und verfahren zu dessen herstellung Pending EP3469664A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016110847.2A DE102016110847B4 (de) 2016-06-14 2016-06-14 Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters
PCT/EP2017/056761 WO2017215798A1 (de) 2016-06-14 2017-03-22 Leitungsintegrierter halbleiterschalter und verfahren zu dessen herstellung

Publications (1)

Publication Number Publication Date
EP3469664A1 true EP3469664A1 (de) 2019-04-17

Family

ID=58448512

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17714166.0A Pending EP3469664A1 (de) 2016-06-14 2017-03-22 Leitungsintegrierter halbleiterschalter und verfahren zu dessen herstellung

Country Status (6)

Country Link
US (1) US10840207B2 (es)
EP (1) EP3469664A1 (es)
CN (1) CN109478749B (es)
DE (1) DE102016110847B4 (es)
MX (1) MX2018015715A (es)
WO (1) WO2017215798A1 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016110847B4 (de) * 2016-06-14 2022-02-17 Auto-Kabel Management Gmbh Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters
DE102020216305B4 (de) 2020-12-18 2022-10-13 Leoni Bordnetz-Systeme Gmbh Elektrische Schaltvorrichtung
CN113131291B (zh) * 2021-03-11 2023-05-12 东莞市晟合科技有限公司 一种搭载电子元器件的连接线及其制作方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2235455A1 (de) * 1971-07-28 1973-05-03 Halbleiterwerk Frankfurt Oder Traegerstreifen fuer halbleiterbauelemente
JPS62142125U (es) * 1986-03-03 1987-09-08
KR940010910B1 (ko) * 1990-04-06 1994-11-19 스미토모 고쿠슈 긴조쿠 가부시기가이샤 반도체 패키지
JP2531928B2 (ja) * 1993-11-05 1996-09-04 株式会社東芝 半導体スタック
AU705177B1 (en) * 1997-11-26 1999-05-20 Kabushiki Kaisha Toshiba Semiconductor device
DE59900800D1 (de) * 1998-03-12 2002-03-14 Auto Kabel Man Gmbh Elektrisches kabel
US6014066A (en) * 1998-08-17 2000-01-11 Trw Inc. Tented diode shunt RF switch
FR2822591A1 (fr) * 2001-03-22 2002-09-27 Commissariat Energie Atomique Assemblage de composants d'epaisseurs diverses
WO2002083549A1 (en) * 2001-04-17 2002-10-24 Telefonaktiebolaget Lm Ericsson (Publ) Printed circuit board integrated switch
JP4039202B2 (ja) * 2002-10-16 2008-01-30 日産自動車株式会社 積層型半導体装置およびその組み立て方法
JP4564937B2 (ja) * 2006-04-27 2010-10-20 日立オートモティブシステムズ株式会社 電気回路装置及び電気回路モジュール並びに電力変換装置
WO2008142865A1 (ja) * 2007-05-21 2008-11-27 Kabushiki Kaisha Toshiba インダクタンス素子とその製造方法、およびそれを用いたスイッチング電源
US7952166B2 (en) * 2008-05-22 2011-05-31 Infineon Technologies Austria Ag Semiconductor device with switch electrode and gate electrode and method for switching a semiconductor device
JP5067267B2 (ja) 2008-06-05 2012-11-07 三菱電機株式会社 樹脂封止型半導体装置とその製造方法
JP2010225720A (ja) 2009-03-23 2010-10-07 Mitsubishi Electric Corp パワーモジュール
US8724325B2 (en) * 2009-05-19 2014-05-13 Hamilton Sundstrand Corporation Solid state switch arrangement
KR101343289B1 (ko) * 2010-05-18 2013-12-18 도요타지도샤가부시키가이샤 반도체 장치 및 그 제조 방법
JP5460653B2 (ja) * 2011-07-14 2014-04-02 本田技研工業株式会社 半導体装置
JP2013065620A (ja) 2011-09-15 2013-04-11 Sumitomo Electric Ind Ltd 配線シート付き電極端子、配線構造体、半導体装置、およびその半導体装置の製造方法
JP2013073945A (ja) * 2011-09-26 2013-04-22 Sumitomo Electric Ind Ltd 配線シート付き電極端子、配線構造体、半導体装置、およびその半導体装置の製造方法
DE102012202281A1 (de) 2012-02-15 2013-08-22 Infineon Technologies Ag Halbleiteranordnung für Druckkontaktierung
CN103795384B (zh) * 2012-10-31 2017-04-19 台达电子企业管理(上海)有限公司 开关电路封装模块
US8987875B2 (en) * 2013-03-08 2015-03-24 Delphi Technologies, Inc. Balanced stress assembly for semiconductor devices
DE102014101882A1 (de) 2014-02-14 2015-08-20 Heraeus Deutschland GmbH & Co. KG Verfahren zur Herstellung einer bondbaren Beschichtung auf einem Trägerband
DE102014104013A1 (de) * 2014-03-24 2015-09-24 Infineon Technologies Austria Ag Leistungshalbleiterbauteil
DE102014006346A1 (de) * 2014-04-30 2015-11-05 Ellenberger & Poensgen Gmbh Hochstromschalter
US9666703B2 (en) * 2014-12-17 2017-05-30 Great Wall Semiconductor Corporation Semiconductor devices with cavities
DE102016110847B4 (de) * 2016-06-14 2022-02-17 Auto-Kabel Management Gmbh Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters

Also Published As

Publication number Publication date
MX2018015715A (es) 2019-04-29
CN109478749A (zh) 2019-03-15
WO2017215798A1 (de) 2017-12-21
DE102016110847A1 (de) 2017-12-14
US10840207B2 (en) 2020-11-17
US20190172811A1 (en) 2019-06-06
DE102016110847B4 (de) 2022-02-17
CN109478749B (zh) 2021-05-07

Similar Documents

Publication Publication Date Title
DE112016005766B4 (de) Schaltungsanordnung und elektrischer anschlusskasten
EP2338207B1 (de) Rfid-transponderantenne
EP3095307B1 (de) Leiterplatte, schaltung und verfahren zur herstellung einer schaltung
DE112016005794T5 (de) Schaltungsanordnung und elektrischer Anschlusskasten
DE102016226231A1 (de) Isolierte sammelschiene, verfahren zum herstellen einer isolierten sammelschiene und elektronisches gerät
DE102016110847B4 (de) Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters
DE10126655A1 (de) Leiterplatte mit mindestens einem elektronischen Bauteil
DE102007041892A1 (de) Elektrische Schaltanordnung mit einem MID-Schaltungsträger und einer damit verbundenen Verbindungsschnittstelle
EP2434846B1 (de) Verdrahtungselement, Leistungsverteiler und Fahrzeugbatterie
DE102008058025B4 (de) Schaltungsträger
EP2091081B1 (de) Schaltungsanordnung mit Bondverbindung
WO2018149687A1 (de) Multilayer-leiterplatte sowie elektronische anordnung mit einer solchen
WO2019057710A1 (de) Elektrische schaltvorrichtung
DE102015216417B4 (de) Leiterplatte und Verfahren zur Herstellung solch einer Leiterplatte
DE102023000391B3 (de) Anschlussvorrichtung für einen elektrischen Leiter und Kontaktierungseinheit
DE102012223077A1 (de) Kontaktanordnung für einen mehrlagigen Schaltungsträger
DE102020203145B4 (de) Leiterplattenanordnung
DE19922468C2 (de) Verfahren zur Herstellung einer elektrischen Verbindung zwischen mehrlagigen Leiterstrukturen
DE102022210631A1 (de) Komponentenanordnung für eine Leistungselektronik und Verfahren zum Bereitstellen einer Komponentenanordnung für eine Leistungselektronik
EP0966777B1 (de) Elektrische baugruppe
EP2522038A2 (de) Kontaktierte solarzelle sowie verfahren zu deren herstellung
DE4242462A1 (de) Verfahren zur Herstellung von isolierten Leiterbahnkreuzungen auf gedruckten Leiterplatten
DE102018220426A1 (de) Verfahren zum Wellenlöten; Leiterplatte; Elektronikmodul
EP1047291A1 (de) Lötbrücke
WO2007143961A1 (de) Elektrisches verbindungselement

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20181204

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20210511

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

R17C First examination report despatched (corrected)

Effective date: 20210719

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230513