DE69131872D1 - Dynamische Halbleiterspeicherschaltung - Google Patents
Dynamische HalbleiterspeicherschaltungInfo
- Publication number
- DE69131872D1 DE69131872D1 DE69131872T DE69131872T DE69131872D1 DE 69131872 D1 DE69131872 D1 DE 69131872D1 DE 69131872 T DE69131872 T DE 69131872T DE 69131872 T DE69131872 T DE 69131872T DE 69131872 D1 DE69131872 D1 DE 69131872D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory circuit
- dynamic semiconductor
- dynamic
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2119948A JP2533221B2 (ja) | 1990-05-11 | 1990-05-11 | ダイナミック型ランダムアクセスメモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69131872D1 true DE69131872D1 (de) | 2000-01-27 |
DE69131872T2 DE69131872T2 (de) | 2000-05-18 |
Family
ID=14774146
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69131872T Expired - Fee Related DE69131872T2 (de) | 1990-05-11 | 1991-05-10 | Dynamische Halbleiterspeicherschaltung |
DE69126912T Expired - Fee Related DE69126912T2 (de) | 1990-05-11 | 1991-05-10 | Halbleiteranordnung und ihre Prüfungsverfahren |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69126912T Expired - Fee Related DE69126912T2 (de) | 1990-05-11 | 1991-05-10 | Halbleiteranordnung und ihre Prüfungsverfahren |
Country Status (5)
Country | Link |
---|---|
US (2) | US5428576A (de) |
EP (2) | EP0456254B1 (de) |
JP (1) | JP2533221B2 (de) |
KR (1) | KR950014679B1 (de) |
DE (2) | DE69131872T2 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2533221B2 (ja) * | 1990-05-11 | 1996-09-11 | 株式会社東芝 | ダイナミック型ランダムアクセスメモリ |
JP3392497B2 (ja) * | 1994-02-25 | 2003-03-31 | 株式会社東芝 | テスト電位転送回路およびこれを用いた半導体記憶装置 |
US5724286A (en) * | 1994-12-14 | 1998-03-03 | Mosaid Technologies Incorporated | Flexible DRAM array |
US6551574B2 (en) * | 1995-06-07 | 2003-04-22 | Rhomed Incorporated | Tuftsin metallopeptide analogs and uses thereof |
KR0170286B1 (ko) * | 1995-12-22 | 1999-03-30 | 김광호 | 반도체 메모리장치의 전압 승압회로 |
US5644258A (en) * | 1996-01-04 | 1997-07-01 | Winbond Electronics Corp. | Driver circuit, with low idle power consumption, for an attachment unit interface |
JP3601901B2 (ja) * | 1996-03-26 | 2004-12-15 | 株式会社 沖マイクロデザイン | 昇圧回路 |
US5917766A (en) * | 1996-05-28 | 1999-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably |
US5999466A (en) * | 1998-01-13 | 1999-12-07 | Micron Technology, Inc. | Method, apparatus and system for voltage screening of integrated circuits |
JPH11260053A (ja) * | 1998-03-12 | 1999-09-24 | Nec Corp | 半導体記憶装置の昇圧回路 |
JP2000339996A (ja) * | 1999-05-31 | 2000-12-08 | Nec Corp | 半導体記憶装置およびそのバーンインテスト方法 |
US8611164B2 (en) | 2011-08-01 | 2013-12-17 | International Business Machines Corporation | Device and method for detecting resistive defect |
CN105827101B (zh) * | 2016-05-06 | 2019-02-05 | 成都芯源***有限公司 | 电压转换集成电路、自举电路以及开关驱动方法 |
JP7175555B2 (ja) * | 2018-03-09 | 2022-11-21 | エイブリック株式会社 | テスト回路及び半導体装置 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4418403A (en) * | 1981-02-02 | 1983-11-29 | Mostek Corporation | Semiconductor memory cell margin test circuit |
JPS5891594A (ja) * | 1981-11-27 | 1983-05-31 | Fujitsu Ltd | ダイナミツク型半導体記憶装置 |
JPS60157250A (ja) * | 1984-01-25 | 1985-08-17 | Mitsubishi Electric Corp | Mosダイナミツクramのスクリ−ニング方法 |
JPS61219162A (ja) * | 1985-03-25 | 1986-09-29 | Nec Corp | 半導体装置の配線パタ−ン |
JPH0789433B2 (ja) * | 1985-11-22 | 1995-09-27 | 株式会社日立製作所 | ダイナミツク型ram |
JPS6394499A (ja) * | 1986-10-07 | 1988-04-25 | Toshiba Corp | 半導体記憶装置 |
US4751679A (en) * | 1986-12-22 | 1988-06-14 | Motorola, Inc. | Gate stress test of a MOS memory |
JPS63181196A (ja) * | 1987-01-22 | 1988-07-26 | Oki Electric Ind Co Ltd | 半導体集積回路装置 |
JPS63183689A (ja) * | 1987-01-26 | 1988-07-29 | Hitachi Ltd | 半導体集積回路装置 |
JP2684365B2 (ja) * | 1987-04-24 | 1997-12-03 | 株式会社日立製作所 | 半導体記憶装置 |
JPS6455857A (en) * | 1987-08-26 | 1989-03-02 | Nec Corp | Semiconductor integrated device |
US4809231A (en) * | 1987-11-12 | 1989-02-28 | Motorola, Inc. | Method and apparatus for post-packaging testing of one-time programmable memories |
JPH01166391A (ja) * | 1987-12-23 | 1989-06-30 | Toshiba Corp | スタティック型ランダムアクセスメモリ |
JPH0218779A (ja) * | 1988-07-05 | 1990-01-23 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
JP2533221B2 (ja) * | 1990-05-11 | 1996-09-11 | 株式会社東芝 | ダイナミック型ランダムアクセスメモリ |
JPH0770620B2 (ja) * | 1990-12-26 | 1995-07-31 | 株式会社東芝 | 半導体記憶装置 |
JPH04225182A (ja) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | 半導体記憶装置 |
JP2829134B2 (ja) * | 1990-12-27 | 1998-11-25 | 株式会社東芝 | 半導体記憶装置 |
JP3381929B2 (ja) * | 1990-12-27 | 2003-03-04 | 株式会社東芝 | 半導体装置 |
JPH0756759B2 (ja) * | 1990-12-27 | 1995-06-14 | 株式会社東芝 | スタティック型半導体記憶装置 |
KR960007478B1 (ko) * | 1990-12-27 | 1996-06-03 | 가부시키가이샤 도시바 | 반도체장치 및 반도체장치의 제조방법 |
JP2829135B2 (ja) * | 1990-12-27 | 1998-11-25 | 株式会社東芝 | 半導体記憶装置 |
JP2925337B2 (ja) * | 1990-12-27 | 1999-07-28 | 株式会社東芝 | 半導体装置 |
JPH07123134B2 (ja) * | 1990-12-27 | 1995-12-25 | 株式会社東芝 | 半導体装置 |
-
1990
- 1990-05-11 JP JP2119948A patent/JP2533221B2/ja not_active Expired - Fee Related
-
1991
- 1991-05-10 EP EP91107613A patent/EP0456254B1/de not_active Expired - Lifetime
- 1991-05-10 KR KR1019910007520A patent/KR950014679B1/ko not_active IP Right Cessation
- 1991-05-10 DE DE69131872T patent/DE69131872T2/de not_active Expired - Fee Related
- 1991-05-10 EP EP96108851A patent/EP0740308B1/de not_active Expired - Lifetime
- 1991-05-10 DE DE69126912T patent/DE69126912T2/de not_active Expired - Fee Related
-
1994
- 1994-10-19 US US08/325,636 patent/US5428576A/en not_active Expired - Fee Related
-
1995
- 1995-06-07 US US08/480,926 patent/US5568436A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR950014679B1 (ko) | 1995-12-13 |
EP0740308B1 (de) | 1999-12-22 |
US5428576A (en) | 1995-06-27 |
DE69126912D1 (de) | 1997-08-28 |
JP2533221B2 (ja) | 1996-09-11 |
EP0456254A2 (de) | 1991-11-13 |
EP0456254B1 (de) | 1997-07-23 |
US5568436A (en) | 1996-10-22 |
JPH0417191A (ja) | 1992-01-21 |
KR910020731A (ko) | 1991-12-20 |
DE69131872T2 (de) | 2000-05-18 |
DE69126912T2 (de) | 1997-12-04 |
EP0740308A2 (de) | 1996-10-30 |
EP0456254A3 (en) | 1991-12-27 |
EP0740308A3 (de) | 1996-12-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |