CN1649146A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1649146A
CN1649146A CNA2004101048396A CN200410104839A CN1649146A CN 1649146 A CN1649146 A CN 1649146A CN A2004101048396 A CNA2004101048396 A CN A2004101048396A CN 200410104839 A CN200410104839 A CN 200410104839A CN 1649146 A CN1649146 A CN 1649146A
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China
Prior art keywords
mentioned
conductor component
semiconductor chip
semiconductor
semiconductor device
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Granted
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CNA2004101048396A
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CN100521196C (zh
Inventor
川岛彻也
三岛彰
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NEC Electronics Corp
Renesas Electronics Corp
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Renesas Technology Corp
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Publication of CN1649146A publication Critical patent/CN1649146A/zh
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Abstract

本发明的课题是谋求封入了多个半导体芯片的半导体器件的散热性的提高。在输入侧板状引线部5上配置了控制用功率MOSFET芯片2，在该芯片的背面上形成了漏极端子DT1，另一方面，在主面上形成了源极端子ST1和栅极端子GT1，该源极端子ST1与源极用板状引线部12连接，此外，在输出侧板状引线部6上配置了同步用功率MOSFET芯片3，在该芯片的背面上形成了漏极端子DT2，将输出侧板状引线部6连接到该漏极端子DT2上，再者，在同步用功率MOSFET芯片3的主面上形成了源极端子ST2和栅极端子GT2，连接该源极端子ST2与源极用板状引线部13，通过露出源极用板状引线部12、13，可提高MCM1的散热性。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别是涉及应用于在封装体中封入了多个半导体芯片的半导体器件有效的技术。
背景技术
在现有的半导体器件中，在各半导体芯片的表面上经焊锡接合了热沉(第1导体构件)的背面，在各半导体芯片的背面上接合了第2导体构件的表面。此外，在热沉的表面上经焊锡接合了第3导体构件的背面，再者，经键合引线电连接了规定的半导体芯片的接合区(land)与控制用端子。利用树脂对各半导体芯片、热沉、第2导体构件的表面、第3导体构件的背面、键合引线和控制用端子的一部分进行了封装(例如，参照专利文献1)。
此外，在上述半导体器件中，在第2导体构件的背面上经平板状的绝缘构件与外部冷却构件连接，进一步促进散热(例如，参照专利文献2)。
【专利文献1】特开2002-110893(图1)
【专利文献2】特开2003-46036(图1)
近年来，半导体器件的高集成化及小型化得到了进展，特别是对于利用绝缘材料对多个半导体芯片进行了封装的半导体器件(被称为MCM(多芯片组件))进行了开发。
在上述MCM的应用例的1个中，有用于电源电路等的开关电路。其中，在个人计算机等的信息设备中广泛地使用了绝缘型DC/DC(直流/直流)变换器，伴随CPU(中央处理单元)等的大电流化或高频化，对这些制品要求高效率化和小型化。
DC/DC变换器由控制用和同步用的功率MOSFET(金属氧化物半导体场效应晶体管)、进行这些晶体管的导通/截止的驱动器IC(集成电路)和除此以外的扼流圈和电容器等构成，但一般来说在DC/DC变换器用MCM中，在1个封装体中封入了2个功率MOSFET和1个驱动器IC。
以这种方式在1个封装体中封入多个半导体芯片，除了减少安装面积外，其目的在于减少电路上的寄生电感或寄生电阻分量。
再有，由于电源电路的大电流化或高频化的缘故，起因于这些寄生分量的损耗变大，为了抑制这一点，必须缩短各芯片间、驱动器IC-MOSFET间、输出端子-负载间的布线图形。因此，预期通过在接近的位置上封入驱动器IC和MOSFET、将构成电源电路的半导体元件作成1个封装体从而能在负载的附近安装的电源用MCM将成为今后的电源设备的主流。
即，在由MCM进行的安装中，与现有的在印刷基板上配置个别地封装了的各元件的安装相比，缩短了布线距离，大幅度地减少了寄生电感或寄生电阻，可实现低损耗的电路。
但是，在MCM中，通过将多个半导体芯片作成1个封装体，虽然减少了安装面积，但与之相反而存在散热性降低的问题。
此外，如本发明者研究了的图16的比较例中所示，在MCM中，由于用引线电连接了芯片-引线框间的主要的电流路径，故在整体的寄生分量中引线部分占了较大的比例，该引线部分中的电阻或电感的寄生分量的增加成为问题。
发明内容
本发明的目的在于提供谋求电特性的提高的半导体器件。
此外，本发明的另一目的在于提供谋求散热性的提高的半导体器件。
通过本说明书的记述和附图，本发明的上述和其它的目的及新的特征将变得很明白。
如果简单地说明本申请中公开了的发明中的代表性的内容的概要，则如下所述。
即，本发明具有：在各自的主面上形成了端子的多个半导体芯片；与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；对上述多个半导体芯片进行封装的封装体；以及分别与上述多个半导体芯片电连接的多个外部连接端子，由上述板状导体构件进行了连接的上述至少2个半导体芯片分别具有晶体管电路，上述板状导体构件从上述封装体露出。
此外，本发明具有：在各自的主面上形成了端子的多个半导体芯片；与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；对上述多个半导体芯片进行树脂封装的封装体；以及分别与上述多个半导体芯片电连接的多个外部连接端子，上述板状导体构件从上述封装体露出，与上述板状导体构件中的一方的半导体芯片的连接部位和与另一方的连接部位在上述封装体的表面背面中的某一方或上述封装体的内部的各自的半导体芯片的外侧进行了连接。
再者，本发明具有：在各自的主面上形成了端子的多个半导体芯片；与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；对上述多个半导体芯片进行树脂封装的封装体；以及分别与上述多个半导体芯片电连接的并配置在上述封装体的背面的周围边缘部上多个外部连接端子，上述板状导体构件从上述封装体的表面背面中的至少某一方露出。
此外，本发明在封入了多个半导体芯片的半导体器件中，用板状的导体连接了元件间或端子-元件间的主要的电流路径，电位不同的至少3个导体的一部分在半导体器件的表面或背面或该两面上露出。
此外，在本发明中，用板状的导体串联地连接了多个半导体芯片，而且在该导体的同一面上连接了多个半导体芯片，以上下反转的方式封入了构成半导体器件的多个半导体芯片中的1个或多个半导体芯片。
作为一例，如果举出DC/DC变换器MCM，则控制用功率MOSFET的漏极端子经板状的导体与作为外部连接端子的输入端子电连接，或直接连接到作为输入端子的一部分的板状的导体上，同步用功率MOSFET也同样地经板状的导体与作为外部连接端子的接地端子电连接，或直接连接到作为接地端子的一部分的板状的导体上。
此外控制用功率MOSFET的源极端子和同步用功率MOSFET的漏极端子分别连接到板状的导体上，用某个导体连接了上述板状的导体，或者控制用功率MOSFET的源极端子和同步用功率MOSFET的漏极端子分别连接到共同的导体的一部分上。
此外，该导体电连接到作为外部连接端子的输出端子上，或者是输出端子的一部分。
再者，分别与输入端子、接地端子、输出端子连接了的或作为其一部分的板状的导体的一部分或整体在封入了半导体器件的绝缘材料的外部露出。
此外，在控制用功率MOSFET的源极端子和同步用功率MOSFET芯片的漏极端子的连接中，使用了共同的板状导体，使同步用功率MOSFET上下反转连接到导体的共同的表面上。
如果简单地说明本申请中公开了的发明中的代表性的发明的效果的概要，则如下所述。
通过具有连接2个半导体芯片的端子的板状导体构件，与引线连接相比，可谋求寄生电阻和寄生电感的减少，可谋求半导体器件中的电特性的提高。再者，通过上述板状导体构件从封装体露出，可谋求半导体器件中的散热性的提高。
附图说明
图1是透过封装体示出本发明的实施例1的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图。
图2是示出沿图1中示出的A-A线切断了的剖面的结构的剖面图。
图3是示出图1中示出的半导体器件的结构的背面图。
图4是示出图1中示出的半导体器件的结构的外观斜视图。
图5是示出本发明的实施例1的变形例的半导体器件的结构的剖面图。
图6是示出本发明的实施例1的变形例的半导体器件的结构的剖面图。
图7是示出本发明的实施例1的变形例的半导体器件的结构的剖面图。
图8是示出图1中示出的半导体器件(非绝缘型DC/DC变换器)中的安装时的等效电路的一例的电路图。
图9是透过封装体示出本发明的实施例2的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图。
图10是示出沿图9中示出的B-B线切断了的剖面的结构的剖面图。
图11是示出图9中示出的半导体器件的结构的背面图。
图12是示出图9中示出的半导体器件的结构的外观斜视图。
图13是示出本发明的实施例3的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的剖面图。
图14是示出本发明的实施例3的变形例的半导体器件的结构的剖面图。
图15是透过封装体示出本发明的实施例4的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图。
图16是透过封装体示出比较例的电源用多芯片组件的结构的平面图。
图17是透过图1中示出的半导体器件的内部示出的斜视图。
具体实施方式
在以下的实施例中，除了特别必要时以外，原则上不重复进行同一或同样的部分的说明。
再者，在以下的实施例中，为了方便起见，在有其必要时，分割为多个部分或实施例来说明，但除了特别明确地示出的情况外，这些部分或实施例并不是彼此没有关系的，一方成为另一方的一部分或全部的变形例、细节、补充说明等的关系。
此外，在以下的实施例中，在提及要素的数目等(包含个数、数值、量、范围等)的情况下，除了在特别明确地示出的情况和在原理上明确地被限定于特定数的情况下，不限定于该特定数，可以大于等于特定数或小于等于特定数。
以下，根据附图，详细地说明本发明的实施例。再有，在说明实施例用的全部的图中，对具有同一功能的构件附以同一符号，省略其重复的说明。
(实施例1)
图1是透过封装体示出本发明的实施例1的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图，图17是透过图1中示出的半导体器件的内部示出的斜视图，图2是示出沿图1中示出的A-A线切断了的剖面的结构的剖面图，图3是示出图1中示出的半导体器件的结构的背面图，图4是示出图1中示出的半导体器件的结构的外观斜视图，图5～图7是分别示出本发明的实施例1的变形例的半导体器件的结构的剖面图，图8是示出图1中示出的半导体器件(非绝缘型DC/DC变换器)中的安装时的等效电路的一例的电路图，图16是透过封装体示出比较例的电源用多芯片组件的结构的平面图。
图1～图4、图17中示出的实施例1的半导体器件在1个封装体(封入用绝缘树脂)17中封入了多个半导体芯片，在本实施例1中，作为上述半导体器件的一例，举出非绝缘型DC/DC变换器用的MCM(多芯片组件)1来说明。
再有，MCM1如图3中所示，是在封装体17的背面17b的周围边缘部上配置了多个外部连接端子11的无引线型的QFN(方形平面无引线封装)结构。
本实施例1的MCM1的基本结构由多个半导体芯片、与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件、对上述多个半导体芯片进行封装的封装体17和在封装体17的背面17b的周围边缘部上配置的多个外部连接端子11构成，由上述板状导体构件进行了连接的上述至少2个半导体芯片分别具有晶体管电路，上述板状导体构件从上述封装体17露出。
再有，MCM1具有作为第1半导体芯片的控制用功率MOSFET芯片2、利用板状导体构件与该控制用功率MOSFET芯片2串联地电连接的作为第2半导体芯片的同步用功率MOSFET芯片3和对这些芯片的工作进行导通/截止的作为第3半导体芯片的驱动器IC芯片4，在封装体17中对该3个半导体芯片进行了封装(封入)。
即，在MCM1上安装了分别具有电源用的晶体管电路的2个半导体芯片(第1和第2半导体芯片)和具有控制该2个半导体芯片的驱动器电路的1个半导体芯片(第3半导体芯片)。
如果说明本实施例1的MCM1的详细的结构，则如图1、图2中所示，在输入侧板状引线部(第1驱动器IC)5上配置了控制用功率MOSFET(第1晶体管)2。即，在控制用功率MOSFET芯片2的背面2b上形成了成为控制用功率MOSFET的漏极端子DT1(第1输出电极)的端子部，在该漏极端子DT1上连接了作为第1板状导体构件的输入侧板状引线部5。
另一方面，在控制用功率MOSFET芯片2的主面2a上形成了控制用功率MOSFET的源极端子(第2输出电极)ST1和成为栅极端子(输入电极)GT1的端子部，连接了控制用功率MOSFET芯片2的主面2a的源极端子ST1与作为第2板状导体构件的源极用板状引线部12。
此外，在输出侧板状引线部6上配置了同步用功率MOSFET芯片(第2晶体管)3。即在同步用功率MOSFET芯片3的背面3b上形成了成为同步用功率MOSFET的漏极端子(第1输出端子)DT2的端子部，在该漏极端子DT2上连接了作为第3板状导体构件的输出侧板状引线部6。另一方面，在同步用功率MOSFET芯片3的主面3a上形成了同步用功率MOSFET的源极端子ST2和成为栅极端子(输入电极)GT2的端子部，连接了同步用功率MOSFET芯片3的主面3a的源极端子ST2与作为第4板状导体构件的源极用板状引线部13。
此外，MCM1具有接地侧板状引线部7和驱动器侧板状引线部8，在驱动器侧板状引线部8上配置了驱动器IC芯片4。即，连接了驱动器IC芯片4与驱动器侧板状引线部8。在驱动器IC芯片4中，分别利用作为金线等的金属细线的引线10电连接了其主面4a的多个端子9中的一部分的端子9、功率MOSFET芯片的栅极端子GT1、源极端子ST1、栅极端子GT2和源极端子ST2，用于各功率MOSFET的导通/截止的控制。
驱动器IC芯片4的主面4a的其它的端子9分别是电源电压端子、引导端子、电压确认用端子和控制信号输入端子等，利用引线10和与其对应的外部连接端子11进行了连接。
如图3中所示，安装了各半导体芯片的输入侧板状引线部5、输出侧板状引线部6和驱动器侧板状引线部8在MCM1的封装体17的背面17b上分别露出一部分或全部，不仅作为与印刷安装基板电连接用的外部连接端子，而且也起到对上述印刷安装基板放出热的散热构件的作用。
此外，如图1、图2中所示，源极用板状引线部12电连接了控制用功率MOSFET芯片2的源极端子ST1与输出侧板状引线部6，同样，源极用板状引线部13电连接了同步用功率MOSFET芯片3的源极端子ST2与接地侧板状引线部7。
再有，如图4中所示，源极用板状引线部12和源极用板状引线部13分别在MCM1的封装体17的表面17a上露出其一部分。
此外，如图2中所示，控制用功率MOSFET芯片2和同步用功率MOSFET芯片3中的各自的背面2b、3b的漏极端子DT1、DT2例如经银膏14等的管芯键合材料分别接合到输入侧板状引线部5、输出侧板状引线部6上。
另一方面，控制用功率MOSFET芯片2和同步用功率MOSFET芯片3中的各自的主面2a、3a的源极端子ST1、ST2例如经金突点15等的多个导电性的突起电极分别接合到源极用板状引线部12、13上。
但是，控制用功率MOSFET芯片2和同步用功率MOSFET芯片3中的主面2a、3a的源极端子ST1、ST2分别与源极用板状引线部12、13的接合也可使用由焊锡构成的突起电极或膏状的导电性的粘接剂等来进行。
在此，图2、图5、图6和图7示出第2板状导体构件与第3板状导体构件和第4板状导体构件与接地侧板状引线部7中的各种连接状态。
如图2中所示，分别经导体16电连接了源极用板状引线部12与输出侧板状引线部6和源极用板状引线部13与接地侧板状引线部7。此外，如图5的变形例中所示，将源极用板状引线部12a、13a加工成分别到与输出侧板状引线部6、接地侧板状引线部7连接的部分为止成为同一导体构件，也可使用焊锡18等来连接。由源极用板状引线部12、导体16、输出侧板状引线部6构成的导体构件(第2导体构件或第3导体构件)具有2个部位的弯曲部，呈大致S字形状。
此外，如图6或图7的变形例中所示，也可一体地形成源极用板状引线部(第2板状导体构件)12与输出侧板状引线部(第3板状导体构件)6，进而一体地形成源极用板状引线部13与接地侧板状引线部7。图6中示出的变形例是利用冲压加工一体地形成的情况，此外，图7中示出的变形例是利用弯曲加工一体地形成的情况。
这样，在本实施例1的MCM1中，在封装体17的内部的控制用功率MOSFET芯片2和同步用功率MOSFET芯片3的各自的外侧连接并电连接了在封装体17的表面17a一侧配置的源极用板状引线部12与在封装体17的背面17b一侧配置的输出侧板状引线部6。
其次，图8示出MCM1的安装时的等效电路的一例。MCM1用布线与线圈20、电容器22、23、进而是负载24、输入电源21等进行了连接。在非绝缘型DC/DC变换器19中，在控制用功率MOSFET芯片2和同步用功率MOSFET芯片3中发生所产生的发热中的大部分。
按照本实施例1的MCM1，因为作为电流路径的板状导体构件在其一个面上连接到半导体芯片上，而且其另一个面在封装体17的外部露出，故可提高散热性。在封装体17的背面17b露出的板状导体构件用作外部连接用的端子部，同时可使热散逸到安装MCM1的印刷布线基板上。再者，在封装体17的表面17a露出的板状导体构件具有提高直接朝向外部气氛的热的排出、或对在MCM1上安装的散热片27(参照图13、图14)或热沉等的散热构件的传热效果的作用。
即，可将在控制用功率MOSFET芯片2和同步用功率MOSFET芯片3中发生的热从在封装体17的背面17b露出的输入侧板状引线部5和输出侧板状引线部6传递给印刷安装基板来散热，再者，由于可从在封装体17的表面17a露出的源极用板状引线部12和源极用板状引线部13对外部放出热，故可得到更高的散热效果。
因而，可谋求MCM1中的散热性的提高。再者，可提高MCM1的电压变换效率。
此外，通过分别利用源极用板状引线部12、13连接控制用功率MOSFET芯片2的源极端子ST1与输出侧板状引线部6，进而连接同步用功率MOSFET芯片3的源极端子ST2与接地侧板状引线部7，与图16中示出的比较例的多芯片组件那样的一般采用的使用了金线等的引线25的引线连接相比，由于本实施例1的MCM1可增加电流流动的路径的剖面面积，故减小了电阻或电感的寄生分量，可有助于变换效率的提高。
即，与引线连接相比可谋求寄生电阻和寄生电感的减少，可谋求MCM1中的电特性的提高。
此外，串联地连接第1晶体管的第1输出电极和第2输出电极的电流路径与第2晶体管的第1输出电极和第2输出电极的电流路径，通过以机械的方式使第1导体构件、第2导体构件、第3导体构件、第1晶体管、第2晶体管实现一体化来构成，可容易地制造可靠性高的半导体器件。
(实施例2)
图9是透过封装体示出本发明的实施例2的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图，图10是示出沿图9中示出的B-B线切断了的剖面的结构的剖面图，图11是示出图9中示出的半导体器件的结构的背面图，图12是示出图9中示出的半导体器件的结构的外观斜视图。
本实施例2的半导体器件与实施例1同样，是非绝缘型DC/DC变换器用的MCM(多芯片组件)1，是封入了控制用功率MOSFET芯片2、同步用功率MOSFET芯片3和使其导通/截止的驱动器IC芯片4的半导体封装体。
如果说明本实施例2的MCM1的结构，则如图9、图10中所示，在输入侧板状引线部5上配置了控制用功率MOSFET芯片2。再者，在控制用功率MOSFET芯片2的主面2a上形成了控制用功率MOSFET的源极端子ST1和成为栅极端子GT1的端子部，此外，在控制用功率MOSFET芯片2的背面2b上形成了成为控制用功率MOSFET的漏极端子DT1的端子部。
另一方面，与实施例1不同，在接地侧板状引线部7上配置了同步用功率MOSFET芯片3。即，如图10中所示，与作为第1半导体芯片的控制用功率MOSFET芯片2表面背面相反的方向上(上下反转)配置了作为第2半导体芯片的同步用功率MOSFET芯片3。再有，在同步用功率MOSFET芯片3的主面3a上形成了成为同步用功率MOSFET的漏极端子DT2的端子部，此外，在同步用功率MOSFET芯片3的背面3b上形成了同步用功率MOSFET的源极端子ST2和成为栅极端子GT2的端子部。
再者，该DC/DC变换器用MCM1如图9中所示，具有输出侧板状引线部6。
此外，在驱动器侧板状引线部8上配置了驱动器IC芯片4，分别电连接了该驱动器IC芯片4的主面4a的端子9的一部分与控制用功率MOSFET芯片2的栅极端子GT1、源极端子ST1、同步用功率MOSFET芯片3的源极端子ST2、栅极端子GT2，用于各功率MOSFET的导通/截止的控制。再有，由于在朝向下方的主面3a上形成了栅极端子GT2，故如图9中所示，利用引线10经金属板26连接了驱动器IC芯片4的多个端子9的一部分与同步用功率MOSFET芯片3的栅极端子GT2。例如经突点电极等电连接了栅极端子GT2与金属板26。其它的端子分别是电源电压端子、引导端子、电压确认用端子和控制信号输入端子等，利用引线10和与其对应的外部连接端子11进行了连接。
此外，输入侧板状引线部5、输出侧板状引线部6、接地侧板状引线部7和驱动器侧板状引线部8如图11中所示，在封装体17的背面17b上分别露出各自的一部分或全部，不仅作为与印刷安装基板电连接用的外部连接用的端子部，而且也起到对印刷安装基板排出热的散热部件的作用。
但是，不一定需要露出全部的板状引线部，例如也可以是只露出输出侧板状引线部6的结构。
此外，源极用板状引线部12电连接了控制用功率MOSFET芯片2的源极端子ST1与同步用功率MOSFET芯片3的漏极端子DT2。再者，如图12中所示，该源极用板状引线部，12的一部分在封装体17的表面17a上露出。
因而，在本实施例2的MCM1中，如图9中所示，用封装体17的表面17a连接了作为第2板状导体构件的源极用板状引线部12中的与控制用功率MOSFET芯片2(一个半导体芯片)的连接部位和与同步用功率MOSFET芯片3(另一个半导体芯片)的连接部位。
再有，在控制用功率MOSFET芯片2中，将形成了其漏极端子DT1的面例如经银膏14等的管芯键合材料压接到输入侧板状引线部5上，其相反一侧的面的源极端子ST1例如经金突点15等的导电性材料连接到源极用板状引线部12上。
另一方面，在同步用功率MOSFET芯片3中，将形成了其漏极端子DT2的面例如经银膏14等的管芯键合材料压接到源极用板状引线部12上，其相反一侧的面的源极端子ST2例如经金突点15等的导电性材料连接到接地侧板状引线部7上。
在本实施例2的MCM1中，通过在表面背面相反的方向上安装至少1个半导体芯片，与实施例1的MCM1相比，可使源极用板状引线部12的加工变得容易。即，如图10中所示，由于只使用平板状的1片源极用板状引线部12能在源极用板状引线部12的同一面上连接控制用功率MOSFET芯片2的源极端子ST1与同步用功率MOSFET芯片3的漏极端子DT2，故可避免因在源极用板状引线部12的不同的面上连接多个半导体芯片导致的加工的麻烦，因而，可减少在引线部间的连接或加工中需要的工夫。
由此，可简化MCM1的结构。
此外，与实施例1的MCM1相比，由于能以1片的平板状形成源极用板状引线部12，故可进一步增加源极用板状引线部12的面积，可进一步提高散热效果，同时可进一步提高电压变换效率。
(实施例3)
图13是示出本发明的实施例3的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的剖面图，图14是示出本发明的实施例3的变形例的半导体器件的结构的剖面图。
本实施例3的半导体器件与实施例1、2同样，是非绝缘型DC/DC变换器用的MCM(多芯片组件)1，进而说明提高散热性的结构。
图13中示出的MCM1在实施例1中已说明的MCM1上安装了作为散热构件的散热片27。即，由于实施例1的MCM1的在封装体17的表面17a上露出的2个板状引线部(源极用板状引线部12、13)具有不同的电位，故经绝缘片28安装了散热片27等的散热构件。
这样，通过在MCM1的表面17a中在其上露出的板状引线部上安装散热片27，可进一步提高MCM1的散热性。
此外，图14中示出的MCM1在实施例2的MCM1上安装了作为散热构件的散热片27。在该MCM1中，在封装体17的表面17a上露出的板状引线部只是源极用板状引线部12这1个。因而，可不介入绝缘片28等直接连接源极用板状引线部12与散热片27，与图13中示出的MCM1相比，可进一步提高散热性。
此外，也可使源极用板状引线部12与散热片27实现一体化，此时，可得到更高的散热效果。
(实施例4)
图15是透过封装体示出本发明的实施例4的半导体器件(非绝缘型DC/DC变换器用多芯片组件)的结构的一例的平面图。
本实施例4的半导体器件与实施例1、2同样，是非绝缘型DC/DC变换器用的MCM(多芯片组件)1，但实施例1和实施例2的MCM1在控制用功率MOSFET芯片2的源极端子ST1、栅极端子GT1与驱动器IC芯片4的端子9的连接中，或在同步用功率MOSFET芯片3的源极端子ST2、栅极端子GT2与驱动器IC芯片4的端子9的连接中，分别使用了引线10，本实施例4的MCM1在这些栅极驱动器电路或其它的连接中使用了金属板(另一板状导体构件)29。
即，在图15中示出的一例中，分别利用金属板29电连接了控制用功率MOSFET芯片2的端子部和与其对应的驱动器IC芯片4的端子9，而且电连接了同步用功率MOSFET芯片3的端子部和与其对应的驱动器IC芯片4的端子9。再者，例如使用金突点15等来进行各端子与金属板29的电连接。
在MCM1中，由于在高速开关时栅极驱动器电路等主电流路径以外的寄生电阻、寄生电感有时成为效率下降的原因，故通过用金属板29以这种方式连接驱动器IC芯片4与控制用功率MOSFET芯片2或同步用功率MOSFET芯片3的电极间，与引线连接相比，可减少寄生电阻、寄生电感。
再有，同样，对于图15中示出的其它的引线10，也可置换为金属板29。
以上，根据发明的实施例具体地说明了由本发明者进行的发明，但本发明不限定于上述发明的实施例，在不脱离其要旨的范围内，当然可作各种变更。
例如，在上述实施例1～4中，作为MCM1的结构，举出QFN型的半导体器件的情况进行了说明，但MCM1不限于QFN型，只要是在封装体中封入了多个半导体芯片的结构，也可以是QFP(方形平面封装)型等其它的结构的半导体器件。再者，被封入的半导体芯片的数目也不限定于3个，可以大于等于4个。
本发明适合用于半导体器件和电子设备。

Claims (24)

1.一种半导体器件，其特征在于：
具备分别具有输入电极、第1输出电极和第2输出电极的第1晶体管和第2晶体管，
串联地连接上述第1晶体管的上述第1输出电极和上述第2输出电极的电流路径与上述第2晶体管的上述第1输出电极和上述第2输出电极的电流路径，
将上述第1晶体管的上述第1输出电极和上述第2输出电极的一方连接到第1导体构件上，
将上述第1晶体管的上述第1输出电极和上述第2输出电极的另一方连接到第2导体构件上，
将上述第2晶体管的上述第1输出电极和上述第2输出电极的另一方连接到上述第2导体构件上，
将上述第2晶体管的另一方连接到第3导体构件上，
对上述第1导体构件、上述第2导体构件、上述第3导体构件进行电隔离，
以机械的方式使上述第1导体构件、上述第2导体构件、上述第3导体构件、上述第1晶体管、上述第2晶体管实现一体化。
2.如权利要求1中所述的半导体器件，其特征在于：
上述第2导体构件具有大于等于2个部位的弯曲部。
3.如权利要求1中所述的半导体器件，其特征在于：
上述第2导体构件呈大致S字形状。
4.如权利要求1中所述的半导体器件，其特征在于：
在上述第2导体构件中连接了上述第1晶体管的输出电极的面与连接了上述第2晶体管的面处于相同的一侧。
5.一种半导体器件，其特征在于具有：
在各自的主面上形成了端子的多个半导体芯片；
与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；
对上述多个半导体芯片进行封装的封装体；以及
分别与上述多个半导体芯片电连接的多个外部连接端子，
由上述板状导体构件进行了连接的上述至少2个半导体芯片分别具有晶体管电路，上述板状导体构件从上述封装体露出。
6.如权利要求5中所述的半导体器件，其特征在于：
上述多个半导体芯片中的第1半导体芯片和第2半导体芯片分别具有电源用晶体管电路，
还具有：
连接到上述第1半导体芯片的漏极端子上的第1板状导体构件；
连接到上述第1半导体芯片的源极端子上的第2板状导体构件；
连接到上述第2半导体芯片的漏极端子上的第3板状导体构件；以及
连接到上述第2半导体芯片的源极端子上的第4板状导体构件，
上述第2板状导体构件与上述第3板状导体构件电连接，上述第2和第3板状导体构件各自的至少一部分从上述封装体露出。
7.如权利要求6中所述的半导体器件，其特征在于：
上述第2板状导体构件和上述第3板状导体构件一体地形成。
8.如权利要求5中所述的半导体器件，其特征在于：
上述多个半导体芯片中的第1半导体芯片和第2半导体芯片分别具有电源用晶体管电路，第3半导体芯片具有控制上述第1和第2半导体芯片的驱动器电路。
9.如权利要求6中所述的半导体器件，其特征在于：
上述第2和第4板状导体构件各自的一部分在上述封装体的表面背面的某一方露出，上述第1和第3板状导体构件各自的一部分在上述封装体的表面背面的另一方露出。
10.如权利要求9中所述的半导体器件，其特征在于：
上述第2板状导体构件和上述第3板状导体构件一体地形成。
11.如权利要求5中所述的半导体器件，其特征在于：
上述多个半导体芯片中的至少1个半导体芯片以与其它的半导体芯片表面背面相反的方向进行安装。
12.如权利要求6中所述的半导体器件，其特征在于：
上述第2半导体芯片以与上述第1半导体芯片表面背面相反的方向进行安装，上述第2和第3板状导体构件各自的一部分在上述封装体的表面背面的某一方露出，上述第1和第4板状导体构件各自的一部分在上述封装体的表面背面的另一方露出。
13.如权利要求12中所述的半导体器件，其特征在于：
上述第2板状导体构件和上述第3板状导体构件一体地形成。
14.如权利要求5中所述的半导体器件，其特征在于：
在上述板状导体构件的从上述封装体露出的部位上安装有散热构件。
15.一种半导体器件，其特征在于具有：
在各自的主面上形成了端子的多个半导体芯片；
与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；
对上述多个半导体芯片进行树脂封装的封装体；以及
分别与上述多个半导体芯片电连接的多个外部连接端子，
上述板状导体构件从上述封装体露出，上述板状导体构件中的与一个半导体芯片的连接部位和与另一个半导体芯片的连接部位，在上述封装体的表面背面中的某一方或上述封装体内部的各半导体芯片的外侧进行了连接。
16.如权利要求15中所述的半导体器件，其特征在于：
上述多个半导体芯片中的第1半导体芯片和第2半导体芯片分别具有电源用晶体管电路，第3半导体芯片具有控制上述第1和第2半导体芯片的驱动器电路。
17.如权利要求15中所述的半导体器件，其特征在于：
在上述板状导体构件的从上述封装体露出的部位上安装有散热构件。
18.如权利要求15中所述的半导体器件，其特征在于：
上述板状导体构件和与其电连接的半导体芯片经多个金突点进行电连接。
19.如权利要求16中所述的半导体器件，其特征在于：
上述第1半导体芯片的端子与上述第3半导体芯片的端子由上述板状导体构件电连接，同时上述第2半导体芯片的端子与上述第3半导体芯片的端子由另一板状导体构件电连接。
20.一种半导体器件，其特征在于具有：
在各自的主面上形成了端子的多个半导体芯片；
与上述多个半导体芯片中的至少2个半导体芯片的端子电连接的板状导体构件；
对上述多个半导体芯片进行树脂封装的封装体；以及
分别与上述多个半导体芯片电连接并配置在上述封装体的背面的周围边缘部上多个外部连接端子，
上述板状导体构件从上述封装体的表面背面中的至少某一方露出。
21.如权利要求20中所述的半导体器件，其特征在于：
上述多个半导体芯片中的第1半导体芯片和第2半导体芯片分别具有电源用晶体管电路，第3半导体芯片具有控制上述第1和第2半导体芯片的驱动器电路。
22.如权利要求20中所述的半导体器件，其特征在于：
在上述板状导体构件的从上述封装体露出的部位上安装有散热构件。
23.如权利要求20中所述的半导体器件，其特征在于：
上述板状导体构件和与其电连接的半导体芯片经多个金突点进行电连接。
24.如权利要求20中所述的半导体器件，其特征在于：
上述多个半导体芯片中的第1半导体芯片和第2半导体芯片分别具有电源用晶体管电路，同时上述第2半导体芯片以与上述第1半导体芯片表面背面相反的方向进行安装，
还具有：
连接到上述第1半导体芯片的漏极端子上的第1板状导体构件；
连接到上述第1半导体芯片的源极端子上的第2板状导体构件；
连接到上述第2半导体芯片的漏极端子上的第3板状导体构件；以及
连接到上述第2半导体芯片的源极端子上的第4板状导体构件，
上述第2和第3板状导体构件各自的一部分在上述封装体的表面背面的某一方露出，上述第1和第4板状导体构件各自的一部分在上述封装体的表面背面的某另一方露出。
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