CN103367338A - 芯片装置和形成其的方法、芯片封装和形成其的方法 - Google Patents

芯片装置和形成其的方法、芯片封装和形成其的方法 Download PDF

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Publication number
CN103367338A
CN103367338A CN201310101194XA CN201310101194A CN103367338A CN 103367338 A CN103367338 A CN 103367338A CN 201310101194X A CN201310101194X A CN 201310101194XA CN 201310101194 A CN201310101194 A CN 201310101194A CN 103367338 A CN103367338 A CN 103367338A
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chip
carrier
electrically connected
chip carrier
insulating material
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CN103367338B (zh
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J.马勒
A.普吕克尔
R.沃姆巴歇尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及芯片装置和形成其的方法、芯片封装和形成其的方法。提供了一种芯片装置，该芯片装置包括：第一芯片载体；第二芯片载体；第一芯片，其电连接到第一芯片载体；第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及第三芯片，其电连接到第二芯片载体；其中第一芯片和第二芯片至少其一电连接到第三芯片。

Description

芯片装置和形成其的方法、芯片封装和形成其的方法
技术领域
各种实施例总体上涉及芯片装置、用于形成芯片装置的方法、芯片封装以及用于形成芯片封装的方法。
背景技术
当电路中芯片数目大时，构造例如芯片壳体的芯片封装会是挑战性的。例如，如果超过一个功率半导体芯片或者一个或多个逻辑集成电路芯片将被封装成为单个器件，芯片壳体可以被提供用于一个或多个半导体芯片的封装。传统上，芯片上芯片构造可以用于形成多芯片壳体。例如，逻辑集成电路芯片的背侧可以胶粘到在功率半导体芯片的一侧上方的电绝缘介质。因此，逻辑集成电路芯片可以附着到共用的管芯垫上方的功率半导体芯片。逻辑集成电路芯片可以与管芯垫和功率半导体芯片电绝缘。然而，当超过一个功率半导体芯片以及一个或多个逻辑集成芯片将构造于壳体中时，每个芯片可以单独地封装在分离的壳体中，并且随后在单个引线框上方彼此电连接。另一选择是昂贵双铜接合基壳体，其中多个具有垂直电流的功率半导体芯片每个可以分开地接合到陶瓷上的分离金属层(例如铜层)。逻辑集成电路芯片可以或者固定到陶瓷侧的另一侧，或者固定到该分离金属层但与其电隔离。
发明内容
各种实施例提供一种芯片装置，其包括：第一芯片载体；第二芯片载体；第一芯片，其电连接到第一芯片载体；第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及第三芯片，其电连接到第二芯片载体；其中第一芯片和第二芯片至少其一电连接到第三芯片。
附图说明
在各图中，相似的附图标记通常在不同视图中始终指代相同的部分。图不一定是按比例的，通常反而将重点放在说明本发明的原理上。在下述描述中，参考下述各图描述本发明的各种实施例，在图中：
图1示出根据实施例的芯片装置；
图2示出根据实施例的用于形成芯片装置的方法；
图3A至3D示出根据实施例的用于形成芯片装置的方法；
图4A和4B示出根据实施例的用于形成芯片装置的方法；
图5示出根据实施例的芯片装置；
图6示出根据实施例的芯片装置；
图7示出根据实施例的芯片装置；
图8示出根据实施例的芯片封装；
图9示出根据实施例的用于形成芯片封装的方法；
图10示出根据实施例的芯片装置。
具体实施方式
下述详细描述参考了附图，所述附图通过图示方式示出了可以在其中实践本发明的特定细节和实施例。
词语"示例性"在此处用于表示"用作示例、例子或例证"。此处描述为"示例性"的任何实施例或设计不一定解读为相较其它实施例或设计是优选或有利的。
关于在侧或表面"上方"形成的沉积材料所使用的词语"上方"在此处可以用于表示所沉积的材料可以"直接"形成于所默示的侧或表面上，例如与其直接接触。关于在侧或表面"上方"形成的沉积材料所使用的词语"上方"在此处可以用于表示所沉积的材料可以"间接"形成于所默示的侧或表面上，一个或多个附加层布置在默示的侧或表面与所沉积的材料之间。
各种实施例提供一种用于多个半导体芯片的壳体，其中多个具有垂直电流流动的功率半导体芯片以及集成电路逻辑芯片可以收纳在壳体内的单个载体上方。
各种实施例提供一种用于多个芯片的壳体，其中壳体可包括多个管芯垫，所述多个管芯垫可以通过电绝缘封装模具而彼此电绝缘。
图1示出根据实施例的芯片装置102。
芯片装置102可包括第一芯片载体104和第二芯片载体106。芯片装置102可包括电连接到第一芯片载体104的第一芯片108，例如半导体芯片，诸如半导体管芯。芯片装置102可包括布置在第一芯片载体104上方并且与第一芯片载体104电绝缘的第二芯片112，例如半导体芯片，诸如半导体管芯；以及电连接到第二芯片载体106的第三芯片114，例如半导体芯片，诸如半导体管芯；其中第一芯片108和第二芯片112至少其一电连接到第三芯片114。
图2示出根据实施例的用于形成芯片装置的方法200。方法200可包括：
将第一芯片电连接到第一芯片载体(在210)；
将第二芯片布置在第一芯片载体上方并且将第二芯片与第一芯片载体电绝缘(在220)；
将第三芯片电连接到第二芯片载体(在230)；以及
将第一芯片和第二芯片至少其一电连接到第三芯片(在240)。
图3A至3D示出根据实施例的用于形成芯片装置的方法。
在310，一个或多个功率器件可以导电接合在一个或多个金属芯片-载体上。第一芯片108可以电连接到第一芯片载体104。第三芯片114可以电连接到第二芯片载体106。
第一芯片载体104和第二芯片载体106可以分开一定距离，换言之，它们可以分离一分隔距离ds。分隔距离ds的范围可以为约10μm至约10mm，例如约50μm至约5mm，例如约100μm至约1mm。
第一芯片载体104可包括第一引线框载体，并且第二芯片载体106可包括第二引线框载体。第一芯片载体104可包括第一管芯垫，并且第二芯片载体106可包括第二管芯垫。
第一芯片载体104可以具有范围为约50μm至约1500μm，例如约100μm至约500μm，例如约150μm至约300μm的厚度t1。
第二芯片载体106可以具有范围为约50μm至约1500μm，例如约100μm至约500μm，例如约150μm至约300μm的厚度t2。
一个器件的整个引线框可以具有约1mm至50mm，例如约2mm至约20mm的长度LP，并且可以具有约1mm至50mm，例如约2mm至约20mm的宽度。
第一芯片载体104和第二芯片载体106至少其一可包括下述材料群组中的至少一种，该材料群组由下述构成：铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
第一芯片载体104和第二芯片载体106至少其一可包括下述材料群组中的至少一种，该材料群组由下述构成：NiPdAu、NiAu、NiPd、NiAuAg、NiPdAuAg、NiNiPPdAu、NiNiPAu、NiNiPPd、NiNiPAuAg、NiNiPPdAuAg。
第一芯片载体104和第二芯片载体106至少其一可包括这样的材料，其包括范围在约1nm至1000nm的粗糙度。
第一芯片载体104和第二芯片载体106至少其一可包括这样的材料，其具有范围在约2%至50%的孔隙度。
第一芯片108和第三芯片114至少其一可包括功率半导体芯片，其中该功率半导体芯片可包括来自由下述构成的群组的至少一种功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅极双极晶体管、晶闸管、MOS受控晶闸管、硅受控整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
根据实施例，第一芯片108可包括功率半导体芯片。图3B示出第一芯片108和第三芯片114每个可以包括功率晶体管。然而可以理解，第一芯片108和/或第三芯片114可包括功率晶体管。第三芯片114或者可包括功率半导体芯片或者可包括逻辑集成电路芯片。
第一芯片108和第三芯片114至少其一可包括功率半导体器件，其中功率半导体器件会能够承载高达大约600V的电压。
第一芯片108可包括顶侧316和底侧318，其中顶侧316可以面向与底侧318面向的方向相反的方向。
第一芯片108可包括在顶侧316上方形成的，例如直接或间接在顶侧316上形成的栅极区域接触322以及至少一个第一源极/漏极区域接触324，并且包括在底侧318上方形成的至少一个第二源极/漏极区域接触326。每个接触可包括导电接触垫。每个接触可以在第一芯片108的顶侧316上方彼此电隔离。例如，栅极区域接触322可以通过在顶侧316上方形成的、例如二氧化硅的电绝缘材料与至少一个第一源极/漏极区域接触324电隔离。封装材料，例如下文所述的电绝缘材料368，也可以用于将栅极区域接触322与至少一个第一源极/漏极区域接触324电隔离。
顶侧也可以称为芯片的“第一侧”、“前侧”或“上侧”。术语“顶侧”、“第一侧”、“前侧”或“上侧”在下文中可以可互换地使用。底侧也可以称为芯片的“第二侧”或“背侧”。术语“第二侧”、“背侧”或“底侧”在下文中可以可互换地使用。如此处关于半导体功率器件所使用，术语“顶侧”、“第一侧”、“前侧”或“上侧”可以理解为是指栅极区域以及至少一个第一源极/漏极区域可以在那里形成的芯片的那侧。术语“第二侧”、“背侧”或“底侧”可以理解为是指第二源极/漏极区域可以在那里形成的芯片的那侧。因此，半导体功率晶体管可以支持垂直电流流动穿过位于顶侧316上方的第一源极/漏极区域和底侧318上方的第二源极/漏极区域之间的芯片。
类似地，第三芯片114可包括半导体功率晶体管，其包括顶侧328和底侧332。类似地，第三芯片114可包括在顶侧328上方形成的栅极区域接触334和至少一个第一源极/漏极区域接触336，并且包括在底侧332上方形成的至少一个第二源极/漏极区域接触338。第一芯片108可以配置成承载第一芯片顶侧316和第一芯片底侧318之间的垂直电流流动。第三芯片114可以配置成承载第三芯片顶侧328和第三芯片底侧332之间的垂直电流流动。栅极区域接触334可以通过在顶侧328上方形成的、例如二氧化硅的电绝缘材料与至少一个第一源极/漏极区域接触336电隔离。封装材料，例如下文所述的电绝缘材料368，也可以用于将栅极区域接触334与至少一个第一源极/漏极区域接触336电隔离。
第一芯片108可以布置在第一芯片载体104上方，并且经由至少一个接触垫，例如形成于第一芯片背侧318上方的第二源极/漏极区域接触326，第一芯片108可以电连接到第一芯片载体104。
类似地，第三芯片114可以布置在第二芯片载体106上，并且经由至少一个接触垫，例如形成于第三芯片背侧332上方的第二源极/漏极区域接触338，第三芯片114可以电连接到第二芯片载体106。
第一芯片108可以经由导电介质342电连接到第一芯片载体104。
第三芯片114可以经由导电介质344电连接到第二芯片载体106。
导电介质342和导电介质344每个可以包括下述材料群组中的至少一种，该群组由下述构成：焊料、软焊料、扩散焊料、膏料、纳米膏料、粘合剂、导电粘合剂。导电介质342和导电介质344每个可以包括下述元素群组的至少一种，该元素群组由下述构成：Ag、Zn、Sn、Pb、Bi、In、Cu、Au、Pd。
导电介质342和导电介质344可包括相同或不同材料。
在320，一个或多个电绝缘集成电路芯片每个可以电绝缘接合在第一芯片载体104和第二芯片载体106至少其一上。第二芯片112可以布置在第一芯片载体104上方。第二芯片112可以与第一芯片载体104电绝缘。
第二芯片112可包括顶侧346和底侧348。第二芯片底侧348，即背侧，可以布置在第一芯片载体104上方。第二芯片112可包括半导体逻辑芯片，其中该半导体逻辑芯片可包括来自由下述构成的群组的至少一种半导体逻辑器件：专用集成芯片ASIC、驱动器、控制器、传感器。可以理解，半导体逻辑芯片，即逻辑集成电路芯片，可包括低功率半导体器件，例如能够承载高达100V至150V的器件。
如此处关于较低功率半导体逻辑器件所使用的，第二芯片顶侧346可以理解为是指承载一个或多个接触垫或者电接触的芯片的那侧，接合垫或电连接可以附着在其中；或者其中它是可以大部分被金属化层覆盖的芯片的那侧。第二芯片底侧348可以理解为是指可以没有金属化或接触垫或电接触的芯片的那侧。第二芯片底侧348可以通过电绝缘介质352附连到第二芯片载体104。因此，第二芯片112可以通过电绝缘介质352与第一芯片载体104电绝缘。电绝缘介质352可包括下述材料群组中的至少一种，该群组由下述构成：粘合剂、电绝缘粘合剂、环氧树脂、胶、膏料、粘合剂箔、电绝缘晶片背侧涂层。
可以理解，尽管根据各种实施例，在第二芯片112安置在第一芯片载体104上方之前，第一芯片108安置在第一芯片载体104上方，但是第二芯片112也可以在第一芯片108安置在第一芯片载体104上方之前安置在第一芯片载体104上方。
第一芯片108、第二芯片112和第三芯片114每个可以包括半导体芯片，例如管芯，该半导体芯片包括晶片衬底。半导体芯片可包括在晶片衬底上方形成的一个或多个电子部件。晶片衬底可包括各种材料，例如半导体材料。晶片衬底可包括下述材料群组中的至少一种，该材料群组由下述构成：硅、锗、III-V族材料、聚合物。根据实施例，晶片衬底可包括掺杂或未掺杂硅。根据另一实施例，晶片衬底可包括绝缘体上硅SOI晶片。根据实施例，晶片衬底可包括半导体化合物材料，例如砷化镓(GaAs)、磷化铟(InP)。根据实施例，晶片衬底可包括四元半导体化合物材料，例如铟镓砷(InGaAs)。
第一芯片108、第二芯片112和第三芯片114至少其一可以具有范围约5μm至约500μm，例如约10μm至约350μm，例如约50μm至约250μm的厚度(底侧至顶侧)。
第一芯片108、第二芯片112和第三芯片114至少其一可以具有范围约100μm至10mm，例如约200μm至8mm，例如约500μm至约5mm的长度。
第一芯片108、第二芯片112和第三芯片114至少其一可以具有范围约100μm至10mm，例如约200μm至8mm，例如约500μm至约5mm的宽度。
在330，第一芯片108和第二芯片112至少其一可以电连接到第三芯片114。一个或多个电互连3541、3542可以一起被沉积，例如通过电流沉积。将第一芯片108和第二芯片112至少其一电连接到第三芯片114可包括形成电互连3541，用于将第一芯片108和第二芯片112至少其一电连接到第三芯片114。一个或多个电互连3541、3542可包括来自下述材料群组的至少一种材料、元素或合金，该群组由下述构成：铜、铝、银、锡、金、钯、锌、镍、铁。
一个或多个电互连3541、3542可以被沉积，并且一个或多个电互连3541可以配置成将第一芯片108和第二芯片112至少其一电连接到第三芯片114。第一芯片108和第二芯片112至少其一可以电连接到第三芯片顶侧328或第三芯片底侧332至少其一。
在图3C中，电互连3541可以形成，使得它将第一芯片108电连接到第三芯片114，例如使得它将第一芯片顶侧316电连接到第三芯片顶侧328。电互连3541可以形成，使得它将在第一芯片前侧316上方形成的一个或多个接触垫322、324电连接到在第三芯片前侧328上方形成的一个或多个接触垫334、336。例如，电互连3541可以形成，使得它将第一芯片第一源极/漏极接触324电连接到第三芯片第一源极/漏极接触336。一个或多个接触垫322、324可包括来自下述材料群组的至少一种材料、元素或合金，该群组由下述构成：铜、铝、银、锡、金、钯、锌、镍、铁。
第二电互连3542可以例如通过电流沉积形成，使得它将在第一芯片前侧316上方形成的一个或多个接触垫322、324电连接到一个或多个接触356，例如在第二芯片前侧346上方形成的接触垫。例如，第二电互连3542可以形成，使得它将第一芯片栅极接触322电连接到在第二芯片前侧346上方形成的一个或多个接触356。每个接触322、324可以在第一芯片前侧316上方彼此电隔离。例如，电接触322可以通过在第一芯片前侧316上方形成的、例如二氧化硅的电绝缘材料与电接触324电隔离。封装材料，例如下文所述的电绝缘材料368，也可以用于将电接触322与电接触324电隔离。
一个或多个电互连3541、3542可包括来自下述电互连的群组的至少一种，该群组由下述构成：导线、导电导线、接合导线、夹具、导电夹具、电流沉积互连。借助导电粘合剂，例如焊料、例如软焊料、例如扩散焊料、例如膏料、例如导电胶，导线形式的一个或多个电互连3541、3542可以附连到芯片接触，例如接触垫。
在340，电绝缘材料368可以被沉积。电绝缘材料368可以被沉积，使得电绝缘材料368可以至少部分围绕第一芯片108、第二芯片112和第三芯片114。电绝缘材料368可以沉积在第一芯片108和第二芯片112之间。电绝缘材料368可以沉积在第二芯片112和第三芯片114之间。电绝缘材料368可以沉积在第一芯片载体104和第二芯片载体106之间。电绝缘材料368可以被沉积，使得电绝缘材料368可以至少部分围绕第一芯片108、第二芯片112和第三芯片114。电绝缘材料368可以被沉积，使得电绝缘材料368可以至少部分围绕第一芯片载体104和第二芯片载体106。电绝缘材料368可以被沉积，使得电绝缘材料368可以至少部分围绕一个或多个电互连3541、3542，其中一个或多个电互连3541、3542可以配置成将第一芯片108和第二芯片112至少其一电连接到第三芯片114。电绝缘材料368可以被沉积，其中除了将第一芯片第一源极/漏极接触324电连接到第三芯片第一源极/漏极接触336的电互连3541之外，第一芯片108可以与第三芯片114电绝缘。
电绝缘材料368可包括下述材料群组中的至少一种，该群组由下述构成：填充或未填充的环氧树脂、预浸渍复合纤维、强化纤维、层压板、模具材料、热固性材料、热塑性材料、填料颗粒、纤维强化层压板、纤维强化聚合物层压板、具有填料颗粒的纤维强化聚合物层压板。
电绝缘材料368可以具有范围约5μm至约500μm，例如约10μm至约300μm，例如约20μm至约150μm的厚度tE。
第一芯片108和第二芯片106可以电连接到第一芯片载体104，即在第一芯片载体104的顶侧358上方。第一芯片108和第二芯片106可以电连接到第一芯片载体104，在第一芯片载体104的同侧上方。第一芯片载体104可包括与第一芯片载体顶侧358相对的第一芯片载体底侧362。第三芯片114可以电连接到第二芯片载体顶侧364。第二芯片载体106可包括与第二芯片载体顶侧364相对的第二芯片载体底侧366。
第一芯片载体104和第二芯片载体106可以布置成基本上彼此齐平，其中第一芯片108、第二芯片112和第三芯片114可以基本上彼此齐平。
电绝缘材料368可以被沉积，使得电绝缘材料368可以从第一芯片载体顶侧358和第二芯片载体顶侧364至少部分围绕第一芯片108、第二芯片112和第三芯片114、一个或多个电互连3541、3542、第一芯片载体104和第二芯片载体106。电绝缘材料368可以被沉积，使得电绝缘材料可以将第一芯片载体104保持到第二芯片载体106，同时将第一芯片载体104和第二芯片载体106分隔一分隔距离ds，并且将第一芯片载体104与第二芯片载体106电隔离。
电绝缘材料368可以被沉积，使得电绝缘材料368可以至少部分限定芯片封装302的一个或多个侧，例如露出的面向外部的表面。换言之，电绝缘材料368可包括形成芯片封装的外表面的至少一侧。
第一芯片108、第二芯片108和第三芯片112可以形成半桥电路的部分，其中第二芯片可包括用于半桥电路的集成驱动器电路。
芯片装置302，例如芯片封装302可以具有范围约1mm至约50mm，例如约2mm至约20mm，例如约3mm至约10mm的长度LP。芯片装置302，例如芯片封装302可以具有范围约1mm至约50mm，例如约2mm至约20mm，例如约3mm至约10mm的宽度(未示出)。
图4A和4B示出根据实施例的用于形成芯片装置的方法。方法400可包括关于方法200和方法300至少其一已经描述的过程的一个或多个或全部。方法400可包括关于过程310、320、330和340描述的特征的一个或多个或全部。
根据实施例，方法400可包括过程310、320、330和340。此外，在410，方法400可包括沉积一个或多个另外电互连3543、3544，例如通过修改过程330，其中一个或多个另外电互连3543、3544可以配置成将第一芯片108和第二芯片112至少其一电连接到一个或多个另外芯片载体372、374。例如，电互连3543可以被沉积，其中电互连3543可以将第三芯片114电连接到第三芯片载体372。电互连3543可以被沉积，其中电互连3543将第三芯片顶侧328电连接到第三芯片载体372。电互连3543可以被沉积，其中电互连3543将第三芯片栅极接触334或第三芯片顶侧328上方的任何其它接触电连接到第三芯片载体372。一个或多个电互连3543、3544可包括来自下述材料群组的至少一种材料、元素或合金，该群组由下述构成：铜、铝、银、锡、金、钯、锌、镍、铁。
此外，电互连3544可以被沉积，其中电互连3544将第二芯片112电连接到第四芯片载体374。电互连3544可以被沉积，其中电互连3544将第二芯片顶侧346电连接到第四芯片载体374。电互连3544可以被沉积，其中电互连3544将第二芯片顶侧346上方的一个或多个接触376电连接到第四芯片载体374。根据实施例，一个或多个接触356可包括第二芯片第一源极/漏极接触，并且一个或多个接触376可包括第二芯片第二源极/漏极接触。
根据实施例，下文另外详述的一个或多个另外芯片可以附着到第三芯片载体372和/或第四芯片载体374，其中一个或多个另外芯片可包括第一芯片108或第二芯片112或第三芯片114的特征的一个或多个或全部。
在420，电绝缘材料468可以被沉积，使得电绝缘材料468可以至少部分围绕第一芯片108、第二芯片112和第三芯片114。电绝缘材料468可以被沉积，使得电绝缘材料468可以至少部分围绕第一芯片载体104、第二芯片载体106以及一个或多个另外芯片载体372、374。电绝缘材料468可以沉积在第一芯片108和第二芯片112之间。电绝缘材料468可以沉积在第二芯片112和第三芯片114之间。电绝缘材料468可以沉积在第一芯片108和第三芯片114之间。电绝缘材料468可以沉积在第一芯片载体104和第二芯片载体106之间。电绝缘材料468可以沉积在第二芯片载体106和第三芯片载体372之间。电绝缘材料468可以沉积在第一芯片载体104和第四芯片载体374之间。电绝缘材料468可以被沉积，使得电绝缘材料468可以至少部分围绕一个或多个电互连3541、3542以及一个或多个另外电互连3543、3544。电绝缘材料368可以被沉积，其中除了将第一芯片栅极接触322电连接到第二芯片第一源极/漏极接触356的电互连3542之外，第一芯片108可以与第二芯片112电绝缘。
电绝缘材料468可包括关于电绝缘材料368所描述的特征的基本功能。电绝缘材料468可以被沉积，使得电绝缘材料468可以例如从第一芯片载体顶侧358，第二芯片载体顶侧364和/或一个或多个另外芯片载体372、374的一个或多个顶侧378、382，至少部分围绕第一芯片108、第二芯片112和第三芯片114，一个或多个电互连3541、3542，和/或一个或多个另外电互连3543、3544，第一芯片载体104和第二芯片载体106，和/或一个或多个另外芯片载体372、374。电绝缘材料468可以被沉积，使得电绝缘材料可以将第一芯片载体104、第二芯片载体106、第三芯片载体372和第四芯片载体374保持在一起，而将第一芯片载体104、第二芯片载体106、第三载体372和第四芯片载体374每个彼此分离和电隔离。电绝缘材料468可以被沉积，使得电绝缘材料468可以至少部分限定芯片封装402的一个或多个侧，例如露出的面向外部的表面。
图5示出根据实施例的芯片装置502。根据各种实施例，电绝缘材料368、468，可以从第一芯片载体顶侧358、第二芯片载体顶侧364以及一个或多个另外芯片载体372、374的一个或多个顶侧378、382被沉积；由此露出第一芯片载体底侧362、第二芯片载体底侧384以及一个或多个另外芯片载体372、374的一个或多个底侧384、386(见图4C)。
在510，方法300和/或方法400可以进一步包括沉积电绝缘材料368、468，其中电绝缘材料368、468至少部分围绕第一芯片载体底侧362和第二芯片载体底侧366，如所示。电绝缘材料368、468可以被沉积，其中电绝缘材料368、468至少部分围绕第三芯片载体底侧384和第四芯片载体底侧386。根据实施例，电绝缘材料368、468可以可选地选择性沉积，其中一个或多个电互连3541、3542、3543、3544的至少一个表面可以从电绝缘材料368、468释放。例如，一个或多个电互连3541、3542、3543、3544的至少一个表面可以不被电绝缘材料368、468覆盖，并且因此露出。
根据实施例，电绝缘材料468可以被沉积，其中第一芯片载体104、第二芯片载体106、第三芯片载体372、第四芯片载体374、第一芯片108、第二芯片112、第三芯片114以及一个或多个电互连3541、3542、3543、3544完全嵌入电绝缘材料468。
图6示出根据实施例的芯片装置602。
可以理解，根据各种实施例的芯片装置，例如芯片封装，可以不限于包括一个、两个、三个或四个芯片载体。
芯片装置602可包括芯片装置102、302、402和502至少其一的一个或多个或全部特征的基本功能性。此外，芯片装置602可包括第二芯片载体106，其中按照与将第二芯片112布置在第一芯片载体104上方相似的过程，第四芯片688可以布置在第二芯片载体顶侧364上方。第四芯片688可包括半导体逻辑集成电路芯片，如此处已经关于第二芯片112所述。
芯片装置602可以进一步包括第三芯片载体372，其中一个或多个芯片可以形成于第三芯片载体372上方。在图6中，按照与将第一芯片108电连接到第一芯片载体104以及将第三芯片112电连接到第二芯片载体106相似的过程，第五芯片692可以电连接到第三芯片载体372。第五芯片692可包括功率半导体芯片，如此处已经关于第一芯片108或第三芯片112所述。
电互连3545可以例如通过电流沉积形成，使得它将在第三芯片前侧328上方形成的一个或多个接触334电连接到第四芯片688。例如，电互连3545可以形成，使得它将在第三芯片前侧328上方形成的第三芯片栅极接触334电连接到在第四芯片前侧696上方形成的一个或多个接触694，例如接触垫。
电互连3546可以例如通过电流沉积形成，使得它将在第四芯片前侧696上方形成的一个或多个另外接触698电连接到第五芯片692。例如，电互连3546可以形成，使得它将在第四芯片前侧696上方形成的另外接触698电连接到在第五芯片前侧6104上方形成的一个或多个接触6102，例如接触垫。
电绝缘材料668可以被沉积，使得电绝缘材料668可以至少部分围绕第一芯片108、第二芯片112、第三芯片113、第四芯片688、第五芯片692、一个或多个电互连3541、3542、3545、3546、第一芯片载体104、第二芯片载体106、第三芯片载体372、第一芯片载体顶侧358、第二芯片载体顶侧364以及第三芯片载体顶侧378。电绝缘材料668可以沉积在第一芯片108和第二芯片112之间。电绝缘材料368可以沉积在第二芯片112和第三芯片114之间。电绝缘材料368可以沉积在第一芯片112和第三芯片114之间。电绝缘材料368可以沉积在第一芯片载体104和第二芯片载体106之间。电绝缘材料668可以被沉积，其中除了将第一芯片第一源极/漏极接触324电连接到第三芯片第一源极/漏极接触336的电互连3541之外，第一芯片108可以与第三芯片114电绝缘。电绝缘材料668可以被沉积，其中除了将第一芯片第二源极/漏极接触322电连接到第二芯片第一源极/漏极接触356的电互连3542之外，第一芯片108可以与第二芯片112电绝缘。电绝缘材料668可以被沉积，其中除了将在第三芯片前侧328上方形成的一个或多个接触334电连接到第四芯片688的电互连3545之外，第三芯片114可以与第四芯片688电绝缘。电绝缘材料668可以被沉积，其中除了将在第四芯片前侧696上方形成的一个或多个另外接触698电连接到第五芯片692的电互连3546之外，第四芯片688可以与第五芯片692电绝缘。
电绝缘材料668可以被沉积，使得电绝缘材料668可以至少部分限定芯片封装602的一个或多个侧，例如露出的面向外部的表面。电绝缘材料668可以可选地形成为至少部分围绕芯片载体的一个或多个相应底侧。电绝缘材料468可以被沉积，使得电绝缘材料可以将第一芯片载体104、第二芯片载体106和第三芯片载体372保持在一起，而将第一芯片载体104、第二芯片载体106和第三载体372每个彼此分离和电隔离。
图7示出根据实施例的芯片装置702。芯片装置702可包括芯片装置102、302、402、502和602至少其一的一个或多个或全部特征的基本功能。
芯片装置702可包括第一芯片载体104和第二芯片载体106。芯片装置702可包括电连接到第一芯片载体104的第一芯片108。芯片装置702可包括第二芯片112，其布置在第一芯片载体104上方并且与第一芯片载体104电绝缘；以及第三芯片114，其电连接到第二芯片载体106；其中第一芯片108和第二芯片112至少其一电连接到第三芯片114。
第一芯片108和第二芯片112至少其一可以电连接到第三芯片顶侧328或第三芯片底侧332至少其一。
第一芯片108和第三芯片114至少其一可包括功率半导体芯片，其中功率半导体芯片可包括来自由下述构成的群组的至少一种功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅极双极晶体管、晶闸管、MOS受控晶闸管、硅受控整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
第一芯片108可以布置在第一芯片载体104上方，并且第一芯片108可以经由在第一芯片背侧318上方形成的至少一个接触垫326而电连接到第一芯片载体104。
第一芯片108可以配置成承载第一芯片顶侧316和第一芯片底侧318之间的垂直电流流动。第三芯片114可以配置成承载第三芯片顶侧328和第三芯片底侧332之间的垂直电流流动。
第一芯片108可以经由导电介质342电连接到第一芯片载体104，导电介质342包括下述材料群组中的至少一种，该群组由下述构成：焊料、软焊料、扩散焊料、膏料、纳米膏料、粘合剂、导电粘合剂。
第二芯片112可包括半导体逻辑芯片。该半导体逻辑芯片可包括来自由下述构成的群组的至少一种半导体逻辑器件：ASIC、驱动器、控制器、传感器。
第二芯片背侧348可以布置在第一芯片载体104上方。
第二芯片112可以通过电绝缘介质352与第一芯片载体104电绝缘，电绝缘介质352包括下述材料群组中的至少一种，该群组由下述构成：粘合剂、电绝缘粘合剂、环氧树脂、胶、膏料、粘合剂箔、电绝缘晶片背侧涂层。
第一芯片载体104可包括第一引线框载体。第二芯片载体106可包括第二引线框载体。
第一芯片载体104和第二芯片载体106至少其一可包括下述材料群组中的至少一种，该材料群组由下述构成：铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
第一芯片载体104和第二芯片载体106至少其一可包括下述材料群组中的至少一种，该材料群组由下述构成：NiPdAu、NiAu、NiPd、NiAuAg、NiPdAuAg、NiNiPPdAu、NiNiPAu、NiNiPPd、NiNiPAuAg、NiNiPPdAuAg。
第一芯片载体104和第二芯片载体106至少其一可包括这样的材料，其包括范围在约1nm至1000nm的粗糙度。
第一芯片载体104和第二芯片载体106至少其一可包括这样的材料，其具有范围在约2%至50%的孔隙度。
芯片装置702可以进一步包括一个或多个电互连3541，其配置成将第一芯片108和第二芯片112至少其一电连接到第三芯片114。
芯片装置702可以进一步包括一个或多个电互连354，其中第一电互连3541可以配置成将在第一芯片前侧316上方形成的一个或多个接触垫322、324电连接到在第三芯片前侧328上方形成的一个或多个接触垫334、336；并且其中第二电互连3542可以配置成将在第一芯片前侧316上方形成的一个或多个接触垫322、324电连接到在第二芯片前侧346上方形成的一个或多个接触垫356。
一个或多个电互连3541、3542可包括来自下述电互连的群组的至少一种，该群组由下述构成：导线、导电导线、接合导线、夹具、导电夹具、凸块、电流沉积互连。
芯片装置702可以进一步包括电绝缘材料368，其中电绝缘材料368可以至少部分围绕第一芯片108、第二芯片112和第三芯片114。
芯片装置702可以进一步包括电绝缘材料368，其中电绝缘材料368可以至少部分围绕第一芯片载体104和第二芯片载体106。
芯片装置702可以进一步包括电绝缘材料368，其中电绝缘材料368可以至少部分围绕一个或多个电互连3541，其中一个或多个电互连3541可以配置成将第一芯片108和第二芯片112至少其一电连接到第三芯片114。
芯片装置702可以进一步包括电绝缘材料368，其中电绝缘材料368可以至少部分围绕第一芯片108、第二芯片112和第三芯片114，其中电绝缘材料368可包括下述材料群组中的至少一种，该群组由下述构成：填充或未填充的环氧树脂、预浸渍复合纤维、强化纤维、层压板、模具材料、热固性材料、热塑性材料、填料颗粒、纤维强化层压板、纤维强化聚合物层压板、具有填料颗粒的纤维强化聚合物层压板。
将第一芯片108和第二芯片112至少其一电连接到第三芯片114可包括：通过电流沉积而形成一个或多个电互连354，用于将第一芯片108和第二芯片112至少其一电连接到第三芯片114。
图8示出根据实施例的芯片封装802。芯片封装802可包括芯片装置102、302、402、502、602和702至少其一的一个或多个或全部特征的基本功能。
芯片封装802可包括第一芯片载体104和第二芯片载体106。芯片封装802可包括布置在第一芯片载体104上方的第一芯片108和第二芯片112。芯片封装802可包括布置在第二芯片载体106上方的第三芯片114。芯片封装802可包括电绝缘材料368。第一芯片108和第二芯片112至少其一可以经由一个或多个电互连3541而电连接到第三芯片114。电绝缘材料368可以至少部分围绕第一芯片载体104、第二芯片载体106和电互连3541。
图9示出根据实施例的用于形成芯片封装的方法900。方法900可包括：
将第一芯片和第二芯片布置在第一芯片载体上方(在910)；
将第三芯片布置在第二芯片载体上方(在920)；
形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连(在930)；以及 
利用电绝缘材料至少部分围绕第一芯片载体、第二芯片载体和电互连(940)。
图10示出根据实施例的芯片装置1002。
芯片装置102可包括第一芯片载体104和第二芯片载体106。芯片装置102可包括电连接到第一芯片载体104的第一芯片108，例如半导体芯片，诸如半导体管芯。芯片装置102可包括：布置在第一芯片载体104上方并且与第一芯片载体104电绝缘的第二芯片112，例如半导体芯片，诸如半导体管芯；电连接到第二芯片载体106的第三芯片114，例如半导体芯片，诸如半导体管芯；布置在第二芯片载体106上方并且与第二芯片载体106电绝缘的第四芯片688，例如半导体芯片，诸如半导体管芯；其中第一芯片108和第二芯片112至少其一电连接到第三芯片114和第四芯片688至少其一。
各种实施例提供一种半导体壳体，其具有至少两个金属载体，即管芯垫。至少一个功率半导体芯片和至少一个逻辑集成电路芯片可以形成于每个金属载体上。至少一个功率半导体芯片可以配置成支持垂直电流流动，其中功率半导体芯片的背侧可以电接触到芯片载体。利用电绝缘介质，例如电绝缘膏料或粘合剂箔，逻辑集成电路芯片可以被固定在芯片载体上。
各种实施例提供了利用多个单独金属芯片载体，将多个功率半导体芯片和逻辑芯片集成在封装壳体中。因此提供了更高的集成密度。此外，所述过程可以与并行过程一起实施，并且大量制造会是可能的，例如通过在大面板上的制造过程。
各种实施例确保了可以不需要特殊或特别修改的引线框，例如引线框不需要特别修改以供装配逻辑芯片。反而可以使用标准引线框。
各种实施例提供一种包括多个芯片载体的多芯片壳体，其中多个芯片载体可以彼此隔离并且通过封装材料彼此电绝缘，该封装材料为例如具有或不具有填料颗粒的模具材料、纤维强化层压板、纤维强化聚合物层压板、具有填料颗粒的纤维强化聚合物层压板。
各种实施例提供一种用于多芯片电路的单个壳体，其包括含有逻辑集成电路芯片的功率半桥电路作为驱动器。
各种实施例提供一种芯片装置，其包括：第一芯片载体；第二芯片载体；第一芯片，其电连接到第一芯片载体；第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及第三芯片，其电连接到第二芯片载体；其中第一芯片和第二芯片至少其一电连接到第三芯片。
根据实施例，第一芯片和第二芯片至少其一电连接到第三芯片顶侧或第三芯片底侧至少其一。
根据实施例，第一芯片和第三芯片至少其一包括功率半导体芯片。
根据实施例，该功率半导体芯片包括来自由下述构成的群组的至少一种功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅极双极晶体管、晶闸管、MOS受控晶闸管、硅受控整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
根据实施例，第一芯片配置成承载第一芯片顶侧和第一芯片底侧之间的垂直电流流动。
根据实施例，第三芯片配置成承载第三芯片顶侧和第三芯片底侧之间的垂直电流流动。
根据实施例，第一芯片布置在第一芯片载体上方，并且第一芯片经由在第一芯片背侧上方形成的至少一个接触垫而电连接到第一芯片载体。
根据实施例，第一芯片经由导电介质而电连接到第一芯片载体，该导电介质包括下述材料群组中的至少一种，该群组由下述构成：焊料、软焊料、扩散焊料、膏料、纳米膏料、粘合剂、导电粘合剂。
根据实施例，第二芯片可包括半导体逻辑芯片和半导体存储器芯片至少其一。
根据实施例，半导体逻辑芯片包括来自由下述构成的群组的至少一种半导体逻辑器件：ASIC、驱动器、控制器、传感器。
根据实施例，第二芯片背侧布置在第一芯片载体上方。
根据实施例，第二芯片通过电绝缘介质与第一芯片载体电绝缘，该电绝缘介质包括下述材料群组中的至少一种，该群组由下述构成：粘合剂、电绝缘粘合剂、环氧树脂、胶、膏料、粘合剂箔、电绝缘晶片背侧涂层。
根据实施例，第一芯片载体包括第一引线框载体，并且其中第二芯片载体包括第二引线框载体。
根据实施例，第一芯片载体和第二芯片载体至少其一包括下述材料群组中的至少一种，该材料群组由下述构成：铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
根据实施例，第一芯片载体和第二芯片载体至少其一包括下述材料群组中的至少一种，该材料群组由下述构成：NiPdAu、NiAu、NiPd、NiAuAg、NiPdAuAg、NiNiPPdAu、NiNiPAu、NiNiPPd、NiNiPAuAg、NiNiPPdAuAg。
根据实施例，第一芯片载体和第二芯片载体至少其一包括这样的材料，其包括范围在约1nm至1000nm的粗糙度。
根据实施例，第一芯片载体和第二芯片载体至少其一包括这样的材料，其具有范围在约2%至50%的孔隙度。
根据实施例，芯片装置进一步包括一个或多个电互连，其配置成将第一芯片和第二芯片至少其一电连接到第三芯片。
根据实施例，芯片装置进一步包括一个或多个电互连，其中第一电互连配置成将在第一芯片前侧上方形成的一个或多个接触垫电连接到在第三芯片前侧上方形成的一个或多个接触垫；并且其中第二电互连配置成将在第一芯片前侧上方形成的一个或多个接触垫电连接到在第二芯片前侧上方形成的一个或多个接触垫。
根据实施例，一个或多个电互连包括来自下述电互连的群组的至少一种，该群组由下述构成：导线、导电导线、接合导线、夹具、导电夹具、凸块、电流沉积互连。
根据实施例，芯片装置进一步包括电绝缘材料，其中电绝缘材料至少部分围绕第一芯片、第二芯片和第三芯片。
根据实施例，芯片装置进一步包括电绝缘材料，其中电绝缘材料至少部分围绕第一芯片载体和第二芯片载体。
根据实施例，芯片装置进一步包括电绝缘材料，其中电绝缘材料至少部分围绕一个或多个电互连，其中一个或多个电互连配置成将第一芯片和第二芯片至少其一电连接到第三芯片。
根据实施例，芯片装置进一步包括电绝缘材料，其中电绝缘材料至少部分围绕第一芯片、第二芯片和第三芯片，其中电绝缘材料包括下述材料群组中的至少一种，该群组由下述构成：填充或未填充的环氧树脂、预浸渍复合纤维、强化纤维、层压板、模具材料、热固性材料、热塑性材料、填料颗粒、纤维强化层压板、纤维强化聚合物层压板、具有填料颗粒的纤维强化聚合物层压板。
各种实施例提供一种用于形成芯片装置的方法，其中该方法提供：将第一芯片电连接到第一芯片载体；将第二芯片布置在第一芯片载体上并且将第二芯片与第一芯片载体电绝缘；将第三芯片电连接到第二芯片载体；以及将第一芯片和第二芯片至少其一电连接到第三芯片。
根据实施例，将第一芯片和第二芯片至少其一电连接到第三芯片包括通过电流沉积形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连。
各种实施例提供一种芯片封装，其包括：第一芯片载体；第二芯片载体；第一芯片和第二芯片，其布置在第一芯片载体上方；第三芯片，其布置在第二芯片载体上方；以及电绝缘材料；其中第一芯片和第二芯片至少其一经由一个或多个电互连而电连接到第三芯片，并且其中电绝缘材料至少部分围绕第一芯片载体、第二芯片载体和电互连。
各种实施例提供一种用于形成芯片封装的方法，该方法包括：将第一芯片和第二芯片布置在第一芯片载体上方；将第三芯片布置在第二芯片载体上方；形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连；以及利用电绝缘材料至少部分围绕第一芯片载体、第二芯片载体和电互连。
根据实施例，形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连包括电流沉积用于将第一芯片和第二芯片至少其一电连接到第三芯片的导电材料。
各种实施例提供一种芯片装置，其包括：第一芯片载体；第二芯片载体；第一芯片，其电连接到第一芯片载体；第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及第三芯片，其电连接到第二芯片载体；第四芯片，其布置在第二芯片载体上方并且与第二芯片载体电绝缘；并且其中第一芯片和第二芯片至少其一电连接到第三芯片和第四芯片至少其一。
尽管已经参考特定实施例具体示出和说明了本发明，但是本领域技术人员应理解，此处可以进行形式和细节上的各种变化而不背离由所附权利要求界定的本发明的精神和范围。本发明的范围因而由所附权利要求指示，并且落在权利要求等同物的含义和范围内的所有变化旨在被涵盖在内。

Claims (30)

1.一种芯片装置，包括：
第一芯片载体；
第二芯片载体；
第一芯片，其电连接到第一芯片载体；
第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及
第三芯片，其电连接到第二芯片载体；
其中第一芯片和第二芯片至少其一电连接到第三芯片。
2.根据权利要求1的芯片装置，其中第一芯片和第二芯片至少其一电连接到第三芯片顶侧或第三芯片底侧至少其一。
3.根据权利要求1的芯片装置，
其中第一芯片和第三芯片至少其一包括功率半导体芯片。
4.根据权利要求3的芯片装置，
其中功率半导体芯片包括来自由下述构成的群组的至少一种功率半导体器件：功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅极双极晶体管、晶闸管、MOS受控晶闸管、硅受控整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
5.根据权利要求3的芯片装置，
其中第一芯片配置成承载第一芯片顶侧和第一芯片底侧之间的垂直电流流动。
6.根据权利要求3的芯片装置，
其中第三芯片配置成承载第三芯片顶侧和第三芯片底侧之间的垂直电流流动。
7.根据权利要求1的芯片装置，
其中第一芯片布置在第一芯片载体上方，并且
其中第一芯片经由在第一芯片背侧上方形成的至少一个接触垫而电连接到第一芯片载体。
8.根据权利要求1的芯片装置，
其中第一芯片经由导电介质电连接到第一芯片载体，该导电介质包括下述材料群组中的至少一种，该群组由下述构成：焊料、软焊料、扩散焊料、膏料、纳米膏料、粘合剂、导电粘合剂。
9.根据权利要求1的芯片装置，
其中第二芯片包括半导体逻辑芯片和半导体存储器芯片至少其一。
10.根据权利要求9的芯片装置，
其中半导体逻辑芯片包括来自由下述构成的群组的至少一种半导体逻辑器件：ASIC、驱动器、控制器、传感器。
11.根据权利要求1的芯片装置，
其中第二芯片背侧布置在第一芯片载体上方。
12.根据权利要求1的芯片装置，
其中第二芯片通过电绝缘介质与第一芯片载体电绝缘，该电绝缘介质包括下述材料群组中的至少一种，该群组由下述构成：粘合剂、电绝缘粘合剂、环氧树脂、胶、膏料、粘合剂箔、电绝缘晶片背侧涂层。
13.根据权利要求1的芯片装置，
其中第一芯片载体包括第一引线框载体，并且
其中第二芯片载体包括第二引线框载体。
14.根据权利要求1的芯片装置，
其中第一芯片载体和第二芯片载体至少其一包括下述材料群组中的至少一种，该材料群组由下述构成：铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
15.根据权利要求1的芯片装置，
其中第一芯片载体和第二芯片载体至少其一包括下述材料群组中的至少一种，该材料群组由下述构成：NiPdAu、NiAu、NiPd、NiAuAg、NiPdAuAg、NiNiPPdAu、NiNiPAu、NiNiPPd、NiNiPAuAg、NiNiPPdAuAg。
16.根据权利要求1的芯片装置，
其中第一芯片载体和第二芯片载体至少其一包括这样的材料，其包括范围在约1nm至1000nm的粗糙度。
17.根据权利要求1的芯片装置，
其中第一芯片载体和第二芯片载体至少其一包括这样的材料，其具有范围在约2%至50%的孔隙度。
18.根据权利要求1的芯片装置，进一步包括
一个或多个电互连，配置成将第一芯片和第二芯片至少其一电连接到第三芯片。
19.根据权利要求1的芯片装置，进一步包括
一个或多个电互连，
其中第一电互连配置成将在第一芯片前侧上方形成的一个或多个接触垫电连接到在第三芯片前侧上方形成的一个或多个接触垫；以及
其中第二电互连配置成将在第一芯片前侧上方形成的一个或多个接触垫电连接到在第二芯片前侧上方形成的一个或多个接触垫。
20.根据权利要求18的芯片装置，
其中一个或多个电互连包括来自下述电互连的群组的至少一种，该群组由下述构成：导线、导电导线、接合导线、夹具、导电夹具、凸块、电流沉积互连。
21.根据权利要求1的芯片装置，进一步包括：
电绝缘材料，
其中电绝缘材料至少部分围绕第一芯片、第二芯片和第三芯片。
22.根据权利要求1的芯片装置，进一步包括：
电绝缘材料，
其中电绝缘材料至少部分围绕第一芯片载体和第二芯片载体。
23.根据权利要求1的芯片装置，进一步包括：
电绝缘材料，
其中电绝缘材料至少部分围绕一个或多个电互连，其中一个或多个电互连配置成将第一芯片和第二芯片至少其一电连接到第三芯片。
24.根据权利要求1的芯片装置，进一步包括：
电绝缘材料，
其中电绝缘材料至少部分围绕第一芯片、第二芯片和第三芯片，
其中电绝缘材料包括下述材料群组中的至少一种，该群组由下述构成：填充或未填充的环氧树脂、预浸渍复合纤维、强化纤维、层压板、模具材料、热固性材料、热塑性材料、填料颗粒、纤维强化层压板、纤维强化聚合物层压板、具有填料颗粒的纤维强化聚合物层压板。
25.一种用于形成芯片装置的方法，该方法包括：
将第一芯片电连接到第一芯片载体；
将第二芯片布置在第一芯片载体上方并且将第二芯片与第一芯片载体电绝缘；
将第三芯片电连接到第二芯片载体；以及
将第一芯片和第二芯片至少其一电连接到第三芯片。
26.根据权利要求19的方法，
其中将第一芯片和第二芯片至少其一电连接到第三芯片包括通过电流沉积形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连。
27.一种芯片封装，包括：
第一芯片载体；
第二芯片载体；
第一芯片和第二芯片，其布置在第一芯片载体上方；
第三芯片，其布置在第二芯片载体上方；以及
电绝缘材料；
其中第一芯片和第二芯片至少其一经由一个或多个电互连而电连接到第三芯片，并且
其中电绝缘材料至少部分围绕第一芯片载体、第二芯片载体和电互连。
28.一种用于形成芯片封装的方法，该方法包括：
将第一芯片和第二芯片布置在第一芯片载体上方；
将第三芯片布置在第二芯片载体上方；
形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连；以及 
利用电绝缘材料至少部分围绕第一芯片载体、第二芯片载体和电互连。
29.根据权利要求21的方法，
其中形成用于将第一芯片和第二芯片至少其一电连接到第三芯片的电互连包括电流沉积用于将第一芯片和第二芯片至少其一电连接到第三芯片的导电材料。
30.一种芯片装置，包括：
第一芯片载体；
第二芯片载体；
第一芯片，其电连接到第一芯片载体；
第二芯片，其布置在第一芯片载体上方并且与第一芯片载体电绝缘；以及
第三芯片，其电连接到第二芯片载体；
第四芯片，其布置在第二芯片载体上方并且与第二芯片载体电绝缘；以及
其中第一芯片和第二芯片至少其一电连接到第三芯片和第四芯片至少其一。
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