JP7337034B2 - 半導体パッケージおよび半導体装置 - Google Patents

半導体パッケージおよび半導体装置 Download PDF

Info

Publication number
JP7337034B2
JP7337034B2 JP2020154536A JP2020154536A JP7337034B2 JP 7337034 B2 JP7337034 B2 JP 7337034B2 JP 2020154536 A JP2020154536 A JP 2020154536A JP 2020154536 A JP2020154536 A JP 2020154536A JP 7337034 B2 JP7337034 B2 JP 7337034B2
Authority
JP
Japan
Prior art keywords
semiconductor package
substrate
semiconductor
exposed
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020154536A
Other languages
English (en)
Other versions
JP2022048623A (ja
Inventor
洋輔 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2020154536A priority Critical patent/JP7337034B2/ja
Priority to US17/348,892 priority patent/US11508698B2/en
Priority to DE102021120891.2A priority patent/DE102021120891B4/de
Priority to CN202111062226.0A priority patent/CN114188294A/zh
Publication of JP2022048623A publication Critical patent/JP2022048623A/ja
Application granted granted Critical
Publication of JP7337034B2 publication Critical patent/JP7337034B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本開示は、半導体パッケージおよび半導体装置に関する。
特許文献１には、複数の半導体素子と、配線用素子とを樹脂封止して一体化した構成の半導体装置が開示されている。
国際公開第２０１０/１１０１７０号
特許文献１に記載の半導体装置では、例えばソース電極を外部の回路と接続するために、ワイヤボンドまたはリードフレームといった外部接続部材を設ける必要があった。また、配線用素子が半導体装置の中央に設けられた場合には、制御端子の接続部材と主電流の接続部材とが干渉してしまうことから、レイアウトが制限されるという問題があった。本開示は、上記の問題点を解決するためになされたものであり、複数の半導体素子と配線用素子とを樹脂封止して一体化した半導体パッケージにおいて、レイアウトの自由度および組み立ての容易さを向上することを目的とする。
本開示の半導体パッケージは、導体基板と、導体基板の上面に接合されたスイッチング機能を有する複数の半導体素子と、導体基板の上面に接合された複数の半導体素子より少数の配線用素子と、導体基板の下面を除く一部と、複数の半導体素子と、配線用素子とを封止する封止材と、を備え、複数の半導体素子のそれぞれは、第１基板と、第１基板の導体基板と反対側に設けられた第１主電極部と、第１基板の導体基板側に設けられ、導体基板と接合された第２主電極部と、第１主電極部と第２主電極部との間に流れる電流を制御するための制御パッドと、を備え、配線用素子は、第２基板と、第２基板の導体基板と反対側に設けられた複数の第１パッドと、第２基板の導体基板と反対側に設けられ、複数の第１パッドと電気的に接続され、制御パッドとワイヤによって接続された複数の第２パッドと、を備え、複数の半導体素子の夫々の第１主電極部と電気的に接続され、導体基板の下面が露出する封止材の面から一部が露出するフレームと、複数の第１パッドと電気的に接続され、封止材の、導体基板の下面が露出する面とは反対側の面から一部が露出する複数の端子ブロックと、をさらに備える。
本開示の半導体パッケージによれば、半導体素子の主電流経路となる導体基板およびフレームの両方が封止材の一方の面から露出する。従って、半導体素子の制御端子となる配線用素子の第２パッドの接続を封止材の他方の面上で行うことにより、主電流経路の配線との干渉を抑制することができる。そのため、配線用素子のレイアウトの自由度が向上する。また、本開示の半導体パッケージは主電流経路となるフレームを内蔵するため、半導体パッケージの外部の回路との接続のために別途の接続部材を必要とせず、容易に接続を行うことができる。従って、本開示の半導体パッケージによれば容易に半導体装置を組み立てることができる。
導体基板上の半導体素子と配線用素子の配置を示す図である。 図１のＡ－Ａ´断面図である。 実施の形態１の半導体パッケージを上方から見た平面図である。 実施の形態１の半導体パッケージを下方から見た平面図である。 図３のＢ－Ｂ´線に沿った実施の形態１の半導体パッケージの断面図である。 図３のＣ－Ｃ´線に沿った実施の形態１の半導体パッケージの断面図である。 図３のＢ－Ｂ´線と同様の断面における実施の形態１の変形例の半導体パッケージの断面図である。 絶縁基板の上面図である。 実施の形態１の半導体装置の上面図である。
１．実施の形態１
１．１ 序
図１は、実施の形態１の半導体パッケージ１について示す模式図である。但し、半導体パッケージ１に含まれるフレーム５、複数の端子ブロック６、スペーサ導体７、および封止材８は、図１では説明の都合上省略されており、図３から図６で図示される。
図１に示すように、半導体パッケージ１は、導体基板２、複数の半導体素子３、および配線用素子４を備えている。半導体素子３の個数は２個以上であればよい。また、配線用素子４の個数は半導体素子３の個数より少なければよい。図１では、８個の半導体素子３と、１個の配線用素子４とを備える半導体パッケージ１を示しており、以下、この半導体パッケージ１について説明する。
各半導体素子３は、導体基板２の上面に接合され、導体基板２と電気的かつ熱的に接続されている。配線用素子４も、各半導体素子３と同様に、導体基板２の上面に接合され、導体基板２と電気的かつ熱的に接続されている。図１の例では、平面視において８個の半導体素子３が配線用素子４を取り囲むように配置されている。
１．２ 半導体素子
各半導体素子３は、スイッチング機能を有する素子であり、例えばＳｉＣを半導体材料として含むＭＯＳＦＥＴ（以下、「ＳｉＣ－ＭＯＳＦＥＴ」と称する）である。但し、各半導体素子３は、Ｓｉなど、ＳｉＣ以外を半導体材料として含む半導体素子であってもよい。また、各半導体素子３は、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）など、ＭＯＳＦＥＴ以外の半導体素子であってもよい。
図１に示されるように、各半導体素子３は、第１基板である半導体基板３１、おもて面電極３２、裏面電極（図示せず）、１または複数の制御パッド３４、および耐圧構造３５を備える。
第１主電極部であるおもて面電極３２は、半導体基板３１の導体基板２と逆側の面であるおもて面に設けられている。おもて面電極３２は、ＭＯＳＦＥＴのソース電極に対応している。
第２主電極部である裏面電極（図示せず）は、半導体基板３１の導体基板２側の面である裏面に設けられており、導体基板２と接合されている。これにより、各半導体素子３の裏面電極の電位は互いに等しくなっている。裏面電極は、ＭＯＳＦＥＴのドレイン電極に対応している。
制御パッド３４は、おもて面電極３２と裏面電極との間に流れる電流を制御するためのパッドである。制御パッド３４は、ＭＯＳＦＥＴのゲート電極に対応している。
おもて面電極３２、裏面電極、および制御パッド３４は、例えば、Ｎｉ、Ｃｕ、Ａｕ、またはＡｇなどのシンタ接続が可能な膜を備えている。おもて面電極３２、裏面電極、および制御パッド３４は、Ａｌなどの電極材と、その上のシンタ接続が可能な膜との積層構造であってもよい。
１．３ 配線用素子
図２は、図１のＡ－Ａ´線に沿った断面図である。但し、図２において導体基板２の図示は省略されている。図２に示されるように、配線用素子４は、第２基板である配線用基板４１、絶縁膜４２、複数の接続配線４３、金属膜４４、および保護膜４５を備えている。
配線用基板４１は、例えばＳｉからなる。
複数の接続配線４３は、配線用基板４１の導体基板２と逆側の面であるおもて面に、絶縁膜４２を介して設けられる。各接続配線４３は、第１パッド４３ａ、第２パッド４３ｂ、および引き回し部４３ｃを備えている。第１パッド４３ａと第２パッド４３ｂとは、引き回し部４３ｃによって電気的に接続されている。
複数の接続配線４３は、例えばＡｌからなる電極パターンである。複数の接続配線４３のうち少なくとも第１パッド４３ａに、例えば、Ｎｉ、Ｃｕ、Ａｕ、またはＡｇなどのシンタ接続が可能な膜４６が形成されていてもよい。必要に応じて、第２パッド４３ｂまたは引き回し部４３ｃに、シンタ接続が可能な膜４６が形成されていてもよい。また、接続配線４３自体が、シンタ接続可能な材料で構成されていてもよい。
金属膜４４は、配線用基板４１の導体基板２側の面である裏面に設けられており、導体基板２と接合されている。つまり、金属膜４４は導体基板２との接合用の膜である。
保護膜４５は、絶縁膜４２の少なくとも一部と、接続配線４３の少なくとも一部とを覆う。第１パッド４３ａと第２パッド４３ｂは、保護膜４５から露出する。
１．４ 半導体素子と配線用素子の接続
各半導体素子３の制御パッド３４は、配線用素子４の第２パッド４３ｂと電気的に接続される。この接続には、ＡｕまたはＡｇからなる細線ワイヤ、もしくはＡｌからなるワイヤが用いられてもよい。
各半導体素子３の裏面電極と、配線用素子４の金属膜４４とは、共に導体基板２に接続される。
各半導体素子３のおもて面電極３２は、フレーム５（図３から図６参照）に接続される。
配線用素子４の第１パッド４３ａには、端子ブロック６が接続される。
各半導体素子３の裏面電極と導体基板２の接合、金属膜４４と導体基板２の接合、おもて面電極３２とフレーム５との接合、および、第１パッド４３ａと端子ブロック６との接続には、シンタ接合を用いることができる。シンタ接合に用いられる接合材は、例えばＡｇまたはＣｕからなる。この接合材は、加圧接合プロセスまたは無加圧接合プロセスなどにより接続を形成する。
半導体素子３の上面におけるおもて面電極３２の周辺には耐圧構造３５があり、半導体素子３の端部はドレイン電位になっている。そのため、半導体素子３の端部をフレーム５と絶縁するには、ある程度の絶縁距離が必要である。そこで、半導体素子３の端部とフレーム５との距離を稼ぐために、おもて面電極３２は、スペーサ導体７（図５参照）を介してフレーム５と接続されてもよい。スペーサ導体７は、フレーム５と一体形成された部品でもよいし、フレーム５と接合材で接続された別体の部品でもよい。
１．５ 封止
複数の半導体素子３と、１または複数の配線用素子４と、導体基板２の少なくとも一部と、フレーム５の少なくとも一部と、複数の端子ブロック６の少なくとも一部とは、封止材８により封止される。
図３から図６は、フレーム５と封止材８を含む半導体パッケージ１を示す図である。
図３は、半導体パッケージ１をおもて側からみた平面図である。図３に示されるように、フレーム５は平面視においてその中央部に開口を有している。フレーム５の開口は、配線用素子４に重なっており、これによりフレーム５は配線用素子４とは接続されない（図５参照）。さらに、フレーム５の開口は、配線用素子４と接続される半導体素子３の制御パッド３４の上部に達していてもよい。その場合、配線用素子４と制御パッド３４とを接続するワイヤボンドのワイヤの高さを気にすることなくフレーム５を設けることができる。また、配線用素子４の第１パッド４３ａに接続された端子ブロック６は、図３に示されるように、封止材８の上面からその一部が露出する。
図４は、半導体パッケージ１を裏側からみた平面図である。図５は、図３のＢ－Ｂ´線に沿った半導体パッケージ１の断面図である。図６は、図３のＣ－Ｃ´線に沿った半導体パッケージ１の断面図である。図４から図６に示されるように、封止材８の下面から、導体基板２の下面とフレーム５の少なくとも２箇所が露出する。なお、図５では、説明の都合上ワイヤの図示が省略されている。
封止材８の下面から露出するフレーム５の２つの露出部は、図５および図６に示すように、同じく封止材８の下面から露出する導体基板２の下面を挟んで対向する。
図５および図６に示されるように、封止材８から露出する導体基板２の下面と、封止材８から露出するフレーム５の露出部との間には、導体基板２とフレーム５との間の絶縁距離を確保するための沿面構造８ａが設けられている。図５および図６において、沿面構造８ａは、封止材８の凹型の部分である。
図７に示されるように、沿面構造８ａは、封止材８の凸形の部分であってもよい。図５または図７に示される沿面構造８ａは、トランスファーモールド法による半導体パッケージの封止工程に使用される金型を用いて形成される。図７に示されるように沿面構造８ａが封止材８の凸型の部分である場合、半導体パッケージ１が後述する絶縁基板１２と接合される際、回路パターンの隙間に重なる位置に沿面構造８ａが配置されることによって、沿面構造８ａを回路パターンに対する半導体パッケージ１の位置決め部品として使用することが可能である。なお、図７では、説明の都合上ワイヤの図示が省略されている。
１．６ 半導体装置
図８は、絶縁基板１２の上面図である。絶縁基板１２は、絶縁基材１３と、絶縁基材１３の上面に互いに隙間を空けて設けられた複数の回路パターン１０Ｎ，１０Ｐ，１０Ｏ１，１０Ｏ２とを備える。
絶縁基板１２の回路パターン１０Ｎ，１０Ｐ，１０Ｏ１，１０Ｏ２に複数の半導体パッケージ１が電気的かつ熱的に接続されることにより、半導体装置１１が形成される。回路パターン１０Ｎ，１０Ｐ，１０Ｏ１，１０Ｏ２と各半導体パッケージ１との接続には、はんだ接合またはシンタ接合が用いられてもよい。
図９は、２個の半導体パッケージ１を含む半導体装置１１の上面図である。半導体装置１１は、ハーフブリッジ回路を構成しており、上アームと下アームの夫々に半導体パッケージ１が１個ずつ用いられている。なお、上アームまたは下アームに複数の半導体パッケージ１が用いられてもよい。
図９において、上アーム用の半導体パッケージを半導体パッケージ１Ｈ、下アーム用の半導体パッケージを半導体パッケージ１Ｌと表記している。
回路パターン１０Ｐおよび回路パターン１０Ｎは、それぞれ半導体装置１１のＰ電位およびＮ電位に対応する。また、回路パターン１０Ｏ１，１０Ｏ２は、半導体装置１１の出力電位に対応する。回路パターン１０Ｏ１，１０Ｏ２は、回路パターン１０Ｐを挟んで対向する位置に配置される。
図５から図７で示されたように、フレーム５の少なくとも２箇所と、導体基板２が半導体パッケージ１の裏面から露出する。上アームの半導体パッケージ１Ｈでは、導体基板２の下面が回路パターン１０Ｐと接続され、フレーム５の一方の露出部が回路パターン１０Ｏ２と接続され、他方の露出部が回路パターン１０Ｏ１と接続される。すなわち、上アームの半導体パッケージ１Ｈにおけるフレーム５の他方の露出部は、下アームの半導体パッケージ１Ｌにおいて導体基板２が接続される回路パターン１０Ｏ１に接続される。
回路パターン１０Ｏ２には、半導体装置１１から電流を取り出すための出力端子５１が接続されている。回路パターン１０ＰにはＰ主電極５２が接続され、回路パターン１０ＮにはＮ主電極５３が接続される。Ｐ主電極５２およびＮ主電極５３は、外部のコンデンサモジュールなどと接続される。
下アームの半導体パッケージ１Ｌでは、導体基板２が回路パターン１０Ｏ１に接続され、フレーム５の２つの露出部が回路パターン１０Ｎに接続されている。
下アームの半導体パッケージ１Ｌにおいても、半導体パッケージ１Ｈと同様、フレーム５が２箇所で封止材８から露出するため、回路パターン１０Ｎは、フレーム５の各露出部に対応する位置に分岐して配設されている。
上アームの半導体パッケージ１Ｈが出力端子５１側に配置され、下アームの半導体パッケージ１ＬがＰ主電極５２とＮ主電極５３の側に配置される。上アームの半導体パッケージ１Ｈと下アームの半導体パッケージ１Ｌは、互いに略直角になる向きで配置される。
半導体パッケージ１の平面形状は矩形である。複数の端子ブロック６は、半導体パッケージ１の平面視における外形の辺に対して斜め方向に配列される。
各端子ブロック６は、外部信号端子５４に対してワイヤ５５で電気的に接続される。外部信号端子５４に入力された制御信号が、端子ブロック６と配線用素子４の接続配線４３とを経由して半導体素子３に伝えられる。こうして、半導体パッケージ１が駆動され、半導体装置１１の回路が動作する。なお、外部信号端子５４と端子ブロック６との接合は、ワイヤを用いない直接接合であってもよい。
１．７ 作用効果
半導体素子３の裏面電極に接続された導体基板２と、半導体素子３のおもて面電極３２に接続されたフレーム５とは、半導体パッケージ１の下面から露出する。半導体パッケージ１の上面からは、端子ブロック６のみが露出する。そのため、主電流を取り扱うための電流容量の大きい配線接続を設ける必要がなく、簡易な接続方法により半導体装置１１を構成することができる。
半導体パッケージ１では、主電流経路としてのフレーム５が封止材８に露出部を除き内包されているため、外部の配線材料を用いて主電極を接続する必要がない。そして、半導体素子３の裏面およびおもて面を、同一のダイボンド工程で回路パターンに接続することができるため、半導体装置１１の製造工程が少なくなる。回路規模の大きい半導体装置１１を組み立てる場合には、寸法の大きい部材を使用するため公差が大きくなることがある。しかし、半導体パッケージ１はフレーム５を内蔵しているため、公差が小さい。従って、製造性および信頼性の高い半導体装置１１を安定して生産することができる。
また、回路パターン同士を極力近づけることができるため、半導体装置１１の寄生インダクタンスを極力小さくすることができる。従って、半導体素子３にＳｉＣ－ＭＯＳＦＥＴを用いた場合に生じるリンギングを抑制することができる。
端子ブロック６は、少数のワイヤにより外部信号端子５４と接続される。あるいは、端子ブロック６は、はんだ等を用いて直接外部信号端子５４と接続される。いずれの場合も、端子ブロック６と外部信号端子５４との接続は半導体パッケージ１の上面側で行われるため、半導体パッケージ１の下面側における主電流回路パターンと干渉しない。従って、レイアウト自由度と歩留まりが向上する。その結果、簡易な組み立てで半導体装置１１を構成することができ、製造コストが低減する。
図９に示した半導体装置１１において、半導体パッケージ１を用いることにより、回路パターンのレイアウトの自由度が向上するため、低Ｌｓ化および省スペース化を図ることができる。
また、上アームの半導体パッケージ１Ｈと下アームの半導体パッケージ１Ｌが略直角に配置されることで、回路パターンが等長配線になり、低Ｌｓ化の実現およびアンバランス動作の防止を図ることができる。
また、複数の端子ブロック６を半導体パッケージ１の辺に対して斜めに配列することで、上アームの半導体パッケージ１Ｈと下アームの半導体パッケージ１Ｌとを略直角に配置しても、以下の２つの効果が得られる。
１つ目の効果は、端子ブロック６と外部信号端子５４とをワイヤボンド接合する際に、ワイヤ同士が干渉することが抑制されることである。
２つ目の効果は、上アームの半導体パッケージ１Ｈに対する外部信号端子５４の配列と、下アームの半導体パッケージ１Ｌに対する外部信号端子５４の配列を、平行にすることができる。これにより、外部信号端子５４に対する制御基板の取り付け性が確保される。
従って、上アームの半導体パッケージ１Ｈの配置方向と下アームの半導体パッケージ１Ｌの配置方向がなす角は、上記の２つの効果を奏する範囲において、厳密な直角からずれていても良い。上記の「略直角」における「略」は、このような誤差を許容する意味で用いられている。
沿面構造８ａが封止材８の一部を用いて形成されることで、沿面構造８ａを設けることによる追加のコストなしで、沿面距離を稼ぐことができる他、半導体パッケージ１の小型化を図ることができる。沿面構造８ａが封止材８の一部の凸部である場合、回路パターン同士の隙間に沿面構造８ａが入る設計にすることで、セルフアライメントの部品として活用することができ、半導体装置１１の製造性を向上することができる。
なお、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。
１，１Ｈ，１Ｌ 半導体パッケージ、２ 導体基板、３ 半導体素子、４ 配線用素子、５ フレーム、６ 端子ブロック、７ スペーサ導体、８ 封止材、８ａ 沿面構造、１０Ｎ，１０Ｏ１，１０Ｏ２，１０Ｐ 回路パターン、１１ 半導体装置、１２ 絶縁基板、１３ 絶縁基材、３１ 半導体基板、３２ おもて面電極、３４ 制御パッド、３５ 耐圧構造、４１ 配線用基板、４２ 絶縁膜、４３ 接続配線、４３ａ 第１パッド、４３ｂ 第２パッド、４３ｃ 引き回し部、４４ 金属膜、４５ 保護膜、５１ 出力端子、５２ Ｐ主電極、５３ Ｎ主電極、５４ 外部信号端子、５５ ワイヤ。

Claims (8)

  1. 導体基板と、
    前記導体基板の上面に接合されたスイッチング機能を有する複数の半導体素子と、
    前記導体基板の上面に接合された前記複数の半導体素子より少数の配線用素子と、
    前記導体基板の下面を除く一部と、前記複数の半導体素子と、前記配線用素子とを封止する封止材と、
    を備え、
    前記複数の半導体素子のそれぞれは、
    第１基板と、
    前記第１基板の前記導体基板と反対側に設けられた第１主電極部と、
    前記第１基板の前記導体基板側に設けられ、前記導体基板と接合された第２主電極部と、
    前記第１主電極部と前記第２主電極部との間に流れる電流を制御するための制御パッドと、
    を備え、
    前記配線用素子は、
    第２基板と、
    前記第２基板の前記導体基板と反対側に設けられた複数の第１パッドと、
    前記第２基板の前記導体基板と反対側に設けられ、前記複数の第１パッドと電気的に接続され、前記制御パッドとワイヤによって接続された複数の第２パッドと、
    を備え、
    前記複数の半導体素子の夫々の前記第１主電極部と電気的に接続され、前記導体基板の下面が露出する前記封止材の面から一部が露出するフレームと、
    前記複数の第１パッドと電気的に接続され、前記封止材の、前記導体基板の下面が露出する面とは反対側の面から一部が露出する複数の端子ブロックと、
    をさらに備える、
    半導体パッケージ。
  2. 前記封止材から露出する前記導体基板の下面と、前記封止材から露出する前記フレームの露出部との間に、凸形または凹形の沿面構造をさらに備える、
    請求項１に記載の半導体パッケージ。
  3. 請求項１または請求項２に記載の少なくとも１つの半導体パッケージと、
    前記少なくとも１つの半導体パッケージが接合される絶縁基板と、を備え、
    前記絶縁基板は、
    絶縁基材と、
    前記絶縁基材の上面に互いに隙間を空けて設けられた複数の回路パターンとを備え、
    前記複数の回路パターンは、前記封止材から露出する前記導体基板の下面と、前記封止材から露出する前記フレームの露出部とに接続される、
    半導体装置。
  4. 前記少なくとも１つの半導体パッケージにおける前記沿面構造は、請求項２に記載の少なくとも１つの半導体パッケージであり、
    前記沿面構造は、前記封止材の一部である凸形であり、前記少なくとも１つの半導体パッケージが前記絶縁基板と接合される際、前記複数の回路パターンの隙間に重なる、
    請求項３に記載の半導体装置。
  5. 前記少なくとも１つの半導体パッケージは、ハーフブリッジ回路の上アームと下アームの夫々を構成し、
    前記少なくとも１つの半導体パッケージの夫々において、前記フレームの少なくとも２箇所が前記封止材から露出する、
    請求項３または請求項４に記載の半導体装置。
  6. 前記少なくとも１つの半導体パッケージの夫々において、前記フレームの前記封止材からの２つの露出部が、平面視において、前記封止材から露出する前記導体基板の下面を挟んで対向し、
    前記下アームを構成する前記少なくとも１つの半導体パッケージにおける前記フレームの前記封止材からの前記２つの露出部は、Ｎ主電極に対応する前記回路パターンに接続され、
    前記上アームを構成する前記少なくとも１つの半導体パッケージにおける前記フレームの前記封止材からの前記２つの露出部の一方は、前記半導体装置の出力端子に接続され、他方は前記下アームを構成する前記少なくとも１つの半導体パッケージの前記導体基板が接続される前記回路パターンに接続される、
    請求項５に記載の半導体装置。
  7. 前記上アームを構成する前記少なくとも１つの半導体パッケージは、前記下アームを構成する前記少なくとも１つの半導体パッケージの配置方向に対して略直角に配置される、
    請求項６に記載の半導体装置。
  8. 前記少なくとも１つの半導体パッケージの平面形状は矩形であり、
    前記複数の端子ブロックは、前記少なくとも１つの半導体パッケージの平面視における外形の辺に対して斜めに配列された、
    請求項７に記載の半導体装置。
JP2020154536A 2020-09-15 2020-09-15 半導体パッケージおよび半導体装置 Active JP7337034B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2020154536A JP7337034B2 (ja) 2020-09-15 2020-09-15 半導体パッケージおよび半導体装置
US17/348,892 US11508698B2 (en) 2020-09-15 2021-06-16 Semiconductor package and semiconductor device
DE102021120891.2A DE102021120891B4 (de) 2020-09-15 2021-08-11 Halbleiter-Package und Halbleitervorrichtung
CN202111062226.0A CN114188294A (zh) 2020-09-15 2021-09-10 半导体封装件及半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020154536A JP7337034B2 (ja) 2020-09-15 2020-09-15 半導体パッケージおよび半導体装置

Publications (2)

Publication Number Publication Date
JP2022048623A JP2022048623A (ja) 2022-03-28
JP7337034B2 true JP7337034B2 (ja) 2023-09-01

Family

ID=80351576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020154536A Active JP7337034B2 (ja) 2020-09-15 2020-09-15 半導体パッケージおよび半導体装置

Country Status (4)

Country Link
US (1) US11508698B2 (ja)
JP (1) JP7337034B2 (ja)
CN (1) CN114188294A (ja)
DE (1) DE102021120891B4 (ja)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217072A (ja) 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
JP2008160163A (ja) 2008-03-24 2008-07-10 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
JP2013038309A (ja) 2011-08-10 2013-02-21 Denso Corp 半導体モジュールおよびそれを備えた半導体装置
US20140159216A1 (en) 2011-08-10 2014-06-12 Denso Corporation Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module
JP2018056538A (ja) 2016-09-26 2018-04-05 株式会社パウデック 半導体パッケージ、モジュールおよび電気機器
WO2019202687A1 (ja) 2018-04-18 2019-10-24 三菱電機株式会社 半導体モジュール
JP2020022216A (ja) 2018-07-30 2020-02-06 三菱電機株式会社 電力変換装置
WO2020110170A1 (ja) 2018-11-26 2020-06-04 三菱電機株式会社 半導体パッケージ、その製造方法、及び、半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5142403B2 (ja) 2009-03-26 2013-02-13 パナソニック株式会社 放電灯点灯装置、灯具、及び車両
WO2012039115A1 (ja) * 2010-09-24 2012-03-29 オンセミコンダクター・トレーディング・リミテッド 回路装置
US9305876B2 (en) 2013-02-01 2016-04-05 Infineon Technologies Austria Ag Device including a semiconductor chip and wires
JP6999462B2 (ja) 2018-03-26 2022-01-18 日立Astemo株式会社 パワー半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005217072A (ja) 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
JP2008160163A (ja) 2008-03-24 2008-07-10 Renesas Technology Corp 半導体装置及びその製造方法、並びに電子装置
JP2013038309A (ja) 2011-08-10 2013-02-21 Denso Corp 半導体モジュールおよびそれを備えた半導体装置
US20140159216A1 (en) 2011-08-10 2014-06-12 Denso Corporation Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module
JP2018056538A (ja) 2016-09-26 2018-04-05 株式会社パウデック 半導体パッケージ、モジュールおよび電気機器
WO2019202687A1 (ja) 2018-04-18 2019-10-24 三菱電機株式会社 半導体モジュール
JP2020022216A (ja) 2018-07-30 2020-02-06 三菱電機株式会社 電力変換装置
WO2020110170A1 (ja) 2018-11-26 2020-06-04 三菱電機株式会社 半導体パッケージ、その製造方法、及び、半導体装置

Also Published As

Publication number Publication date
CN114188294A (zh) 2022-03-15
DE102021120891B4 (de) 2024-05-08
US11508698B2 (en) 2022-11-22
JP2022048623A (ja) 2022-03-28
US20220084990A1 (en) 2022-03-17
DE102021120891A1 (de) 2022-03-17

Similar Documents

Publication Publication Date Title
KR100430772B1 (ko) 반도체장치
US7271477B2 (en) Power semiconductor device package
JP5413471B2 (ja) 電力用半導体装置
JP5272191B2 (ja) 半導体装置および半導体装置の製造方法
KR100566046B1 (ko) 파워 반도체장치
US9966344B2 (en) Semiconductor device with separated main terminals
US9613890B2 (en) Semiconductor device
JP5029078B2 (ja) 電力用半導体装置
JP5930070B2 (ja) 半導体装置
US20230352453A1 (en) Semiconductor module
KR102586458B1 (ko) 반도체 서브 어셈블리 및 반도체 파워 모듈
JP4471600B2 (ja) 回路装置
JP7337034B2 (ja) 半導体パッケージおよび半導体装置
JP7491043B2 (ja) 半導体モジュール
JP7396118B2 (ja) 半導体モジュール
US20230087499A1 (en) Semiconductor unit and semiconductor device
CN219917172U (zh) 电子器件和功率电子模块
JP7494613B2 (ja) 半導体装置
WO2023140046A1 (ja) 半導体装置
US20230420341A1 (en) Power module for half-bridge circuit with scalable architecture and improved layout
US20230275006A1 (en) Semiconductor apparatus
JP4246598B2 (ja) 電力用半導体装置
CN115411008A (zh) 开关装置、半导体装置及开关装置的制造方法
JP2022143169A (ja) 半導体装置
JP2022191879A (ja) 半導体装置

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221003

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230714

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230725

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230822

R150 Certificate of patent or registration of utility model

Ref document number: 7337034

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150