TWI489563B - 預先模鑄成形且封裝粘著的多晶粒半導體封裝 - Google Patents

預先模鑄成形且封裝粘著的多晶粒半導體封裝 Download PDF

Info

Publication number
TWI489563B
TWI489563B TW098136740A TW98136740A TWI489563B TW I489563 B TWI489563 B TW I489563B TW 098136740 A TW098136740 A TW 098136740A TW 98136740 A TW98136740 A TW 98136740A TW I489563 B TWI489563 B TW I489563B
Authority
TW
Taiwan
Prior art keywords
die
lead frame
semiconductor package
molded
gap
Prior art date
Application number
TW098136740A
Other languages
English (en)
Other versions
TW201029076A (en
Inventor
Armand Vincent C Jereza
Original Assignee
Fairchild Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor filed Critical Fairchild Semiconductor
Publication of TW201029076A publication Critical patent/TW201029076A/zh
Application granted granted Critical
Publication of TWI489563B publication Critical patent/TWI489563B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

預先模鑄成形且封裝粘著的多晶粒半導體封裝
本申請案大體而言係關於半導體裝置及用於製造此等裝置之方法。更具體言之，本申請案描述含有多個晶粒之半導體封裝及用於製造此等封裝之方法。
半導體封裝在此項技術中係熟知的。通常，此等封裝可包括一或多個半導體裝置(諸如積體電路(「IC」)晶粒)，其可連接至在引線框架中於中央形成的晶粒襯墊。在一些狀況下，接合導線(bond wire)將該IC晶粒電連接至一系列端子(terminal)，該等端子充當與外部裝置(諸如，印刷電路板(「PCB」))之電連接。可使用囊封材料來覆蓋該等接合導線、該IC晶粒、該等端子及/或其他組件以形成該半導體封裝之外部。該等端子之一部分及可能該晶粒襯墊之一部分可自該囊封材料暴露於外部。以此方式，可保護晶粒免受環境危險-諸如，潮濕、污染、腐蝕及機械衝擊-同時電連接且機械連接至在該半導體封裝外部的預期裝置。
在該半導體封裝形成後，其通常用於日漸增長之電子應用種類之中，諸如，磁碟機、USB控制器、攜帶型電腦裝置、行動電話等等。取決於晶粒及電子應用，該半導體封裝可高度微型化且可需要盡可能小。
在許多情形下，每一半導體封裝僅含有一含有一IC裝置之單個晶粒。因此，每一半導體封裝之功能性通常限制於晶粒所含之彼特定IC裝置之功能。
本申請案係關於含有多個晶粒之半導體封裝及用於製造此等封裝之方法。該等半導體封裝含有一具有多個晶粒之引線框架且亦含有一連接該等晶粒之單個預先模鑄成形之封夾件(clip)。該預先模鑄成形之封裝將源極晶粒及閘極晶粒之可焊接襯墊經由間隙部連接至該引線框架之源極及閘極。該等晶粒上及該等間隙部上之該等可焊接襯墊提供一大體上平坦之表面，該預先模鑄成形之封裝附著至該表面。在與導線接合件(wirebonding)連接相比時，該組態增加互連之橫截面積，藉此改善該半導體封裝之導通電阻(RDSon )及熱效能。相對於使用導線接合件連接之類似半導體封裝而言，該組態亦降低成本。
下文描述提供特定細節以便提供徹底理解。然而，熟悉此項技術者將理解可在不使用此等特定細節之情況下實施並使用該等半導體封裝及使用該等封裝之相關聯方法。實際上，該等裝置及相關聯方法可藉由修改所說明裝置及相關聯方法投入實踐且可結合習知用於此工業中之任何其他設備及技術來使用。舉例而言，雖然下文描述著重於用於製造IC工業中之半導體裝置的方法，但其可用於且適用於其他電子裝置，如光電裝置、太陽能電池、微機電系統(MEMS)結構、照明控制器、電源供應器及放大器。
含有由預先模鑄成形之封夾件連接之多個晶粒之半導體封裝及用於製造此等封裝之方法的一些實施例展示於諸圖中。在一些實施例中，該等半導體裝置係以四方扁平無引線(QFN)半導體封裝之形式提供。在其他實施例中，該等半導體裝置係以電源四方扁平無引線(PQFN)半導體封裝之形式提供。
該等半導體封裝可使用本文中所提供說明並描述之結構的任何方法製造。在一些實施例中，用於製造一半導體封裝之方法提供一用於產生一預先模鑄成形之封夾件的第一引線框架。如第1圖中所圖示，如此項技術中已知，一第一引線框架10藉由金屬衝壓或蝕刻以產生一框架12來製造，該框架12含有具有所要形狀之多個面板14，該等面板14由連桿16彼此連接。該引線框架10可由此項技術中已知之任何導電材料製成，該材料包括Cu、Cu合金、Ni-Pd、Ni-Pd-Au或其組合。在一些實施例中，該第一引線框架10包含Cu。
第1圖描繪一具有六個獨立面板14之引線框架10。每對面板可與在該等面板之間的連桿16分離且用作如本文所描述之預先模鑄成形之封夾件。因此，每一引線框架10可用於製造3個預先模鑄成形之封夾件，其中之每一者係由一對面板14製成。該引線框架10可在需要時以少如2個面板(以製造1個預先模鑄成形之封夾件)及多達多個面板(以製造一半數目的預先模鑄成形之封夾件)來組態，其限制條件為該引線框架上之總尺寸將適合於模鑄成形設備。
接著，如第2圖中所展示，該引線框架10可藉由一模鑄成形材料18囊封。該模鑄成形材料18藉由任何已知囊封製程(包括灌封、轉移模鑄成形或注入)在該等面板之側面及該等面板之底表面之部分的周圍形成。含有該等面板14之所得部分模鑄成形之引線框架20描繪於第2圖中。面板14在模鑄成形之引線框架20內仍經由連桿16彼此連接。
該模鑄成形之引線框架20可接著分離為描繪於第3圖(俯視圖)及第4圖(仰視圖)中之個別模鑄成形之封夾件引線框架25(或預先模鑄成形之封夾件)。可使用此項技術中已知之任何製程(包括沖切成型(punch singulation)製程或鋸切成型(saw singulation)製程)執行此分離。在此製程期間，移除連接面板14之連桿16以使得僅保留面板14。第4圖圖示在一些實施例中，該囊封製程僅覆蓋該等面板之下表面之部分。未經囊封之該等面板之底部上的暴露表面15將用作互連表面。
接著，可提供半導體封裝之引線框架(或基礎引線框架)。在一些實施例中，如第5圖中所描繪，引線框架30藉由3個部分(晶粒黏接焊盤或DAP)34、36及38組態，該等晶粒將位於該3個部分上。如此項技術中已知，可例如藉由金屬衝壓或蝕刻製造該引線框架30。引線框架30可由此項技術中已知之導電材料製成，該材料包括Cu、Cu合金、Ni-Pd、Ni-Pd-Au或其組合。在一些實施例中，引線框架30包含Cu。
引線框架30可經組態以最小化此等晶粒所需之頂層特徵結構結構之長度，該等晶粒稍後將置放於引線框架30上。藉由最小化該頂層特徵結構結構之長度，可增加DAP之長度。在一些組態中，該頂層特徵結構結構經組態為一折疊間隙部(standoff)32，如第5圖中所描繪。雖然第5圖描繪兩個間隙部特徵結構結構，但該等半導體封裝可含有一個間隙部且甚至可含有3個或3個以上間隙部特徵結構結構。
此特徵結構結構之特寫特徵結構結構展示間隙部32在一垂直方向上自引線框架30之側面延伸。該間隙部可具有與本文中所描述之其功能相符的任何長度及寬度。在一些實施例中，該間隙部可具有約40密耳之長度及約5密耳之寬度。
該間隙部可經組態以相對於該引線框架或DAP之鄰近邊緣偏置或齊平。該間隙部經組態成齊平之實施例在第5圖中描繪為間隙部32。該間隙部經組態成偏置之實施例在第5圖中描繪為間隙部31。
由該間隙部32添加之額外長度(相對於引線框架30之基座而言)取決於該等晶粒之厚度，因為間隙部32之上表面將大體上與將附著至DAP之晶粒之上表面齊平。
間隙部特徵結構與習知頂層特徵結構之比較描繪於第6A圖與第6B圖中。一個習知頂層特徵展示於第6A圖之頂部且包含一向上延伸之短區段35及一向引線框架之鄰近區段延伸之長區段37。由於此習知組態，該習知頂層特徵需要引線框架之一區段(通常為DAP)至下一區段之間的距離為約1.195mm。然而，使用該折疊間隙部組態允許此距離縮短至約0.5mm。但是，在其他實施例中，該間隙部可藉由一階梯特徵結構39組態，如第6B圖中所描繪。
如第7圖中所展示，一旦已形成具有DAP 34、36及38之引線框架30，則接著將晶粒42、44及46提供於此引線框架30上。在諸圖中所描繪之實施例中，使用三個晶粒。但在其他實施例中，可使用2個晶粒或甚至4個或4個以上晶粒。該等晶粒可為此項技術中已知之任何半導體晶粒，包括由矽或任何其他已知半導電材料製成的晶粒。
在一些實施例中，該等晶粒可含有此項技術中已知之任何IC裝置。任何給定晶粒中之IC裝置可與任何其他晶粒中所使用之IC裝置相同或不同。該等IC裝置之一些非限制實例包括音訊放大器、LDO、邏輯驅動器、信號交換器或其組合。
在其他實施例中，該等晶粒亦可含有一離散裝置。任 何給定晶粒中之該離散裝置可與任何其他晶粒中所使用之離散裝置相同或不同。可使用此項技術中已知之任何離散裝置，包括二極體及/或電晶體。該等離散裝置之實例包括曾納二極體(zener diode)、肖特基二極體(schottky diode)、小信號二極體、雙極接面電晶體「BJT」、金屬氧化物半導體場效電晶體(「MOSFET」)、絕緣閘極雙極電晶體(「IGBT」)、絕緣閘極場效電晶體(「IGFET」)或其組合。在一些實施例中，離散裝置包含一MOSFET裝置。
在又一些其他實施例中，該等晶粒亦可含有一被動裝置。任何給定晶粒中之該被動裝置可與任何其他晶粒中所使用之被動裝置相同或不同。可使用此項技術中已知之任何被動裝置，包括電容器、電感器、電阻器、濾波器或其組合。
在又一些其他實施例中，該等晶粒可含有IC裝置、離散裝置及被動裝置之任何組合。舉例而言，在諸圖中所展示之實施例中，晶粒42含有一MOSFET，晶粒44含有一MOSFET且晶粒46含有一控制IC裝置。
可使用任何已知製程製造具有IC裝置、被動裝置及/或離散裝置的晶粒。在一些實施例中，可獨立製造三個晶粒。但在其他實施例中，可大體上同時製造所有該等晶粒。
該等晶粒可使用任何已知製程附著至引線框架30。在一些實施例中，此製程包括使用焊料凸塊法之覆晶製程，其可包括使用焊料凸塊、球、栓及其組合以及焊膏，繼之以固化及回焊製程。在其他實施例中，附著製程包括使用導電粘著劑之覆晶製程。該導電粘著劑可為例如導電環氧樹脂、導電膜、可絲網印刷之焊膏或焊接材料，諸如含引線之焊料或無引線之焊料。
接著，預先模鑄成形之封夾件25附著至所要晶粒(亦即，晶粒42及晶粒44)。可使用此項技術中已知之任何製程進行此附著。在一些實施例中，附著製程藉由在將附著預先模鑄成形之封夾件之位置上提供任何已知焊膏50開始。因此，如第8圖中所展示，焊膏50提供於晶粒42、晶粒44之上表面及兩個間隙部25之上表面上。可使用此項技術中已知之任何方法提供焊膏50。
預先模鑄成形之封夾件25之底表面接著使用焊膏50附著至該等晶粒。預先模鑄成形之封夾件25經附著以使得預先模鑄成形之封夾件25之底表面上之所暴露連接被連接至該等晶粒中所含之不同裝置的所要部分。在一些實施例中，預先模鑄成形之封夾件25附著至晶粒以使得晶粒42之源極經由該引線框架電連接至晶粒44之汲極。在一些實施例中，該預先模鑄成形之封夾件可附著至所有3個晶粒。
在上文描述之方法中，在引線框架30之前製造預先模鑄成形之封夾件25。但是，在其他實施例中，可大體與引線框架30同時或甚至在引線框架30之後而非在其之前製造預先模鑄成形之封夾件25。封夾件引線框架已附著至所要晶粒之後的所得結構描繪於第9圖中。
若需要，則可在不同晶粒之間及/或在晶粒與引線框架30之間進行額外連接。在一些實施例中，可藉由此項技術中已知之任何導線接合件製程進行此(等)額外連接。作為導線接合件之實例，晶粒之所要部分可在晶粒之所要位置上及引線框架之所要位置上具備接觸襯墊。此後，自其他晶粒及/或引線框架30上之所要連接點的接觸襯墊形成導線接合件55以形成電連接。導線接合件55可由此項技術中已知之任何導電材料(包括Au或Cu)且使用此項技術中已知之任何製程製成。已形成導線接合件55之後的所得結構圖示於第10圖中。
接著，所得結構經囊封以形成完成之半導體封裝100。如第11圖中所描繪，該等晶粒、該預先模鑄成形之封夾件25、該等導線接合件50及該引線框架30之大部分可囊封於此項技術中已知之任何模鑄成形材料130中。第12圖描繪以透明材料囊封(出於檢視內部組件之目的)。在一些實施例中，模鑄成形材料130可包含環氧樹脂模鑄成形化合物、熱固性樹脂、熱塑性材料或灌封材料。在其他實施例中，模鑄成形材料包含環氧樹脂模鑄成形化合物。在該囊封製程期間，引線框架30之特定側面未經囊封，藉此形成半導體封裝100之端子105。
由此製程形成之半導體封裝含有兩個(或兩個以上)晶粒，該等晶粒具有經由單個預先模鑄成形之封夾件彼此連接之裝置。該預先模鑄成形之封夾件25藉由使用在定位該等晶粒之該引線框架上的間隙部保持大體上平坦。當與使用習知線粘著相比時，該預先模鑄成形之封夾件增加互連之橫截面積。藉由增加之橫截面積，該半導體封裝之導通電阻(RDSon )及熱效能得以改善。在一些組態中，一類型之習知半導體封裝使用8根Cu線連接該等晶粒。因為該等線具有約2密耳之直徑，所以互連之橫截面積為約25平方密耳。但將預先模鑄成形之封裝用於相同互連(但具有長度為約40密耳且寬度為約5密耳的折疊間隙部)提供約200平方密耳之橫截面積，進而產生約700%之增加。
除任何先前指示之修改外，可由熟悉此項技術者設計許多其他變化及替代配置而不背離本說明書之精神與範疇，且隨附申請專利範圍欲涵蓋此等修改及配置。因此，雖然已在上文結合當前被視為最實用且較佳之態樣之內容以特定性及細節描述資訊，但對於一般熟悉此項技術者而言將顯而易見可進行包括但不限於形式、功能、操作方式及用途的許多修改，而不背離本文中所闡述之原理及概念。且，如本文中所使用，實例意欲僅為說明性的且不應視為以任何方式加以限制。
10．．．第一引線框架
12．．．框架
14．．．面板
15．．．暴露表面
16．．．連桿
18．．．模鑄成形材料
20．．．模鑄成形之引線框架
25．．．模鑄成形之封裝引線框架/預先模鑄成形之封夾件
30．．．引線框架
31．．．間隙部
32．．．間隙部/折疊間隙部
34．．．DAP
35．．．短區段
36．．．DAP
37．．．長區段
38．．．DAP
39．．．階梯特徵
42．．．晶粒
44．．．晶粒
46．．．晶粒
50．．．焊膏
100．．．完成之半導體封裝/半導體封裝
105．．．端子
130．．．模鑄成形材料
可根據諸圖較佳理解上文描述，其中
第1圖展示用於製造一半導體封裝之一面板化預先模鑄成形之封夾件的一些實施例；
第2圖展示用於製造一半導體封裝之一面板化模鑄成形之封夾件的一些實施例；
第3圖及第4圖分別展示用於一半導體封裝中之一預先模鑄成形之封夾件之一些實施例的俯視圖及仰視圖；及
第5圖描繪用於一半導體封裝中之引線框架之一些實施例以及一間隙部特徵結構之特寫；
第6A圖及第6B圖展示一些實施例中之間隙部特徵結構與習知頂層特徵結構之間的比較；
第7圖描繪一具有用於一半導體封裝中之多個晶粒之引線框架的一些實施例；
第8圖描繪塗覆至晶粒及間隙部之焊膏之一些實施例；
第9圖描繪可用於一半導體封裝中之預先模鑄成形之封夾件的一些實施例；
第10圖描繪可用於一半導體封裝中之導線接合件的一些實施例；
第11圖及第12圖展示一經囊封之半導體封裝的一些實施例。
諸圖圖示含有多個晶粒之半導體封裝及用於製造此等封裝之方法之特定態樣。諸圖與上文描述一起說明並解釋該等方法之原理及經由此等方法產生之結構。在諸圖式中，為了清楚起見，誇示層及區域之厚度。亦應理解，當一層、組件或基板被稱為在另一層、組件或基板「上」時，其可直接在該另一層、組件或基板上，或亦可存在介入層。不同圖式中之相同參考數字表示相同元件，且因此將不重複其描述。
25．．．模鑄成形之封裝引線框架/預先模鑄成形之封夾件
46．．．晶粒
100．．．完成之半導體封裝/半導體封裝
105．．．端子
130．．．模鑄成形材料

Claims (29)

  1. 一種半導體封裝，其包含：一第一晶粒之一底表面，其連接至一引線框架之一上表面；一第二晶粒之一底表面，其連接至該引線框架之一上表面；及一預先模鑄成形之封夾件(clip)，其連接至該第一晶粒之一上表面、該第二晶粒之一上表面、且連接至形成於該引線框架之一上表面上的一間隙部(standoff)。
  2. 如申請專利範圍第1項之半導體封裝，其中該預先模鑄成形之封夾件包含一對部分囊封之面板。
  3. 如申請專利範圍第1項之半導體封裝，其中該引線框架之該上表面含有複數個間隙部，該預先模鑄成形之封夾件之底表面連接至該複數個間隙部。
  4. 如申請專利範圍第3項之半導體封裝，其中該等間隙部形成於該引線框架之閘極及源極引線柱上。
  5. 如申請專利範圍第1項之半導體封裝，其進一步包含一第三晶粒，其中該第三晶粒之底表面連接至一引線框架之一上表面。
  6. 如申請專利範圍第1項之半導體封裝，其中該第三晶粒藉由導線接合件(wirebonding)連接至該第一晶粒及該第二晶粒。
  7. 如申請專利範圍第6項之半導體封裝，其中該第一晶粒、該第二晶粒、該第三晶粒或該等晶粒之一組合藉由導線接合件連接至該引線框架。
  8. 如申請專利範圍第1項之半導體封裝，其進一步包含一模鑄成形材料，其囊封該第一晶粒、該第二晶粒及該預先模鑄成形之封裝。
  9. 如申請專利範圍第8項之半導體封裝，其中該模鑄成形材料亦囊封該引線框架，但除該引線框架之一側面之一部分之外。
  10. 如申請專利範圍第1項之半導體封裝，其中該間隙部可具有一折疊組態、一偏置組態或一階梯組態。
  11. 一種半導體封裝，其包含：一第一晶粒之一底表面，其連接至一引線框架之一上表面；一第二晶粒之一底表面，其連接至該引線框架之一上表面；及 一預先模鑄成形之封夾件，其連接至該第一晶粒之一上表面、該第二晶粒之一上表面、且連接至形成於該引線框架之一上表面上的複數個間隙部。
  12. 如申請專利範圍第11項之半導體封裝，其中該預先模鑄成形之封夾件包含一對部分囊封之面板。
  13. 如申請專利範圍第11項之半導體封裝，其中該等間隙部形成於該引線框架之閘極及源極引線柱上。
  14. 如申請專利範圍第11項之半導體封裝，其進一步包含一第三晶粒，其中該第三晶粒之底表面連接至一引線框架之一上表面。
  15. 如申請專利範圍第14項之半導體封裝，其中該第三晶粒藉由導線接合件連接至該第一晶粒及該第二晶粒。
  16. 如申請專利範圍第15項之半導體封裝，其中該第一晶粒、該第二晶粒、該第三晶粒或此等晶粒之一組合藉由導線接合件連接至該引線框架。
  17. 如申請專利範圍第11項之半導體封裝，其進一步包含一模鑄成形材料，其囊封該第一晶粒、該第二晶粒及該預先模鑄成形之封夾件。
  18. 如申請專利範圍第17項之半導體封裝，其中該模鑄成形材料亦囊封該引線框架，但除該引線框架之一側面之一部分之外，其作為該半導體封裝之一端子操作。
  19. 如申請專利範圍第17項之半導體封裝，其中該間隙部可具有一折疊組態、一偏置組態或一階梯組態。
  20. 一種用於製造半導體封裝之方法，其包含以下步驟：提供一引線框架，其具有含有一間隙部的一上表面；將一第一晶粒之一底表面連接至該引線框架之一上表面；將一第二晶粒之一底表面連接至該引線框架之一上表面；及將一預先模鑄成形之封夾件連接至該第一晶粒之一上表面、該第二晶粒之一上表面、且連接至該間隙部。
  21. 如申請專利範圍第20項之方法，其中該預先模鑄成形之封夾件包含一對部分囊封之面板。
  22. 如申請專利範圍第20項之方法，其中該引線框架之該上表面含有複數個間隙部，該預先模鑄成形之封夾件之底表面連接至該複數個間隙部。
  23. 如申請專利範圍第20項之方法，其進一步包含以下步驟：將一第三晶粒之一底表面連接至一引線框架之一上表面。
  24. 如申請專利範圍第23項之方法，其進一步包含以下步驟：藉由導線接合件將該第三晶粒連接至該第一晶粒及該第二晶粒。
  25. 如申請專利範圍第20項之方法，其進一步包含以下步驟：提供一模鑄成形材料以囊封該第一晶粒、該第二晶粒、及該預先模鑄成形之封裝。
  26. 如申請專利範圍第20項之方法，其中該模鑄成形材料亦囊封該引線框架，但除該引線框架之一側面之一部分之外，其作為該半導體封裝之一端子操作。
  27. 如申請專利範圍第20項之方法，其中該間隙部可具有一折疊組態、一偏置組態或一階梯組態。
  28. 一種用於製造半導體封裝之方法，其包含以下步驟：提供一引線框架，其具有一含有一間隙部的上表面；將一第一晶粒之一底表面連接至該引線框架之一上表面以使得該第一晶粒之上表面大體上與該間隙部齊平；將一第二晶粒之一底表面連接至該引線框架之一上表面 以使得該第二晶粒之上表面大體上與該間隙部齊平；自一獨立引線框架形成一預先模鑄成形之封夾件；將一預先模鑄成形之封夾件連接至該第一晶粒之一上表面、該第二晶粒之一上表面、且連接至該間隙部；及提供一模鑄成形材料以囊封該第一晶粒、該第二晶粒、該預先模鑄成形之封夾件及該引線框架，但除該引線框架之一側面之一部分之外，其作為該半導體封裝之一端子操作。
  29. 如申請專利範圍第28項之方法，其中該預先模鑄成形之封夾件包含一對部分囊封之面板。
TW098136740A 2008-10-31 2009-10-29 預先模鑄成形且封裝粘著的多晶粒半導體封裝 TWI489563B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/262,486 US7898067B2 (en) 2008-10-31 2008-10-31 Pre-molded, clip-bonded multi-die semiconductor package

Publications (2)

Publication Number Publication Date
TW201029076A TW201029076A (en) 2010-08-01
TWI489563B true TWI489563B (zh) 2015-06-21

Family

ID=42129516

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098136740A TWI489563B (zh) 2008-10-31 2009-10-29 預先模鑄成形且封裝粘著的多晶粒半導體封裝

Country Status (5)

Country Link
US (1) US7898067B2 (zh)
KR (1) KR101189001B1 (zh)
CN (1) CN102217062B (zh)
TW (1) TWI489563B (zh)
WO (1) WO2010051211A2 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768105B2 (en) 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US8664038B2 (en) * 2008-12-04 2014-03-04 Stats Chippac Ltd. Integrated circuit packaging system with stacked paddle and method of manufacture thereof
US20100164078A1 (en) * 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
US8436429B2 (en) * 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method
CN102829298B (zh) * 2012-08-08 2015-06-17 张小伟 一种保健型电脑显示器万向升降仪
KR101977994B1 (ko) 2013-06-28 2019-08-29 매그나칩 반도체 유한회사 반도체 패키지
US9287227B2 (en) 2013-11-29 2016-03-15 STMicroelectronics (Shenzhen) R&D Co. Ltd Electronic device with first and second contact pads and related methods
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing
US9480161B2 (en) 2014-01-17 2016-10-25 Freescale Semiconductor, Inc. Thin low profile strip dual in-line memory module
US9837380B2 (en) 2014-01-28 2017-12-05 Infineon Technologies Austria Ag Semiconductor device having multiple contact clips
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US11088046B2 (en) 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
US11562948B2 (en) * 2019-11-04 2023-01-24 Mediatek Inc. Semiconductor package having step cut sawn into molding compound along perimeter of the semiconductor package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277804A (ja) * 1995-06-15 2000-10-06 Nichia Chem Ind Ltd 窒化物半導体素子の製造方法及び窒化物半導体素子、並びに発光素子
US20040079967A1 (en) * 2002-10-24 2004-04-29 Yukio Shakuda Semiconductor light emitting device
CN1649146A (zh) * 2004-01-28 2005-08-03 株式会社瑞萨科技 半导体器件

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496356A (ja) * 1990-08-13 1992-03-27 Nec Corp 樹脂封止型半導体装置用リードフレーム
US6093961A (en) * 1999-02-24 2000-07-25 Chip Coolers, Inc. Heat sink assembly manufactured of thermally conductive polymer material with insert molded metal attachment
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6784540B2 (en) * 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7135761B2 (en) * 2004-09-16 2006-11-14 Semiconductor Components Industries, L.Lc Robust power semiconductor package
DE102004063851B4 (de) 2004-12-30 2020-01-09 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Schaltung
US20070057368A1 (en) * 2005-09-13 2007-03-15 Yueh-Se Ho Semiconductor package having plate interconnections
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
TW200836315A (en) 2007-02-16 2008-09-01 Richtek Techohnology Corp Electronic package structure and method thereof
JP2009182022A (ja) 2008-01-29 2009-08-13 Renesas Technology Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277804A (ja) * 1995-06-15 2000-10-06 Nichia Chem Ind Ltd 窒化物半導体素子の製造方法及び窒化物半導体素子、並びに発光素子
US20040079967A1 (en) * 2002-10-24 2004-04-29 Yukio Shakuda Semiconductor light emitting device
CN1649146A (zh) * 2004-01-28 2005-08-03 株式会社瑞萨科技 半导体器件

Also Published As

Publication number Publication date
WO2010051211A3 (en) 2010-07-22
CN102217062B (zh) 2014-10-29
WO2010051211A2 (en) 2010-05-06
KR101189001B1 (ko) 2012-10-09
US7898067B2 (en) 2011-03-01
KR20110074570A (ko) 2011-06-30
CN102217062A (zh) 2011-10-12
TW201029076A (en) 2010-08-01
US20100109134A1 (en) 2010-05-06

Similar Documents

Publication Publication Date Title
TWI489563B (zh) 預先模鑄成形且封裝粘著的多晶粒半導體封裝
US9824949B2 (en) Packaging solutions for devices and systems comprising lateral GaN power transistors
US8389336B2 (en) Semiconductor device package and method of assembly thereof
US20110244633A1 (en) Package assembly for semiconductor devices
US8198132B2 (en) Isolated stacked die semiconductor packages
JP5227501B2 (ja) スタックダイパッケージ及びそれを製造する方法
US20090261462A1 (en) Semiconductor package with stacked die assembly
US20050236702A1 (en) Semiconductor package for a large die
US20090189261A1 (en) Ultra-Thin Semiconductor Package
US20240096759A1 (en) Smds integration on qfn by 3d stacked solution
KR20140032923A (ko) 와이어리스 모듈
TWI485819B (zh) 封裝結構及其製造方法
US20070087471A1 (en) Semiconductor package and method of manufacturing the same
US7642638B2 (en) Inverted lead frame in substrate
US20200243428A1 (en) Packaged multichip module with conductive connectors
US8072051B2 (en) Folded lands and vias for multichip semiconductor packages
US10468319B2 (en) Low-profile electronic package
US8268671B2 (en) Semiconductor system-in-package and methods for making the same
US9870986B2 (en) Single or multi chip module package and related methods
US7843048B2 (en) Multi-chip discrete devices in semiconductor packages