JP5966921B2 - 半導体モジュールの製造方法 - Google Patents
半導体モジュールの製造方法 Download PDFInfo
- Publication number
- JP5966921B2 JP5966921B2 JP2012287305A JP2012287305A JP5966921B2 JP 5966921 B2 JP5966921 B2 JP 5966921B2 JP 2012287305 A JP2012287305 A JP 2012287305A JP 2012287305 A JP2012287305 A JP 2012287305A JP 5966921 B2 JP5966921 B2 JP 5966921B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor chip
- semiconductor
- control
- solder material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Description
3:第1表面電極
4:第2表面電極
5:制御パッド
6:樹脂
7、7a、7b:半田材
7c:高温溶融半田材
7d:低温溶融半田材
9:ボンディングワイヤ
10、10a、10b、10c、10d、10e、10f:半導体モジュール
12:積層ユニット
13a:出力電極
13b:第1電極
13c:第2電極
14:制御電極
15:冷却プレート
41:ボンディングツール
80:カーボン治具
Claims (1)
- 平板型の第1及び第2半導体チップが樹脂で封止されているとともに、樹脂内部にて、いずれかの半導体チップと電気的に接続している第1電極と第2電極と出力電極と第1制御電極と第2制御電極が樹脂から露出している半導体モジュールの製造方法であって、
夫々の半導体チップは、第1面に第1表面電極と制御パッドが露出しているとともに、第1面とは反対側の第2面に第2表面電極が露出しており、
樹脂内にて、前記第1電極、前記第1半導体チップ、前記出力電極、前記第2半導体チップ、及び、前記第2電極がこの順序で積層しており、
前記第1電極と前記第1半導体チップの前記第1表面電極が対向するとともに電気的に接続し、前記第1半導体チップの前記第2表面電極が前記出力電極と対向するとともに電気的に接続し、前記第2半導体チップの前記第1表面電極が前記出力電極と対向するとともに電気的に接続し、前記第2半導体チップの前記第2表面電極と前記第2電極が対向するとともに電気的に接続しており、
前記第1制御電極が前記第1半導体チップの制御パッドにボンディングワイヤを介して電気的に接続しており、前記第2制御電極が前記第2半導体チップの制御パッドにボンディングワイヤを介して電気的に接続しており、
前記第1及び第2電極、前記出力電極、前記第1及び第2制御電極のうち、前記第1半導体チップの制御パッドが向いている側に位置する電極が、積層方向から見て前記第1半導体チップの制御パッドと重ならないように配置されており、
前記第1及び第2電極、前記出力電極、前記第1及び第2制御電極のうち、前記第2半導体チップの制御パッドが向いている側に位置する電極が、積層方向から見て前記第2半導体チップの制御パッドと重ならないように配置されており、
当該製造方法は、
前記第1電極、前記第1半導体チップ、前記出力電極、前記第2半導体チップ、前記第2電極を、間に半田材を挟んで上からこの順序で鉛直方向に重ねて積層体を作る工程と、
前記積層体を加熱して前記半田材を溶融させる工程と、
前記積層体を冷却して前記半田材を固着させる工程と、を備えるとともに、
前記積層体を作る工程に先立って、前記第1電極と前記出力電極の少なくとも一方の電極と、重ねたときに前記少なくとも一方の電極の直下に位置する半田材を、当該少なくとも一方の電極を裏返した上から接合させるプレ接合工程と、
を備えていることを特徴とする半導体モジュールの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012287305A JP5966921B2 (ja) | 2012-12-28 | 2012-12-28 | 半導体モジュールの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012287305A JP5966921B2 (ja) | 2012-12-28 | 2012-12-28 | 半導体モジュールの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014130894A JP2014130894A (ja) | 2014-07-10 |
JP5966921B2 true JP5966921B2 (ja) | 2016-08-10 |
Family
ID=51409054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012287305A Active JP5966921B2 (ja) | 2012-12-28 | 2012-12-28 | 半導体モジュールの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5966921B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6409733B2 (ja) * | 2015-10-16 | 2018-10-24 | トヨタ自動車株式会社 | 半導体装置 |
WO2017175686A1 (ja) * | 2016-04-04 | 2017-10-12 | ローム株式会社 | パワーモジュールおよびその製造方法 |
CN110164858B (zh) * | 2018-02-16 | 2023-05-05 | 株式会社电装 | 半导体器件 |
JP7139881B2 (ja) * | 2018-02-16 | 2022-09-21 | 株式会社デンソー | 半導体装置 |
JP7294403B2 (ja) * | 2019-03-12 | 2023-06-20 | 住友電気工業株式会社 | 半導体装置 |
JP7172847B2 (ja) | 2019-05-15 | 2022-11-16 | 株式会社デンソー | 半導体装置 |
JP7518789B2 (ja) | 2021-03-17 | 2024-07-18 | 株式会社東芝 | 半導体装置 |
WO2023090072A1 (ja) * | 2021-11-16 | 2023-05-25 | ローム株式会社 | 半導体装置 |
WO2023188016A1 (ja) * | 2022-03-29 | 2023-10-05 | 三菱電機株式会社 | 半導体モジュールおよび電力変換装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4323299B2 (ja) * | 2003-12-03 | 2009-09-02 | 三菱電機株式会社 | 半導体装置 |
JP2005217072A (ja) * | 2004-01-28 | 2005-08-11 | Renesas Technology Corp | 半導体装置 |
JP4438489B2 (ja) * | 2004-04-13 | 2010-03-24 | 富士電機システムズ株式会社 | 半導体装置 |
JP4924920B2 (ja) * | 2006-06-28 | 2012-04-25 | 三菱マテリアル株式会社 | Au−Sn合金はんだペーストを用いて素子の接合面全面を基板に接合する方法 |
US7999369B2 (en) * | 2006-08-29 | 2011-08-16 | Denso Corporation | Power electronic package having two substrates with multiple semiconductor chips and electronic components |
JP4985009B2 (ja) * | 2007-03-20 | 2012-07-25 | トヨタ自動車株式会社 | 半導体装置とその半導体装置をパッケージする方法 |
JP5136343B2 (ja) * | 2008-10-02 | 2013-02-06 | 三菱電機株式会社 | 半導体装置 |
JP5271861B2 (ja) * | 2009-10-07 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN102593108B (zh) * | 2011-01-18 | 2014-08-20 | 台达电子工业股份有限公司 | 功率半导体封装结构及其制造方法 |
US20120200281A1 (en) * | 2011-02-07 | 2012-08-09 | Texas Instruments Incorporated | Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing |
JP5578326B2 (ja) * | 2011-03-29 | 2014-08-27 | 日立金属株式会社 | リード部品及びその製造方法、並びに半導体パッケージ |
CN103534805B (zh) * | 2011-05-16 | 2016-08-24 | 丰田自动车株式会社 | 功率模块 |
-
2012
- 2012-12-28 JP JP2012287305A patent/JP5966921B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014130894A (ja) | 2014-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5966921B2 (ja) | 半導体モジュールの製造方法 | |
JP6750514B2 (ja) | 半導体装置 | |
JP4973059B2 (ja) | 半導体装置及び電力変換装置 | |
JP5287359B2 (ja) | 半導体モジュール | |
JP2011114176A (ja) | パワー半導体装置 | |
JPWO2019098368A1 (ja) | 半導体装置 | |
US20150028466A1 (en) | Semiconductor device and manufacturing method thereof | |
JP6689708B2 (ja) | 電子装置 | |
US8710644B2 (en) | Semiconductor unit having a power semiconductor and semiconductor apparatus using the same | |
JP2012074648A (ja) | パワー半導体モジュール及びその製造方法 | |
JP4885046B2 (ja) | 電力用半導体モジュール | |
WO2005119896A1 (ja) | インバータ装置 | |
TW201921613A (zh) | 電子裝置 | |
JP5811072B2 (ja) | パワーモジュール | |
US20230130647A1 (en) | Semiconductor device | |
JP4942629B2 (ja) | 電力用半導体モジュール | |
JP2012074730A (ja) | 電力用半導体モジュール | |
JP5081951B2 (ja) | インバータ装置 | |
JP2019068110A (ja) | パワーモジュール | |
JP2020150020A (ja) | 半導体装置 | |
WO2020184051A1 (ja) | 半導体装置 | |
US9698076B1 (en) | Metal slugs for double-sided cooling of power module | |
KR20210076469A (ko) | 파워 모듈 및 그 제조 방법 | |
JP7074046B2 (ja) | 半導体装置とその製造方法 | |
JP6447914B2 (ja) | パワーモジュールの直流側配線基板及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141222 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150924 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20151013 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151210 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160607 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160620 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5966921 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |