CN101436584B - 层叠半导体封装 - Google Patents

层叠半导体封装 Download PDF

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CN101436584B
CN101436584B CN2008100029517A CN200810002951A CN101436584B CN 101436584 B CN101436584 B CN 101436584B CN 2008100029517 A CN2008100029517 A CN 2008100029517A CN 200810002951 A CN200810002951 A CN 200810002951A CN 101436584 B CN101436584 B CN 101436584B
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chip
weld pad
data
semiconductor chip
conjunction
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CN101436584A (zh
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金钟薰
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

一种层叠半导体封装，其能够增加数据存储容量，同时提高数据处理速度。该层叠半导体封装包括：具有芯片选择焊垫和连接焊垫的基板；包含多个半导体芯片的半导体芯片模块，每个芯片包含数据结合焊垫、芯片选择结合焊垫、与该数据结合焊垫电连接的数据再分配单元、以及穿过该数据结合焊垫并与该数据再分配单元连接的数据穿通电极，该半导体芯片被层叠以露出该芯片选择结合焊垫；以及用于将该芯片选择焊垫和该芯片选择结合焊垫电连接的导电引线。

Description

层叠半导体封装
技术领域
本发明涉及一种层叠半导体封装。
背景技术
近年来，随着半导体制造技术的发展，人们已经开发出多种半导体封装，其具有适于在较短时间周期内处理大量数据的半导体器件。
近期，出现了一种层叠半导体封装，其中层叠并电连接了多个半导体芯片，以增大该半导体封装的数据存储容量和数据处理速度。
为了实现该层叠半导体封装，需要一种技术，以选择性地向该多个半导体芯片中的特定半导体芯片施加控制信号或数据信号。
发明内容
本发明的实施例涉及一种层叠半导体封装，其通过穿通电极(throughelectrode)向半导体芯片提供数据信号并通过导电引线向半导体芯片提供芯片择选信号而能够高速工作。
在一个实施例中，一种层叠半导体封装包括：基板，具有芯片选择焊垫和连接焊垫；半导体芯片模块，包括多个半导体芯片，每个半导体芯片具有数据结合焊垫、芯片选择结合焊垫、与该数据结合焊垫电连接的数据再分配单元、以及穿过该数据结合焊垫并与该数据再分配单元电连接的数据穿通电极，该半导体芯片被层叠以露出该芯片选择结合焊垫；以及导电引线，用于电连接该芯片选择焊垫和该芯片选择焊垫结合。
当层叠的半导体芯片的数量为2N(N是大于2的自然数)时，每个半导体芯片包括N个芯片选择结合焊垫。
该层叠半导体封装可以进一步包括与该芯片选择结合焊垫电连接的芯片选择再分配单元。
该层叠半导体封装可以进一步包括穿过该芯片选择结合焊垫的芯片选择穿通电极。
该芯片选择焊垫包括被施加接地电压(Vss)的接地电压焊垫和被施加电源电压(Vcc)的电源电压焊垫。
地址信号、功率信号、数据信号和控制信号输入到该数据再分配单元。
导电连接构件夹置于该数据再分配单元和该穿通电极之间。
该导电连接构件是焊料。
在另一个实施例中，层叠半导体封装包括：基板，具有连接焊垫和芯片选择焊垫；多个半导体芯片，层叠在该基板上，每个半导体芯片具有置于其边缘上方的数据结合焊垫和芯片选择结合焊垫；间隔物，夹置于该半导体芯片之间并将相邻的半导体芯片相互隔离；穿通电极，穿过该半导体芯片并与该数据结合焊垫和该连接焊垫相连；以及导电引线，电连接该芯片选择焊垫和该芯片选择结合焊垫。
每个穿通电极从该半导体芯片相应地突出该间隔物的厚度。
备选地，该穿通电极的长度基本上与该半导体芯片的厚度相等，且导电连接构件夹置于被该间隔物隔离的该穿通电极之间。
该导电连接构件是焊料。
当层叠的半导体芯片的数量为2N(N是大于2的自然数)时，每个半导体芯片包括N个芯片选择结合焊垫和芯片选择再分配单元。
该芯片选择焊垫包括被施加接地电压(Vss)的接地电压焊垫和被施加电源电压(Vcc)的电源电压焊垫。
附图说明
图1为示出了依据本发明的实施例的层叠半导体封装的透视图。
图2为图1所示的基板的平面图。
图3为图1的平面图。
图4为图3中沿着线I-I’截取的横截面图。
图5为示出了依据本发明的另一个实施例的层叠半导体封装的平面图。
图6为图5所示的基板的平面图。
图7为图5中沿着线II-II’截取的横截面图。
具体实施方式
图1为示出了依据本发明的实施例的层叠半导体封装的透视图。
参照图1，层叠半导体封装400包括基板100、半导体芯片模块200和导电引线300。
图2为图1所示的基板的平面图。
参照图1和图2，基板100包括基板主体105、芯片选择焊垫110和连接焊垫120。此外，基板100可以进一步包括球焊盘(ball land)和焊球。
基板主体105具有平板形状。从其顶部观察，基板主体105具有矩形形状，并且基板主体105可以是印刷电路板(PCB)。
芯片选择焊垫110沿着基板主体105的上表面的边缘排布。例如，芯片选择焊垫110可置于基板主体105的上表面的边缘的中心部分。
芯片选择焊垫110包括被施加接地电压Vss的接地电压焊垫112和被施加电源电压Vcc的电源电压焊垫114。
在本实施例中，芯片选择焊垫110的数量由包括在半导体芯片模块200中的半导体芯片的数量决定，该半导体芯片模块200在下文中描述。在所示的本实施例中，芯片选择焊垫110的数量为2，因此包括在半导体芯片模块200中的半导体芯片的数量可以多达4。同样地按照类似方式，当芯片选择焊垫110的数量为3时，包括在半导体芯片模块200中的半导体芯片的数量可以多达8；以及当芯片选择焊垫110的数量为4时，包括在半导体芯片模块200中的半导体芯片的数量可以多达16。
芯片选择焊垫110沿着基板主体105的上表面的边缘排布，并且多个连接焊垫120可以分别置于芯片选择焊垫110的两侧。
图3为图1的平面图。图4为图3中沿着线I-I’截取的横截面图。
参照图3和图4，半导体芯片模块200置于基板主体105的上表面上。
半导体芯片模块200包括多个半导体芯片(210、220、230、240)。在本实施例中，半导体芯片模块200可包括多达2N(N是大于或等于1的自然数)个半导体芯片。例如，半导体芯片模块200可包括多达2(当N为1)、多达4(当N为2)、多达8(当N为3)、多达16(当N为4)或多达32(当N为5)个半导体芯片。
在本实施例中，半导体芯片模块200包括例如4个半导体芯片(210、220、230、240)。
下文中，包括在半导体芯片模块200中的该4个半导体芯片被称为第一半导体芯片210、第二半导体芯片220、第三半导体芯片230和第四半导体芯片240。
置于基板100上方的第一半导体芯片210包括第一数据结合焊垫212、第一芯片选择结合焊垫214、第一数据穿通电极216以及第一数据再分配单元218。地址信号、功率信号、数据信号和控制信号通过基板主体105的连接焊垫120输入到数据结合焊垫212。
第一数据结合焊垫212和第一芯片选择结合焊垫214沿着第一半导体芯片210的上表面的边缘排布。例如，第一数据结合焊垫212和第一芯片选择结合焊垫214沿着第一方向FD排布。
第一数据结合焊垫212置于与图2所示的基板主体105的每个连接焊垫120相对应的位置，并且第一芯片选择结合焊垫214置于与图2所示的基板主体105的每个芯片选择焊垫110相对应的位置。
第一数据穿通电极216穿过第一数据结合焊垫212和第一半导体芯片210。因此，第一半导体芯片210的第一数据穿通电极216与基板主体105的连接焊垫120电连接。诸如焊料的连接构件夹置于连接焊垫120和第一数据穿通电极216之间。
第一数据再分配单元218置于第一半导体芯片210的上表面上方。第一数据再分配单元218的第一端部与第一数据穿通电极216电连接。第一数据再分配单元218的与该第一端部相对的第二端部朝与第一方向FD垂直的第二方向SD延伸第一长度L1。
第一半导体芯片210也可以进一步包括第一芯片选择再分配单元217。第一芯片选择再分配单元217形成在与第一半导体芯片210的第一芯片选择结合焊垫214相对应的位置。第一芯片选择再分配单元217在第二方向SD上具有小于第一长度L1的第二长度。此外，第一芯片选择结合焊垫214可包括穿过第一芯片选择结合焊垫214的第一芯片选择穿通电极。
第二半导体芯片220包括第二数据结合焊垫222、第二芯片选择结合焊垫224、第二数据穿通电极226和第二数据再分配单元228。
第二半导体芯片220以阶梯方式置于第一半导体芯片210上方，因此第一芯片选择结合焊垫214或第一芯片选择再分配单元217通过第二半导体芯片220露出。
第二数据结合焊垫222和第二芯片选择结合焊垫224沿着第二半导体芯片220的上表面的边缘排布，该边缘与第一数据结合焊垫212和第一芯片选择结合焊垫214相邻。例如，第二数据结合焊垫222和第二芯片选择结合焊垫224沿着第一方向FD排布。第二数据结合焊垫222置于第一数据再分配单元218上方。
第二数据穿通电极226穿过第二数据结合焊垫222和第二半导体芯片220。因此，第二数据穿通电极226与第一数据再分配单元218电连接。导电连接构件(未示出)可夹置于第二数据穿通电极226和第一数据再分配单元218之间。可用作该导电连接构件的示例材料包括焊料。
第二数据再分配单元228置于第二半导体芯片220的上表面上方。第二数据再分配单元228的第一端部与第二数据穿通电极226电连接。与第二数据再分配单元228的该第一端部相对的第二端部朝与第一方向FD垂直的第二方向SD延伸第一长度L1。
第二半导体芯片220也可以进一步包括第二芯片选择再分配单元227。第二芯片选择再分配单元227可形成在与第二半导体芯片220的第二芯片选择结合焊垫224相对应的位置。第二芯片选择再分配单元227沿第二方向形成小于第一长度L1的第二长度。此外，第二芯片选择结合焊垫224可包括穿过第二芯片选择结合焊垫224的第二芯片选择穿通电极(未示出)。
第三半导体芯片230包括第三数据结合焊垫232、第三芯片选择结合焊垫234、第三数据穿通电极236和第三数据再分配单元238。第三半导体芯片230以阶梯方式置于第二半导体芯片220上方，因此第二芯片选择结合焊垫224或第二芯片选择再分配单元227通过第三半导体芯片230露出。
第三数据结合焊垫232和第三芯片选择结合焊垫234沿着第三半导体芯片230的上表面的边缘排布，该边缘与第二数据结合焊垫222和第二芯片选择结合焊垫224相邻。例如，第三数据结合焊垫232和第三芯片选择结合焊垫234沿着第一方向FD排布。第三数据结合焊垫232置于第二数据再分配单元228上方。
第三数据穿通电极236穿过第三数据结合焊垫232和第三半导体芯片230。因此，第三数据穿通电极236与第二数据再分配单元228电连接。导电连接构件可夹置于第三数据穿通电极236和第二数据再分配单元228之间。可用作该导电连接构件的示例材料包括焊料。
第三数据再分配单元238置于第三半导体芯片230的上表面上方。第三数据再分配单元238的第一端部与第三数据穿通电极236电连接。与第三数据再分配单元238的该第一端部相对的第二端部朝与第一方向FD垂直的第二方向SD延伸第一长度L1。
同时，第三半导体芯片230可以进一步包括第三芯片选择再分配单元237。第三芯片选择再分配单元237可形成在与第三半导体芯片230的第三芯片选择结合焊垫234相对应的位置。第三芯片选择再分配单元237沿第二方向形成小于第一长度L1的第二长度。此外，第三芯片选择结合焊垫234包括穿过第三芯片选择结合焊垫234的第三芯片选择穿通电极。
第四半导体芯片240包括第四数据结合焊垫242、第四芯片选择结合焊垫244、第四数据穿通电极246和第四数据再分配单元248。第四半导体芯片230以阶梯方式置于第三半导体芯片230上方，因此第三芯片选择结合焊垫234或第三芯片选择再分配单元237通过第四半导体芯片240露出。
第四数据结合焊垫242和第四芯片选择结合焊垫244沿着第四半导体芯片240的上表面的边缘排布，该边缘与第三数据结合焊垫232和第三芯片选择结合焊垫234相邻。例如，第四数据结合焊垫242和第四芯片选择结合焊垫244沿着第一方向FD排布。第四数据结合焊垫242置于第三数据再分配单元238上方。
第四数据穿通电极246穿过第四数据结合焊垫242和第四半导体芯片240，因此第四数据穿通电极246与第三数据再分配单元238电连接。导电连接构件(未示出)可夹置于第四数据穿通电极246和第三数据再分配单元238之间。可用作该导电连接构件(未示出)的示例材料包括焊料。
第四数据再分配单元248置于第四半导体芯片240的上表面上方。第四数据再分配单元248的第一端部与第四数据穿通电极246电连接。与第四数据再分配单元248的该第一端部相对的第二端沿着与第一方向FD垂直的第二方向SD延伸第一长度L1。
第四半导体芯片240可以进一步包括第四芯片选择再分配单元247。第四芯片选择再分配单元247可形成在与第四半导体芯片240的第四芯片选择结合焊垫244相对应的位置。第四芯片选择再分配单元247沿第二方向形成小于第一长度L1的第二长度。此外，第四芯片选择结合焊垫244包括穿过第四芯片选择结合焊垫244的第四芯片选择穿通电极。
再次参照图4，基板主体105的连接焊垫120与第一半导体芯片210的第一数据穿通电极216电连接，并且第一数据再分配单元218、第二数据穿通电极226、第二数据再分配单元228、第三数据穿通电极236、第三数据再分配单元238、第四数据穿通电极246、第四数据再分配单元248全部电学互联在一起。
再次参照图1和图3，导电引线300电连接到基板主体105的芯片选择焊垫110，并且电连接到第一到第四半导体芯片210、220、230和240的第一到第四芯片选择结合焊垫214、224、234和244。
表1概述了通过导电引线300将芯片选择焊垫110和第一到第四芯片选择结合焊垫214、224、234和244电连接的布局方案之一。
<表1>
芯片选择结合焊垫(P1) 芯片选择结合焊垫(P2)
第一半导体芯片     Vss     Vss
第二半导体芯片     Vcc     Vss
第三半导体芯片     Vss     Vcc
第四半导体芯片     Vcc     Vcc
图5为示出了依据本发明的另一个实施例的层叠半导体封装的平面图。
参照图5-7，层叠半导体封装950包括基板500、半导体芯片600、间隔物700、穿通电极800和导电引线900。
图6为图5所示的基板的平面图。
基板500是具有平板形状的印刷电路板(PCB)。该PCB包括芯片选择焊垫510和连接焊垫520。
芯片选择焊垫510包括被施加接地电压Vss的接地电压焊垫512和被施加电源电压Vcc的电源电压焊垫514。尽管在本实施例中芯片选择焊垫510包括接地电压焊垫512和电源电压焊垫514，芯片选择焊垫510可包括最少三个焊垫。
半导体芯片600置于形成有芯片选择焊垫510和连接焊垫520的基板500的上表面上方。在本实施例中，例如，四个半导体芯片600置于基板500的上表面上方。
在目前所示的本实施例中，四个半导体芯片600基本上具有同样的形状。每个半导体芯片600包括置于与基板500的连接焊垫520相对应的位置的数据结合焊垫610，以及置于与基板500的芯片选择焊垫510相对应的位置的芯片选择结合焊垫620。数据结合焊垫610和芯片选择结合焊垫620分别沿着半导体芯片600的该上表面的边缘排布。
图7为图5中沿着线II-II’截取的横截面图。
间隔物700夹置于层叠在基板500上方的一对相邻的半导体芯片600之间。间隔物700在该相邻的半导体芯片600之间形成间隙。
穿通电极800穿过形成在半导体芯片600内的数据结合焊垫610，以及穿过与数据结合焊垫610相对应的半导体芯片600。穿通电极800具有柱形形状，且可用作穿通电极800的示例材料包括铜。
穿过半导体芯片600的穿通电极800的长度基本上与半导体芯片600的厚度相等。在穿通电极800的长度基本上与半导体芯片600的厚度相等的情况下，诸如焊料的连接构件夹置于该相邻的半导体芯片600的穿通电极800之间，以电连接通过间隔物700相互隔离的半导体芯片600的穿通电极800。
同时，如图7所示，穿通电极800的长度超过半导体芯片600的厚度，以电连接该相邻的半导体芯片600的穿通电极800。具体而言，每个穿通电极800从半导体芯片600相应地突出间隔物700的厚度。
按照图1所示的方法，导电引线900电连接形成在基板500内的芯片选择焊垫510以及形成在每个半导体芯片600内的芯片选择结合焊垫620。
从上文描述显见，在本发明中，由于多个层叠的半导体芯片的数据结合焊垫通过穿通电极而电连接，并且芯片选择结合焊垫和基板的芯片选择焊垫通过导电引线而电连接，从而具有如下优势：数据通过该穿通电极高速输入或输出，并且通过导电引线连接芯片选择结合焊垫和芯片选择焊垫，制作工艺可以显著缩短。
尽管为了说明的目的，描述了本发明的具体实施例，本领域技术员将会理解，在不背离在权利要求书中披露的本发明的范围和精神的情况下可以进行各种修正、添加和替换。
本申请主张于2007年11月13日提交的韩国专利申请No.10-2007-00115700的优先权，其全部内容引用结合于此。

Claims (14)

1.一种层叠半导体封装，包括：
基板，在其上表面上具有芯片选择焊垫和连接焊垫；
半导体芯片模块，包括在所述基板的上表面上的多个半导体芯片，每个半导体芯片在其上表面上包括：
数据结合焊垫；
芯片选择结合焊垫；
数据再分配单元，电连接到所述数据结合焊垫；以及
多个穿通电极，分别穿通所述每个半导体芯片，与所述基板相邻的半导体芯片中的穿通电极将该半导体芯片上的数据结合焊垫电连接到所述基板上的连接焊垫，除去与所述基板相邻的半导体芯片之外的各半导体芯片的穿通电极将相应的半导体芯片上的数据结合焊垫电连接到在下方相邻的半导体芯片上的数据再分配单元，其中所述半导体芯片被层叠以露出所述芯片选择结合焊垫；以及
导电引线，将所述芯片选择焊垫电连接到所述芯片选择结合焊垫。
2.根据权利要求1的层叠半导体封装，其中当层叠的半导体芯片的数量为2N，且N是大于2的自然数时，每个半导体芯片包含N个芯片选择结合焊垫。
3.根据权利要求1的层叠半导体封装，还包括与所述芯片选择结合焊垫电连接的芯片选择再分配单元。
4.根据权利要求3的层叠半导体封装，其中部分所述穿通电极将所述芯片选择焊垫电连接到所述芯片选择再分配单元。
5.根据权利要求1的层叠半导体封装，其中所述芯片选择焊垫包括被施加接地电压的接地电压焊垫和被施加电源电压的电源电压焊垫。
6.根据权利要求1的层叠半导体封装，其中地址信号、功率信号、数据信号和控制信号被输入到所述数据再分配单元。
7.根据权利要求1的层叠半导体封装，其中导电连接构件夹置于所述数据再分配单元和所述穿通电极之间。
8.根据权利要求7的层叠半导体封装，其中所述导电连接构件是焊料。
9.一种层叠半导体封装，包括：
基板，具有连接焊垫和芯片选择焊垫；
多个半导体芯片，层叠在所述基板上方，每个所述半导体芯片具有置于其边缘上方的数据结合焊垫和芯片选择结合焊垫；
间隔物，夹置于每对相邻的半导体芯片之间，并使每对相邻的半导体芯片相互隔离；
多个穿通电极，分别穿过每个半导体芯片并与相对应的半导体芯片的数据结合焊垫电连接，相邻的半导体芯片中的穿通电极相互电连接，且与所述基板相邻的半导体芯片中的穿通电极电连接到所述连接焊垫；以及
导电引线，电连接所述芯片选择焊垫和所述芯片选择结合焊垫。
10.根据权利要求9的层叠半导体封装，其中每个穿通电极从所述半导体芯片相应地突出所述间隔物的厚度。
11.根据权利要求9的层叠半导体封装，其中所述穿通电极的长度基本上等于所述半导体芯片的厚度，并且导电连接构件夹置于被所述间隔物隔离的所述穿通电极之间。
12.根据权利要求11的层叠半导体封装，其中所述导电连接构件是焊料。
13.根据权利要求9的层叠半导体封装，其中当层叠的半导体芯片的数量为2N，且N是大于2的自然数时，每个半导体芯片包括N个芯片选择结合焊垫和芯片选择再分配单元。
14.根据权利要求9的层叠半导体封装，其中所述芯片选择焊垫包括被施加接地电压的接地电压焊垫和被施加电源电压的电源电压焊垫。
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