CN102332531A - 两端子阻抗切换器件结构及其制造方法 - Google Patents
两端子阻抗切换器件结构及其制造方法 Download PDFInfo
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Abstract
一种形成两端子器件的方法，包括形成第一电介质材料覆盖衬底表面区域。形成底部布线材料覆盖第一电介质材料和沉积切换材料覆盖底部布线材料。使底部布线材料和切换材料经受第一图案化和蚀刻工艺以形成第一结构。该第一结构至少包括底部布线结构和具有第一侧面区域的切换元件，和包含切换元件的暴露区域的顶部表面区域。形成第二电介质材料至少覆盖包含切换元件暴露区域的第一结构。在第二电介质层的部分中形成开口区域以暴露切换元件的顶部表面区域的部分。形成包含导电材料的顶部布线材料至少覆盖开口区域以便于导电材料与切换元件直接接触。执行第二蚀刻工艺以至少形成顶部布线结构。
Description
技术领域
本发明一般涉及两端子器件。更为具体地，本发明的实施例提供一种用于两端子切换器件的方法和结构。两端子切换器件可以用作具有随机存取且快速切换特性的非易失性阻抗切换存储器。
背景技术
半导体器件的成功主要由密集晶体管比例缩小工艺来推动。然而，当场效应晶体管(FET)尺寸接近小于100nm，诸如短沟道效应的问题开始阻止正确的器件操作。此外，这种低于100nm的器件尺寸会导致非定比例(non-scaling)的亚阈斜率且会增加功耗。通常认为诸如那些普通公知的Flash的基于晶体管存储器在十年内会达到缩放比例极限。Flash存储器是一种非易使存储器器件类型。
已经在研究诸如铁电RAM(Fe RAM)、磁阻RAM(MRAM)、有机RAM(ORAM)和相变RAM(PCRAM)等的其他非易失性随机存取存储器(RAM)器件作为下一代存储器器件。这些器件通常需要新的材料和器件结构以与硅基器件相耦合以形成存储器单元，这缺乏一种或多种关键品质。例如，Fe-RAM和MRAM器件具有快速的切换特性和优良的编程持久性，但是他们的制造与CMOS不兼容且尺寸通常很大。PCRAM器件的切换利用焦尔热效应，这固有地具有更高功耗。有机RAM或ORAM与大规模硅基制造不兼容且器件可靠性通常很差。
综上所述，因此期望一种改进的半导体存储器器件和技术。
发明内容
本发明一般涉及两端子器件。更为具体地，本发明的实施例提供一种用于两端子切换器件的方法和结构。已经将两端子切换器件应用于非易失性阻抗切换存储器(resistive switching memory device)。但是应该认识到本发明可以具有更广泛的应用范围。
在具体实施例中，提供一种用于形成两端子切换器件的方法。该方法包括提供衬底和形成覆盖衬底表面区域的第一电介质材料。沉积底部布线材料来覆盖该电介质材料。该方法包括沉积接触材料来覆盖底部布线材料并沉积切换材料来覆盖包括接触材料的底部布线材料。在某些实施例中，接触材料是可选项。该方法形成覆盖切换材料的掩模层。在具体的实施例中，该方法利用掩模层使底部布线材料、接触材料和切换材料经受第一蚀刻工艺以形成第一结构。第一结构包括底部布线结构和切换元件。第一结构具有顶表面区域和侧面区域。在具体的实施例中，顶表面区域包括切换元件的顶部区域。该方法包括沉积第二电介质材料来至少覆盖第一结构，该第一结构包含切换元件的暴露的顶部区域和第一电介质材料的暴露部分。该方法包括平坦化至少覆盖第一结构的第二电介质材料表面同时保持覆盖第一结构的第二电介质材料的部分。在第二电介质层的部分中形成开口区域以暴露第一结构的顶表面区域的一部份。然后该方法沉积导电材料来覆盖该开口区域。在具体的实施例中，导电材料与切换元件直接接触。形成顶部布线材料至少覆盖导电材料，并采用第二蚀刻工艺以至少形成顶部布线结构。在具体的实施例中，包含切换元件的第一侧面区域的第一结构的侧面区域免受来自第二蚀刻工艺的导电材料的污染。
在另外的实施例中，提供一种形成两端子切换器件的方法。该方法包括提供衬底和形成覆盖衬底表面区域的第一电介质材料。沉积底部布线材料来覆盖该电介质材料。该方法包括沉积接触材料来覆盖底部布线材料并沉积切换材料来覆盖包括接触材料的所述底部布线材料。在某些实施例中，接触材料是可选项。该方法形成覆盖切换材料的掩模层。在具体的实施例中，该方法利用掩模层使底部布线材料、接触材料和切换材料经受第一蚀刻工艺以形成第一结构。第一结构包括底部布线结构和切换元件。第一结构具有顶表面区域和侧面区域。在具体的实施例中，顶表面区域包括切换元件的顶部区域。该方法包括沉积第二电介质材料来至少覆盖第一结构，该第一结构包含切换元件的暴露的顶部区域和第一电介质材料的暴露部分。该方法包括平坦化至少覆盖第一结构的第二电介质材料表面，同时保持覆盖第一结构的第二电介质材料的部分。在第二电介质层的部分中形成开口区域以暴露第一结构的顶表面区域的一部份。在具体的实施例中，该方法沉积导电材料来覆盖包含所述开口区域的第二电介质材料以与切换元件直接接触。该方法包括沉积第一粘合层来覆盖所述导电材料，并使第一粘合层和该导电材料经受第二图案化及蚀刻工艺。第二图案化和蚀刻工艺去除部分所述导电材料和部分第一粘合层以暴露第二电介质材料的表面区域，同时至少保持至少在开口区域中的导电材料和粘合层。形成顶部布线材料来覆盖第一粘合层和第二电介质层的暴露部分。在具体的实施例中，顶部布线材料经受第二图案化和蚀刻工艺以形成顶部布线结构。在具体的实施例中，包含切换元件的第一侧面区域的第一结构的侧面区域免受来自第二图案化和蚀刻工艺的导电材料的污染，且在顶部布线结构和底部布线结构之间没有短路发生。
通过本发明可以获得许多益处。仅例如，本发明方法提供用于利用金属作为顶部电极来制造切换器件的方法和结构。由于在上部电极蚀刻期间没有暴露切换材料的侧壁，该方法提供没有诸如顶部电极与底部电极之间短路的缺陷的器件结构，由此提高器件性能和器件产量。
附图说明
图1是示出布置在交叉棒式(crossbar)结构中的两端子切换器件的简化视图；
图2是示出切换器件的电极之间的短路的简化视图；
图3-16是示出根据本发明实施例的形成两端子切换器件的方法的简化视图；
图17-19是示出根据本发明实施例的形成两端子切换器件的另一方法的简化视图；
图20-21是示出根据本发明实施例的形成两端子切换器件的另一方法的简化视图；
图22-23是示出根据本发明实施例的形成两端子切换器件的方法简化视图。
具体实施方式
本发明一般涉及两端子器件。更为具体地，本发明的实施例提供一种用于两端子切换器件的方法和结构。两端子切换器件可以用于提供随机存取、快速切换和能缩小至很小尺寸的非易失性阻抗切换存储器器件。但是应该认可本发明可以具有更广泛的应用范围。
对于利用阻抗切换的切换器件，对于电极或布线结构中的每一个使用所选择的材料。例如，诸如铂的贵金属用于氧化镍基阻抗切换器件以向所述器件提供欧姆接触并防止与切换材料化学反应。某些固态电解液基(electrolytebased)(例如GeSe)切换器件或非晶硅基切换器件使用银作为电极材料或接触材料的至少一种以提高切换性能。这些金属材料通常不应用于当前的CMOS制造。特别地，由于它们的惰性性质，对这些材料的化学蚀刻特别具有挑战性或者是不可能，使得纳米级器件制造困难。
图1是示出在交叉棒式结构中的阻抗切换器件的简化视图，但是其他空间布置也是可能的。阻抗切换器件100包括顶部布线结构102、底部布线结构104、以及构造于夹在顶部布线结构与底部布线结构之间的交叉区域中的切换层106。例如，顶部布线结构至少包括银、金、铂、钯或其他金属材料，取决于实施例，切换层可以由诸如金属氧化物材料或非晶硅材料的氧族化合物材料组成。
图2示出部分形成的器件202。该部分形成的器件包括底部布线结构208、切换元件210和顶部布线结构204。通过同时蚀刻顶部布线材料204和切换层210来形成部分形成的器件。当用于特定切换器件的顶部布线结构由惰性金属组成时，采用诸如溅射的物理蚀刻来蚀刻。该蚀刻步骤会导致沉积于切换层侧壁上的污染物导电材料206的形成，如图所示。污染物导电材料可以是来自于顶部布线结构或底部布线结构或来自这二者的被蚀刻掉材料，且会导致顶部布线结构204和底部布线结构208之间电短路，降低器件性能和产量。
因此，本发明提供用于形成切换器件的方法和结构，特别地，阻抗切换器件利用至少一种贵金属作为布线结构的一个或两个所述布线结构。但是应该认可根据本发明的实施例可以应用于其它器件。
图3-16示出根据本发明实施例的制造切换器件的方法。该方法包括提供包括表面区于304的衬底302。衬底可以为诸如硅晶片等的半导体衬底。在某些实施例中，衬底可以包括形成于其上的一个或多个器件。取决于实施例，所述一个或多个器件可以包括CMOS器件，以及其他。如图4中所示，该方法包括形成第一电介质材料402来覆盖衬底的表面区域。第一电介质材料可以为氧化硅或氮化硅或包含不同电介质膜的组合的合适的电介质膜叠层。可以利用诸如包含等离子体增强化学气相沉积的化学沉积、旋涂、这些技术的组合等技术来形成第一电介质材料。
参考图5，该方法沉积第一粘合层502来覆盖第一电介质材料。第一粘合层可以为氮化钨、钛、氮化钛、钽或氮化钽、或这些膜的任意组合或其他。第一粘合层可以利用诸如化学气相沉积或原子层沉积等化学沉积来形成。在其他应用中，取决于该应用，可以使用诸如溅射的物理气相沉积。如图6中所示，形成底部布线材料602来覆盖第一粘合层。取决于实施例，底部布线结构材料可以为铜、钨、铝或其他合适的金属材料。可以利用诸如物理气相沉积工艺的技术来沉积底部布线材料，例如，溅射或蒸镀。底部布线材料也可以利用化学气相沉积、或诸如电镀或来自液体媒介的无电镀沉积的电化学沉积方法或包括各种方法的组合的其他适合的沉积技术来沉积。在具体的实施例中，第一粘合层向第一布线材料和第一电介质材料提供粘贴层。
如图7中所示，该形成切换器件的方法包括沉积第二粘合层702来覆盖底部布线结构材料。第二粘合层可以为阻挡层或闭锁层以防止底部布线结构材料与例如切换层材料或随后形成的接触层材料的化学反应。取决于实施例，第二粘合层可以为钛、氮化钛、钽、氮化钽、钨、氮化物、或其他。
参考图8，在具体实施例中，该方法包括形成接触材料802来覆盖第二粘合层。在具体的实施例中，接触材料可以为诸如掺杂多晶硅(下文中称之为多晶硅材料)的掺杂半导体材料。在具体实施例中，多晶硅材料用于底部布线材料与非晶硅切换材料之间的接触层。在优选实施例中，掺杂多晶硅材料为利用诸如硼等的杂质的p+掺杂。在具体实施例中，硼具有大约10E18至10E21cm-3的浓度范围。在特定实施例中，会进一步处理多晶硅材料以提高切换器件的性能。例如，可以在掺杂多晶硅材料的表面区域中形成缺陷或纳米金属材料以提高切换器件的性能。在具体的实施例中，多晶硅材料使得能够控制并提高非晶硅切换材料的切换特性。对于其他切换材料，可以使用诸如金属氧化物或其他的其他接触材料，或不需要接触层。当然，本领域技术人员会意识到其他变化、修正和改变。
在具体的实施例中，如图9中所示，该方法形成切换材料902来覆盖接触材料。切换材料可以为未掺杂非晶硅材料。取决于实施例，未掺杂非晶硅材料可以利用化学气相沉积方法或物理气相沉积方法来沉积。该化学气相沉积方法可以包括利用硅烷、乙硅烷、合适的氯硅烷、或包含气体的合适硅作为前体的化学气相沉积工艺。在具体的实施例中，未掺杂非晶硅材料可以利用等离子体增强化学气相沉积(PECVD)工艺或低压化学气相沉积(LPCVD)工艺来沉积。用于非晶硅材料的沉积温度可以在从大约200摄氏度到大约450摄氏度的范围内，且优选在大约350摄氏度到大约400摄氏度的范围内。取决于实施例，可以提供在从大约50埃至大约1000埃的厚度范围内的非晶硅材料。在优选的实施例中，可以提供在从大约100埃至大约500埃的厚度范围内的非晶硅材料。
参考图10，该方法包括形成掩模层1002来覆盖切换材料。取决于实施例，该掩模层可以为适合的有机光致抗蚀剂材料、或无机硬掩模、或二者的组合。取决于应用，可以由诸如氧化硅或氮化硅的电介质材料或其他形成硬掩模。取决于实施例，硬掩模可以为金属硬掩模。
在具体的实施例中，该方法利用掩模层作为掩模使切换材料、接触材料和底部布线结构材料经受第一蚀刻工艺以形成第一结构1102，如图11中所示。第一蚀刻工艺选择性地去除第一电介质材料的一部分以暴露第一电介质材料的顶表面区域1108。在具体的实施例中，第一结构至少包括底部布线结构1104和切换元件1106。切换元件至少包括第一侧面区域1110。取决于所使用的硬掩模，在蚀刻工艺之后可以去除硬掩模的剩余部分。或者，在具体实施例中，对于利用氧化硅的硬掩模和利用氧化硅材料的第二电介质层，硬掩模会在蚀刻之后完整无缺地留下来。
参考图12，该方法包括沉积第二电介质层以覆盖第一结构和第一电介质层的暴露部分。取决于实施例，第二电介质层可以包括氧化硅材料或氮化硅材料或其组合。在具体的实施例中，第二电介质层可以为利用采用TEOS(四乙基原硅酸盐，tetraethyloxysilicate)作为前体的等离子体增强化学气相沉积工艺沉积的氧化硅。氧化硅材料还可以利用旋涂玻璃(SOG)技术和随后合适的固化工艺来形成。或者，取决于具体应用，还可以使用旋涂玻璃和化学气相沉积的组合。
在具体的实施例中，该方法采用平坦化工艺以形成平坦化电介质表面1302，如图13中所示。在具体的实施例中，这可以通过对第二电介质材料的化学机械抛光、或各项异性化学蚀刻或覆层蚀刻(blanket etch)来实现。如图所示，在具体的实施例中，覆盖切换元件顶部区域的第二电介质材料的部分1304被保留。在具体实施例中，该方法包括在第二电介质材料的部分中形成开口区域1402以暴露切换元件的顶部区域的一部份，如图14中所示。在具体的实施例中，通过利用第二图案化和蚀刻工艺来形成开口区域。例如，对于二氧化硅作为电介质材料，蚀刻工艺可以为干蚀刻，诸如利用CF4、SF6或NF3作为蚀刻气体的氟基蚀刻。取决于实施例，也可以使用诸如HF基蚀刻的适合的湿蚀刻技术。
在具体的实施例中，该方法沉积导电材料1502来覆盖包含切换元件被暴露的顶部区域的开口区域。如图中所示，在具体实施例中，导电材料形成与所述开口区域大体保形且与切换元件接触。在具体实施例中，对于非晶硅切换材料，导电材料包括银材料。可以利用诸如溅射或蒸镀的物理气相沉积工艺来沉积银材料。取决于应用，还可以通过诸如化学气相沉积的化学沉积工艺、诸如电镀或无电镀沉积的电化学方法或其组合来形成银材料。该方法沉积第三粘合层1504来覆盖导电材料，如图15中所示。在具体实施例中，第三粘合层可以用作阻挡层以防止例如银材料的导电材料被氧化。第三粘合层1504可以用作导电材料1502与后续层之间的扩散阻挡，并形成导电材料与后续层之间的电接触。取决于实施例，第三粘合层1504可以为钛、氮化钛、钽或氮化钽、钨、或氮化物。取决于应用，第三粘合层1504可以利用诸如原子层沉积、化学气相沉积等的化学沉积或诸如溅射的物理沉积或其他方法来形成。
参考图16，该方法形成顶部布线材料1602来覆盖阻挡层。取决于实施例，顶部布线材料可以为钨、铝、铜或其他。例如，可以利用诸如溅射、蒸镀等的物理气相沉积工艺技术来沉积顶部布线结构材料。取决于实施例，还可以利用诸如化学气相沉积、电化学沉积(包括电镀和无电镀)的化学沉积来沉积顶部布线结构材料。
在具体的实施例中，该方法包括使顶部布线材料与阻挡层和导电材料一起经受第二图案化和蚀刻工艺以形成用于切换器件的顶部布线结构。在具体的实施例中，将顶部布线结构和底部布线结构在空间上倾斜布置。在某些实施例中，将第一布线结构和第二布线结构在空间上呈正交方式布置。在具体实施例中，由于在顶部布线材料蚀刻其间将包含切换元件和底部布线结构的第一结构嵌入在电介质材料中，所以第一结构的侧面区域被保护不受沉积材料的污染，该沉积材料例如是由于对至少顶部材料和导电材料的蚀刻产生的污染物导电材料。因此，避免了顶部布线结构与底部布线结构之间的短路。
在具体的实施例中，当向顶部布线结构或底部布线结构施加合适的电压以改变切换材料的电阻特性时，导电材料在切换材料中形成多个包含细丝结构的导电材料颗粒。以银材料作为导电材料而非晶硅作为切换材料作为例子，一旦向顶部布线结构施加正电压，则在非晶硅材料的缺陷区域中形成多个银颗粒。所述多个银颗粒可以包括具有长度的银细丝结构。允许银细丝结构的长度根据施加的合适电压而改变，由此改变非晶硅材料的电阻，使得能够通过阻抗切换该器件。在于2007年10月19日提交的美国申请No.11/875,541中描述了这种器件结构，该申请也转让给了本申请的申请人，这里，通过引用将其全文并入本文。
取决于实施例，可以存在如图17a、17b、18和19中示出的各种变化。例如，在沉积如图15中的导电材料1502和第三粘合层1504之后，该方法可以执行图案化和蚀刻工艺以去除导电材料1502的第一部分和第三阻挡层1504的第一部分，以暴露第二电介质材料的表面区域1702，如图17a和图17b中所示。如所示出的，导电材料的第二部分和第三阻挡层的第二部分至少保留在开口区域中，如图17a和图17b中所示。导电材料的第二部分保持与切换元件接触。该方法然后沉积第四阻挡层1802来覆盖第二电介质材料的暴露区域和开口区域中的第三粘合层，如图18中所示。
参考图19，另一种方法沉积顶部布线材料1902来覆盖第四粘合层并执行图案化和蚀刻工艺以形成顶部布线结构。在具体实施例中，顶部布线结构和底部布线结构在空间上倾斜布置并在具体实施例中形成交叉棒式结构。
取决于实施例，还可以存在如图20-21中示出的其他变化。例如，采用图12中的中间过程形成结构，平坦化第二电介质层1202以暴露切换元件的表面区域2004并形成大体平坦的第二电介质表面2002，如图20中所示。沉积导电材料2102来覆盖切换元件和平坦的第二电介质表面，如图21中所示。如图所示，导电材料与切换元件接触。形成第三粘合层2104来覆盖导电材料且沉积顶部布线材料2106来覆盖粘合层2104。该方法使导电材料、第三粘合层和顶部布线材料经受图案化和蚀刻工艺以形成顶部布线结构。在具体的实施例中，将顶部布线结构相对于底部布线结构在空间上倾斜布置。在具体的实施例中，对于利用非晶硅材料的切换元件，可以使用银材料作为导电材料。第三粘合层可以为钛、氮化钛、钽、氮化钽、氮化钨等。
再者，取决于应用，可以存在如图22和23中示出的变化。例如，图14中的开口区域1402可以用导电材料2202来填充以形成插销状结构，如图22中所示。如图所示，导电材料2202与切换元件接触。形成粘合层2302来覆盖导电材料并形成顶部布线材料2304来覆盖粘合层，如图23中所示。在具体实施例中，该方法然后执行图案化和蚀刻工艺以形成相对于底部布线结构具有一定角度的顶部布线结构。在具体实施例中，将顶部布线结构在空间上布置成与底部布线结构正交。
因此，根据本发明的实施例提供一种形成在顶部布线结构与底部布线结构之间没有短路的切换器件的方法。已经将本方法应用于具有Ag/非晶硅/p+多晶硅结构且采用钨材料作为顶部布线材料和底部布线材料的器件结构中。应该理解，本发明可以应用于使用惰性金属或贵金属的器件的制造。这种器件的实例可以包括利用金属氧化物作为切换材料的切换器件，顶部布线材料或底部布线材料中的至少一种为惰性的以不与金属氧化物切换材料化学反应。顶部惰性布线材料的蚀刻可采用物理蚀刻。来自顶部布线材料或底部布线材料等的被蚀刻导电材料或其他材料在切换元件的侧面区域的再沉积会在顶部电极与底部电极之间形成短路，影响器件性能和产量。
应该理解，本文中所描述的示例和实施例仅为示例性的目的，而本领域技术人员根据其会提议出各种修改或改变，且这些修改或改变落入本申请的精神和范围以及附属权利要求的范围。
Claims (13)
1.一种形成两端子切换器件的方法，包括：
提供衬底；
形成第一电介质材料来覆盖所述衬底表面区域；
沉积底部布线材料来覆盖所述电介质材料；
沉积接触材料来覆盖所述底部布线材料；
沉积切换材料来覆盖包括所述接触材料的所述底部布线材料；
形成掩模层来覆盖该切换材料；
利用所述掩模层使所述底部布线材料、所述接触材料和所述切换材料经受第一蚀刻工艺，以形成具有顶部表面区域和侧面区域的第一结构，第一结构至少包括底部布线结构和切换元件，该切换元件具有第一侧面区域，所述顶部表面区域包含所述切换元件被暴露的区域；
沉积第二电介质材料来至少覆盖包含所述切换元件的所述暴露区域的第一结构和第一电介质材料的暴露区域；
形成平坦化的第二电介质材料表面来至少覆盖的第一结构并暴露切换元件顶部区域；
沉积导电材料来覆盖第二电介质材料和所述切换元件的顶部表面区域，该导电材料与该切换元件直接接触；
沉积顶部布线材料至少覆盖所述导电材料；
使所述顶部布线材料经受第二蚀刻工艺以形成顶部布线结构；
其中，包含所述切换元件的第一侧面区域的第一结构的侧面区域没有来自至少第二图案化和蚀刻工艺的污染物导电材料。
2.根据权利要求1的方法，其中将顶部布线结构和底部布线结构在空间上按照交叉棒式结构布置。
3.根据权利要求1的方法，其中，顶部布线材料还包括第一粘合材料或第一阻挡材料，其中第一粘合材料或第一阻挡材料包括钛、氮化钛、钽、氮化钽或氮化钨。
4.根据权利要求1的方法，底部布线材料还包括第二粘合材料或第二阻挡材料，其中第二粘合材料或第二阻挡材料包括钛、氮化钛、钽、氮化钽或氮化钨。
5.根据权利要求1的方法，其中所述衬底包括制造于其上的一个或多个CMOS器件，所述两端子器件可以***作以与一个或多个CMOS器件耦合。
6.根据权利要求1的方法，其中所述接触材料包括多晶硅材料。
7.根据权利要求6的方法，其中所述多晶硅材料被利用具有从大约10E17至10E21cm-3浓度范围的硼进行了p+掺杂。
8.根据权利要求6的方法，其中所述多晶硅材料具有从大约50埃至大约2000埃的厚度范围。
9.根据权利要求6的方法，其中所述多晶硅材料具有从大约100埃至大约500埃的厚度范围。
10.根据权利要求1的方法，其中所述切换材料为非晶硅材料。
11.根据权利要求1的方法，其中所述导电材料包括诸如金、铂、银、钯、镍或铜的金属，以及包含这些金属的任意组合。
12.根据权利要求11的方法，其中所述导电材料包括具有从大约50埃至大约2000埃厚度范围的银。
13.根据权利要求11的方法，其中所述导电材料包括具有从大约100埃至大约500埃厚度范围的银。
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| CN110875353A (zh) * | 2018-08-30 | 2020-03-10 | 台湾积体电路制造股份有限公司 | 存储器装置及其形成方法 |
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| US20120015506A1 (en) | 2012-01-19 |
| US20150200362A1 (en) | 2015-07-16 |
| JP2012023374A (ja) | 2012-02-02 |
| EP2408035A3 (en) | 2014-11-26 |
| KR101860508B1 (ko) | 2018-05-23 |
| JP5863302B2 (ja) | 2016-02-16 |
| EP2408035A2 (en) | 2012-01-18 |
| US9012307B2 (en) | 2015-04-21 |
| KR20120006942A (ko) | 2012-01-19 |
| CN102332531B (zh) | 2016-01-20 |
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