CN102097427B - 层叠型电子器件 - Google Patents

层叠型电子器件 Download PDF

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Publication number
CN102097427B
CN102097427B CN201010550394XA CN201010550394A CN102097427B CN 102097427 B CN102097427 B CN 102097427B CN 201010550394X A CN201010550394X A CN 201010550394XA CN 201010550394 A CN201010550394 A CN 201010550394A CN 102097427 B CN102097427 B CN 102097427B
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semiconductor chip
metal layer
layer
structured metal
insulating barrier
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CN102097427A (zh
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H·埃维
J·马勒
A·普鲁克尔
I·尼基丁
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及一种层叠型电子器件，所述层叠型电子器件包括第一半导体芯片，所述第一半导体芯片限定第一主面和与该第一主面相对的第二主面，并在所述第一主面上具有至少一个电极垫。所述层叠型电子器件还包括载体，在所述载体的第一主表面处布置有第一结构化金属层。所述第一结构化金属层经由导电材料的第一接合层接合至所述电极垫，其中所述第一接合层具有小于10μm的厚度。第一绝缘层覆盖在所述载体的第一主表面和所述第一半导体芯片上面。

Description

层叠型电子器件
技术领域
本发明涉及电子器件，并且更具体地涉及将半导体部件嵌入层叠型衬底的技术，举例来说诸如将半导体部件嵌入印刷电路板。
背景技术
已认识到将半导体器件嵌入层叠型衬底是对于设法使电子器件的大小、厚度、成本和重量最小化的应用而言有前途的技术。常常在诸如手机、膝上型PC、掌上电脑、PDU(个人数字助理)等便携式应用中遇到这样的要求，并且这样的要求还在诸如功率器件的许多其他电子应用中有关联性。
近来，已将半导体芯片直接嵌入PCB(印刷电路板)以及SBU(逐次堆积(build-up))层叠型衬底的堆积层。有前途的嵌入有源器件技术鉴于电路设计和走线能力应允许低的生产成本、有效并且可靠的电连接方法和高的多用性。
发明内容
由于这些及其他原因，对本发明有需要。
附图说明
附图被包括以提供对实施例进一步的理解，并且被并入和构成本说明书的一部分。附图示意实施例并与说明一起用于解释实施例的原理。随着其他的实施例及实施例的许多预期的优点通过参考以下的详细说明而变得更好地被理解，它们将容易地被领会。
图1A至1F是示意性示出制造层叠型电子器件100的方法的一个实施例的剖视图。
图2A至2E是示意性示出制造层叠型电子器件200的方法的一个实施例的剖视图。
图3是示意性示出层叠型电子器件300的一个实施例的剖视图。
图4是示意性示出层叠型电子器件400的一个实施例的剖视图。
图5是示意性示出层叠型电子器件500的一个实施例的剖视图。
图6是示意性示出层叠型电子器件600的一个实施例的剖视图。
具体实施方式
现在参考附图来描述各个方面及实施例，其中相似的附图标记一般地通篇被用于表示相似的元件。为了解释的目的，在以下的说明中陈述了许多特定细节，以便提供对实施例的一个或多个方面的详尽理解。然而，对于本领域的技术人员显然的是，可通过较低程度的特定细节来实践实施例的一个或多个方面。在其他情况下，以示意性的形式示出已知的结构和元件，以便有助于描述实施例的一个或多个方面。因此，以下的说明不应在限制意义上被接受，并且范围由所附权利要求限定。还应注意的是，图中的各种层、片或衬底的表示不一定按比例。
在以下的详细说明中，对形成其部分的附图进行参考，并且在附图中，通过图解说明的方式示出可在其中实践本发明的特定实施例。在这点上，参考正被描述的(一个或多个)图的定向而使用举例来说诸如“上部(upper)”、“下部(lower)”、“顶部”、“底部”、“左侧”、“右侧”、“前侧”、“后侧”等方向术语。由于实施例的部件可被放置在许多不同的定向上，所以方向术语被用于图解说明的目的而决不是限制性的。应理解的是，可利用其他实施例，并且可进行结构上的或逻辑上的改变而不背离本发明的范围。
应理解的是，除非另有说明，在此描述的各种示例性实施例的特征可彼此结合。
如在本说明书中所采用的那样，术语“耦合”和/或“电耦合”不是指元件必须直接耦合到一起；可在“耦合”或“电耦合”的元件之间提供居间元件。
以下进一步描述的半导体芯片可具有不同的类型，可通过不同的技术制成，并且可包括例如集成的电、光电或机电的电路和/或无源器件(passive)。半导体芯片例如可被构造成功率半导体芯片，诸如功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、JFET(结型场效应晶体管)、功率双极型晶体管或功率二极管。此外，半导体芯片可包括控制电路、微处理器或微机电部件。特别地，可涉及具有垂直结构的半导体芯片，换句话说，可按使得电流可在垂直于半导体芯片的主表面的方向上流动的方式来制作半导体芯片。具有垂直结构的半导体芯片可具有接触垫，特别地在其两个主表面上具有接触垫，即在其前侧和后侧上。特别地，功率半导体芯片可具有垂直结构。举例来说，功率MOSFET的源电极和栅电极可位于一个主表面上，而同时该功率MOSFET的漏电极被布置在另一主表面上。此外，以下描述的器件可包括逻辑集成电路以控制其他半导体芯片的集成电路，例如功率半导体芯片的集成电路。半导体芯片不必由例如Si、SiC、SiGe、GaAs的特定半导体材料制成，并且此外，半导体芯片可包含不是半导体的无机和/或有机材料，举例来说诸如绝缘体、塑料或金属。
此外，在此描述的半导体芯片可在它们的外表面中的一个或多个上包括电极垫(electrode pad)(或接触垫)，其中电极垫用于电接触半导体芯片或集成在半导体芯片中的电路。电极垫可具有焊盘(land)的形式，即半导体芯片的外表面上的平整的接触层。电极垫可位于半导体芯片的有源主表面上或位于两个主表面上。例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒的任何想得到的金属或金属合金通常可被用作材料。金属层不必是同质的或者仅由一种材料制成，即有可能在金属层中包含各种材料组成和浓度。
一个或多个半导体芯片被安装在载体(carrier)上并且被嵌入至少一个电绝缘层或层堆叠中以形成层叠型电子器件。电绝缘层可具有箔(foil)或片(sheet)的形状，其被层叠在(一个或多个)半导体器件和载体之上。所述箔可由聚合物材料制成。在一个实施例中，所述箔可由涂有金属层(例如铜层)的聚合物材料制成(所谓的RCC(涂树脂铜)箔)。可持续合适的时间施加热量和压力使得聚合物箔或片附接至底层结构。在层叠期间，电绝缘箔或片能够流动(即处于塑性状态)，导致载体上的半导体芯片或其他拓扑结构之间的间隙被填充以电绝缘箔或片的聚合物材料。电绝缘箔或片可由任何适当的硬质塑料、热塑性或热固性材料或层压材料制成。在一个实施例中，绝缘箔或片可由预浸料坯(prepreg)(预浸渍纤维的简称)制成，即例如由例如玻璃或碳纤维的纤维毡和例如硬质塑料材料的树脂的组合制成。可例如在环氧树脂的基础上制做硬质塑料树脂。预浸材料在本领域中是已知的，并且通常被用于制造PCB(印刷电路板)。在另一实施例中，绝缘箔或片可由颗粒增强的层叠型树脂层制成。所述颗粒可由与预浸料坯层的纤维相同的材料制成。在一个实施例中，绝缘箔或片可由未填充的层叠型树脂层制成。如上所述，所述树脂可例如是热固性树脂。在又一实施例中，绝缘箔或片可由热塑性材料制成，在层叠期间通过施加压力和热量使其熔化并且其在冷却和压力释放时(可逆地)硬化。由热塑性材料制成的层叠型树脂层也可以是未填充的、纤维增强的或颗粒增强的。热塑性材料可以是聚醚酰亚胺(PEI)、聚醚砜(PES)、聚苯硫醚(PPS)或聚酰胺酰亚胺(PAI)的集合中的一种或多种材料。
(一个或多个)半导体芯片被安装在其上的载体形成层叠型电子器件的一部分。在一个实施例中，载体可以是PCB(印刷电路板)。所述PCB可具有至少一个绝缘层和附接于该绝缘层的结构化的金属箔层。绝缘层通常在环氧树脂、聚四氟乙烯、芳族聚酰胺纤维或碳纤维的基础上制做，并且可包括诸如纤维毡的增强手段，例如玻璃或碳纤维。所述(一个或多个)半导体芯片被安装在结构化的金属箔层上。因此，在层叠之后，层叠型电子器件实际上可以是在其中集成有一个或多个裸芯片的多层PCB。在另一实施例中，载体可以是结构化的金属板或片，举例来说诸如引线框架(leadframe)。所述(一个或多个)半导体芯片被安装在结构化的金属板上。电绝缘层或层堆叠被层叠到结构化的金属板和安装在该结构化的金属板上的(一个或多个)半导体芯片上，以形成覆盖并嵌有所述(一个或多个)半导体芯片的堆积层叠型结构。
半导体芯片经由接合层(bond layer)接合至载体的结构化金属层上。在一个实施例中，接合层由扩散焊料制成。如果扩散焊接被用作连接技术，则焊接材料被使用，该焊接材料由于界面扩散过程而在焊接操作结束之后于所述(一个或多个)半导体芯片的电极垫、扩散焊料接合层与载体的结构化金属层之间的界面处引起金属间相。在这种情况下，可想到使用AuSn、AgSn、CuSn、AgIn、AuIn、CuIn、AuSi、Sn或Au焊料。
在一个实施例中，通过使用彼此电接触的金属颗粒的层而使(一个或多个)半导体芯片接合至载体的结构化金属层。为此，有可能使用导电粘合剂，其可基于环氧树脂或其他聚合物材料并且可在其中加例如金、银、镍或铜颗粒，以便提供电导率(electrical conductivity)。还有可能通过涂覆所谓的纳米浆料(nano paste)或通过直接沉积金属颗粒且然后通过执行烧结工艺以产生烧结金属颗粒层来制造这样的包含电互连颗粒的层。
所有的前述实施例，即将扩散焊料或导电粘合剂或烧结的金属颗粒(用可蒸发的浆料涂覆或作为裸颗粒)用于使(一个或多个)半导体芯片接合至载体的结构化金属层均允许生成小的厚度的接合层。这是由于这些材料特定的特性和它们可能的涂覆方法。更具体地，可以高度可控的方式将扩散焊接材料溅射或电流沉积(galvanically deposit)到所述(一个或多个)半导体芯片的电极垫上，使得只有少量的材料能积聚在电极垫上。可通过印刷或点涂(dispensing)技术将包含金属颗粒的浆料(即导电粘合剂或纳米浆料)涂覆于所述(一个或多个)半导体芯片的电极垫，而且这些方法允许将特定且可控的量的材料涂覆在电极垫上。这样，有可能制造具有小于10μm，乃至小于3μm的厚度的接合层。这样小的高度的接合层大大地有助于层叠步骤，并因此允许制造高成品率和可靠性的层叠型电子器件。此外，层叠型电子器件可具有小的厚度，而且该厚度可精确地被限定并在其横向尺寸上可为常数。更进一步，在此描述的薄膜小片(die)附接技术促进从所述(一个或多个)半导体芯片向外排热。有效的传热能力在嵌入小片技术中具有重要意义，特别是在利用功率半导体芯片的情况下。
可通过在此描述的技术来制造各种不同类型的层叠型电子器件。举例来说，层叠型电子器件可构成包含一个或多个功率MOSFET的电源。例如，层叠型电子器件可包括半桥线路(circuitry)，其可例如被实现在用于转换DC电压的电子电路，即所谓的DC-DC转换器中。DC-DC转换器可被用于将由电池或可再充电的电池提供的DC输入电压转换成与下游连接的电子电路的需求相匹配的DC输出电压。
图1A至1F示意制造层叠型电子器件100的方法的第一实施例的工艺步骤。应注意的是，由于可使用未在这些图中被描绘的另外的步骤，图1A至1F所示的制造的各个阶段可被理解为简单化。例如，在层叠型电子器件100的装配期间可涂覆另外的介电层或结构化金属层。将会结合图2至6所示的实施例在下文中进一步解释一些可能的变化。
根据图1A，可提供载体10。载体10可包括由例如聚合物材料制成的绝缘层12和涂覆在绝缘层12的顶部表面上的第一结构化金属层14。第一结构化金属层14可以例如是先前已被涂覆(例如层叠)在绝缘层12上且然后(例如通过蚀刻技术)被构造成引线图案(例如金属迹线)的薄金属箔。所述金属可以是铜或任何其他合适的材料。绝缘层12可以是由介电材料制成的刚性介电层(或板)，举例来说诸如例如通过玻璃、纸等增强的环氧树脂或聚酯。换句话说，载体10例如可以是标准PCB。
根据图1B，提供半导体芯片20。半导体芯片20可以是如上所述的任何类型。举例来说，如图1B所示，半导体芯片20可以是在顶部表面上布置有第一电极垫22和第二电极垫24以及在底部表面上布置有连续的第三电极垫26的垂直半导体器件。举例来说，半导体芯片20可以是功率MOSFET，并且所述第一、第二和第三电极垫可分别构成半导体芯片20的栅极、源极和漏极接触部。
第三电极垫26涂有接合层28。在一个实施例中，接合层28可由扩散焊接材料制成。在这种情况下，可想到使用AuSn、AgSn、CuSn、AgIn、CuIn、AuSi、Sn或Au焊料。可通过举例来说诸如溅射的物理气相沉积(PVD)技术或通过电流沉积将接合层28涂覆于第三电极垫26。这两种技术都允许小且可控的量的材料的涂覆，这些材料以光滑的、平整的层的形状堆积在第三电极垫26上。
在另一实施例中，可通过涂覆包含分布在聚合物材料中的金属颗粒的浆料来实现接合层28。所述浆料可以是流体的、粘性的(viscous)或似蜡的(waxy)。树脂材料可例如由α松油醇制成。包含金属颗粒的浆料可例如从Coocson Electronic(产品名称：N1000)、AdvancedNano-Particles(ANP)、Harima Chemicals(产品名称：NPS-H和NHD-1)或NBE Technologies(产品名称：NBE Tech)这些公司购得。金属颗粒可例如由银、金、铜、锡或镍制成。金属颗粒的线度(extension)(平均直径)可小于100nm，并且特别地小于50nm或10nm。这些浆料在本领域中也被称为纳米浆料。
在另一实施例中，可通过导电粘合剂，即包含金属颗粒的聚合物浆料来实现接合层28。如以下将更详细地解释的那样，这些种类的浆料可通过与纳米浆料相同的技术来涂覆。在导电粘合剂中，聚合物材料通常是可在施加热量和/或压力时固化的树脂。
包含散布在聚合物液体中的金属颗粒的浆料的涂覆可通过举例来说诸如模版印刷(stencil printing)、丝网印刷、墨喷印刷的印刷技术来执行。用于浆料的涂覆的其他技术，举例来说诸如点涂技术也是有可能的。所有这些技术同样地允许小且可控的量的浆料材料(导电粘合剂或纳米浆料材料)在第三电极垫26的表面上的涂覆。
在涂覆接合层28(例如扩散焊料或导电粘合剂或纳米浆料或直接沉积的颗粒)之后，可使接合层28经受温度上升。如果接合层28由扩散焊料制成，则可施加在大约180至400℃的范围内的温度，以在电极垫26、接合层28的焊接材料与第一结构化金属层14之间形成金属间相。施加的温度可显著低于扩散焊料的金属的熔化温度(当在宏观尺寸上被提供时)。施加的温度优选地应相对低，例如350℃或350℃以下，以便防止载体10的绝缘层12的任何可能的损坏。
如果接合层28由包含金属颗粒的浆料制成，则可施加在100与300℃之间的范围内的，并且特别地在100与200℃之间的范围内的温度，而这样的温度可证明是足够的。如果浆料是导电粘合剂，则这个温阶(temperature step)使聚合树脂固化。如果浆料是所谓的纳米浆料，则这个温阶使包含有金属颗粒的聚合物液体蒸发并且使所述颗粒聚结(coalescent)和烧结。在这种情况下，图1C所示的金属接合层28是由具有如上所述的大小的、烧结的金属颗粒制成的金属接合层。在两种情况下(导电粘合剂的浆料或纳米浆料)，施加的温度可显著低于制做金属颗粒的金属的熔化温度(当在宏观尺寸上被提供时)。为了制造接合层28，载体12和半导体芯片20的组件可通过加热板加热或可被放置在烘箱中。
此外，还有可能通过直接涂覆金属颗粒(而不用浆料)且然后烧结所涂覆的裸金属颗粒来提供由烧结的金属颗粒制成的接合层28。应注意的是，由烧结的金属颗粒制成的接合层28的电导率通常高于由导电粘合剂制成的接合层28(其中金属颗粒被嵌入固化的树脂而不是被烧结)的电导率。
在所有情况下，即如果接合层28由扩散焊料、导电粘合剂、纳米浆料或直接沉积的裸金属颗粒制成，则接合层28可具有从1至10μm的范围内的、从1至5μm的范围内的并且更特别地从1至3μm的范围内的厚度d。特别地，接合层28的厚度d可小于2μm。小的厚度d的接合层28有助于通过接合层28的热量传递，并因此允许在半导体芯片20中产生有效的排热。可通过对用于接合层28的金属材料(扩散焊料中的金属材料或导电粘合剂、纳米浆料中的金属颗粒的金属材料或直接沉积的金属颗粒的金属材料)的选择来进一步改善排热。在所有情况下，包括Au、Ag、Cu和/或Sn的材料由于它们的高热导率而可以是优选的。
如图1D所示，然后涂覆第一绝缘层30以覆盖在载体12和半导体芯片20上面。在一个实施例中，第一绝缘层可以是在压力或热量之下被涂覆的、未固化的树脂的预浸料坯(即纤维增强)树脂层或颗粒增强树脂层。第一绝缘层30可在环氧、聚酯或其他塑料材料的基础上由已知的预浸料坯材料制成，例如棉纸增强环氧材料、玻璃布增强环氧材料、磨砂玻璃(matte glass)增强聚酯材料、玻璃布增强聚酯材料等。在另一实施例中，第一绝缘层30可由热塑性材料制成。
第一绝缘层30可以是具有与载体10大致相同的横向尺寸的箔。在层叠期间，所述箔液化并将半导体芯片20和/或其他拓扑结构封装在载体10上。在层叠之后，第一绝缘层30的顶部表面是大致平整或平面的，即实际上不在第一绝缘层下方再现所述拓扑结构。因此，载体10和安装在其上的半导体芯片20的布置无空隙地完全被绝缘层30覆盖并被嵌入该绝缘层。图1D所示的结构可以是包括安装在载体10上的裸的嵌入半导体芯片20的多层PCB，其中载体10本身为PCB。
半导体芯片20的厚度可小于100μm，并且特别地小于60乃至50或30μm。第一绝缘层30的厚度可小于200μm，或者特别地大约或小于100μm。应注意的是，如果使用举例来说诸如软焊料凸块的常规的接合层，则由于这样的软焊料凸块的厚度通常为大约50μm或50μm以上，所以不能实现例如大约100μm或100μm以下的小厚度的绝缘层30。因此，正是接合层28的小且可控的厚度d允许使用小到例如100μm或100μm以下的厚度的第一绝缘层30。
在制造工艺的随后的阶段中，在第一绝缘层30的顶部表面中形成开口32a、32b、32c。可例如通过常规打孔、激光打孔、化学蚀刻或任何其他适当的方法来产生开口32a、32b、32c。开口32a、32b、32c的宽度可例如在从20至300μm的范围内。如图1E所示，可形成开口32a以暴露电极垫22的区域，可例如形成多个开口32b以暴露电极垫24的区域，并且可形成开口32c以暴露第一结构化金属层14的焊盘或迹线。开口32a、32b、32c在本领域中被称为通孔(垂直互连通路)或贯穿连接(through-connection)。
如图1F所示，然后可用导电材料来填充开口32a、32b、32c。例如，可通过水电镀(galvanic plating)或无电镀技术使开口32a、32b、32c导电。作为结果，在第一绝缘层30的顶部表面上产生第二结构化金属层40。此外，还有可能用包含金属颗粒的浆料来填充开口32a、32b、32c。这种导电浆料也可被用于在电极垫22、24或第一结构化金属层14与第二结构化金属层40之间形成电接触。这样，栅极接触部22和源极接触部24可向上与第二结构化金属层(箔)40接触，源极接触部24可向下与第一结构化金属层(箔)14的迹线或焊盘接触，而漏极接触部26可接合至第一结构化金属层14的另一迹线或焊盘。
应注意的是，在将第一绝缘层30层叠在载体10上之前，第二结构化金属层40可能已附接至第一绝缘层30。在这种情况下，可在层叠步骤之前或之后完成第二结构化金属层40的构造。此外，可在开口32a、32b、32c的填充之前、期间或之后通过例如水电镀来增强(reinforce)第二结构化金属层40。
作为前述方法的另外的变化，应注意的是，在将半导体芯片20附接至载体10之前，不一定必须将接合层28的材料涂覆于半导体芯片20的电极垫26。还有可能将接合层28的材料涂覆于第一结构化金属层14的(一个或多个)指定区域且然后将半导体芯片20放置在涂有接合层28的材料的区域上。在这种情况下，可将与如上所述的相同技术用于将接合层28的材料沉积到第一结构化金属层14的(一个或多个)指定区域上。
应注意的是，将浆料材料或直接沉积的金属颗粒或扩散焊料用于接合层28允许具有高度共面性的上下外表面的的层叠型电子器件的产生。这种高度共面性有助于图1E和1F所示的步骤，即形成开口32a、32b、32c和用导电材料填充开口32a、32b、32c。此外，当将器件100电连接并实现到最终设备中时，层叠型电子器件100的高度共面性有益于用户。在这个背景下，应注意的是，例如由软焊料凸块制成的常规的接合层28通常在层叠型电子器件100的厚度上引起强烈变化。
图2A至2E示意制造层叠型电子器件200的另一实施例的各个阶段。不言而喻，上述技术、材料和方法也可应用于以下结合图2A至2E进一步解释的方法和器件。在这个背景下，为了避免重复，对以上说明进行参考。
如图2A所示，载体110可包括绝缘层112，其可类似于第一实施例的绝缘层12并可由与第一实施例的绝缘层12相同的材料制成。绝缘层112被夹在第一(上部)结构化金属层114与第三(下部)结构化金属层115之间。第一与第三结构化金属层114、115可由与第一实施例的第一结构化金属层14相同的材料制成。换句话说，载体110可例如表示在两侧都具有结构化金属层的PCB。
类似于第一实施例(图1A至1F)，可通过去除不需要的金属，例如通过蚀刻或其他技术来去除不需要的金属而实现第一(上部)和第三(下部)结构化金属层114、115的图形化，仅将所需的金属迹线或焊盘留在载体110上。可使用诸如丝网印刷、光刻、PCB铣削的所有常见的减成方法。此外，还有可能使用加成工艺以使上部和下部结构化金属层114、115图形化。加成工艺通常为电镀工艺，其中在未被遮蔽的区域中将铜或另一金属材料镀在绝缘层112上。
如图2A所示，上部结构化金属层114的图形化的区域或迹线114a、114c、114d可电连接或热连接至下部结构化金属层115的图形化的区域或迹线115a、115b、115c、115d。可通过常规打孔、激光打孔等来制作导电贯穿连接或通孔并通过所述孔的贯穿电镀(plating-through)产生导电贯穿连接或通孔。这样，分别使迹线114a与115a、114c与115c、114d与115d电互连。迹线114a与115b没有电互连，但经由热通孔117热耦合。可通过本领域已知的任何适当的方法来产生热通孔117。热通孔117是被填充以高热导率的材料，例如金属材料的孔。然而，热通孔117中的金属材料与传导迹线114a、115b中的一个或两者分开，以便防止这些迹线114a、115b电互连。
如图2B所示，半导体芯片120_1、120_2和120_3附接至载体110的两侧。第一和第二半导体芯片120_1和120_2可以是功率MOSFET，而第三半导体芯片120_3可以是逻辑IC。第一半导体芯片120_1在载体110的上侧(upper side)附接至第一结构化金属层114，而第二半导体芯片120_2在与所述上侧相对的、载体110的下侧(lower side)附接至第三结构化金属层115。半导体芯片120_1和120_2两者都可以是垂直功率器件。因此，举例来说，第一半导体芯片120_1的栅电极垫122可电连接至上部结构化金属层114的迹线114a，而第一半导体芯片120_1的源电极垫124可连接至上部结构化金属层114的迹线114c。对于第二半导体芯片120_2，漏电极垫126可连接至下部结构化金属层115的迹线115c。
在每种情况下，都通过接合层128来实现结构化金属层114、115与电极垫122、124、126之间的电接触。接合层128对应于第一实施例的接合层28。因此，接合层128的厚度d限于结合第一实施例所描述的范围。此外，接合层128由结合第一实施例所提及的材料中的一种制成。此外，已在第一实施例的背景下描述了接合层128的材料的涂覆方法，并且为简洁起见对这部分说明进行参考。应注意的是，使用小的厚度的接合层128的有益效果在双面***中更明显，在该双面***中两个半导体芯片120_1和120_2被布置在关于载体110的相对位置处。因此，可这样来制造具有高度共面性和均匀性并且跨其横向尺寸具有小且恒定的厚度的多层PCB。
如图2B所示，第三半导体芯片120_3可以是逻辑IC。由于逻辑IC120_3不是垂直器件，所以接合层128没有被用于在第三半导体芯片120_3与下部结构化金属层115之间提供电连接。接合层128被布置在第三半导体芯片120_3的金属基板127与下部结构化金属层115的金属迹线115b之间，并在第三半导体芯片120_3与金属迹线115b之间提供有效的热连接(thermallink)。如图2B所示，多个热通孔117进一步帮助从第三半导体芯片120_3排热。热通孔117可操作用于通过载体110向在载体110的另一(上)侧上的金属迹线114a有效地传递热量。
如图2C所示，然后将第一绝缘层130涂覆于载体110的上侧，而将第二绝缘层150涂覆于载体110的下侧。通过层叠工艺来涂覆第一和第二绝缘层130、150。第一和第二绝缘层130、150可具有与以上对于第一实施例的第一绝缘层30所描述的相同的设计，并可由与以上对于第一实施例的第一绝缘层30所描述的相同的材料制成。此外，与以上对于第一绝缘层30所描述的相同的工艺可被用于将第一和第二绝缘层130、150固定于载体110(例如双面PCB)。如图2C所示，半导体芯片120_1、120_2和120_3无空隙地被嵌入第一和第二绝缘层130、150的材料并被该材料覆盖。由于第一和第二绝缘层130、150的聚合物材料在层叠期间的塑性，所以该聚合物材料填充载体110的两侧上的所有间隙或拓朴结构。
在随后的工艺步骤中，在第一和第二绝缘层130、150的外表面中形成开口132a、132b、132c、132d和132e，参见图2D。开口132a、132b和132c分别类似于第一实施例的开口32a、32b和32c，并对第一实施例的说明进行参考以避免重复。在第一绝缘层130中产生开口132d以暴露第一半导体芯片120_1的漏电极垫126的多个区域。在第二绝缘层150中形成开口132e以暴露第三半导体芯片120_3(逻辑IC)的电极垫129。
如图2E所示，将第二结构化金属层140涂覆于第一绝缘层130的上部表面，并将第四结构化金属层160涂覆于第二绝缘层150的下部表面。可借助于本领域已知的或上述的任何减成或加成工艺将第二和第四结构化金属层140、160涂覆于第一和第二绝缘层130、150。特别地，可使用用于PCB制作的任何标准工艺。例如，第一和第二绝缘层130、150可以是在被涂覆于载体110的上侧和下侧之前被涂以金属的层。
开口132a、132b、132c、132d、132e被填充以金属。在这种连接下，对第一实施例的对应的说明进行参考。应注意的是，将开口132c中的导电材料与上部和下部结构化金属层140、160的电互连金属迹线或焊盘114d和115d电互联以形成从层叠型电子器件200的一侧延伸至其另一侧的导电贯穿连接。
第二和第四结构化金属层140、160的结构化区域可形成从层叠电子器件200的外部可达到的外部接触元件，并因此可允许形成与半导体芯片120_1、120_2和120_3的电接触。换句话说，第二和第四结构化金属层140、160的结构化区域可形成层叠型电子器件200的外部接线端，或者可形成通向层叠型电子器件200的外部接线端的导体迹线(conductor trace)。
如图2E所示，第一(上部)和第三(下部)结构化金属层114、115、第二结构化金属层140和第四结构化金属层160形成用于使第一、第二和第三半导体芯片120_1、120_2和120_3电互连的布线的部分。更具体地说，将功率MOSFET120_1和120_2的栅电极垫122电连接至逻辑IC120_3的电极垫129。将“低侧(low side)”功率MOSFET120_1的源电极垫124电连接至“高侧(highside)”功率MOSFET120_2的漏电极垫126。经由贯穿连接将“低侧”功率MOSFET120_1的漏电极垫126电连接至第四结构化金属层160的迹线或焊盘160a。将第四结构化金属层160的迹线或焊盘160b电连接至“高侧”功率MOSFET120_2的源电极垫124。因此，迹线或焊盘160a和160b可形成层叠型电子器件200的I/O接线端，在所述I/O接线端之间串联布置两个功率MOSFET120_1、120_2并实现由逻辑IC120_3控制的两个开关。
图2E所示的层叠型电子器件200可表示半桥线路。术语“低侧”和“高侧”指这个已知的线路。应注意的是，所有的半导体芯片120_1、120_2、120_3都完全被嵌入第一和第二绝缘层130、150并被该第一和第二绝缘层130、150覆盖。换句话说，图2E所示的布置可以是带有完全嵌入的半导体芯片120_1、120_2、120_3的多层PCB。术语“多层PCB”在此被用于指在PCB内部包括至少一个结构化金属层114、115的PCB。使用多层PCB的这个定义(即具有至少一个内部结构化金属层的PCB)，可分别将第一和第二实施例的层叠型电子器件100和200设计成嵌有至少一个半导体芯片的多层PCB。
在一个实施例中，第二和/或第四结构化金属层140、160的外部金属迹线可被用于形成与举例来说诸如电容器、电感器或电阻器的无源器件的电接触。参考图3，根据第三实施例的层叠型电子器件300包括附接至第二结构化金属层140的电容器170(或至少一个或多个其他类型的无源器件)。不言而喻，无源器件也可被表面安装至在层叠型电子器件300的下侧处的第四结构化金属层160。除了附加的无源器件之外，层叠型电子器件300类似于第二实施例的层叠型电子器件200，并且为了简洁起见对以上说明进行参考。
在图4中示意了根据第四实施例的层叠型电子器件400。层叠型电子器件400可包括两个半导体芯片120_1和120_3。第一半导体芯片120_1可以是功率MOSFET，而第三半导体芯片120_3可以是逻辑IC。层叠型电子器件400包括载体410。载体410可以是具有绝缘层412和第一结构化金属层414的预结构化的PCB。绝缘层412对应于第一和第二实施例的绝缘层12、112，而第一结构化金属层414对应于第一和第二实施例的第一结构化金属层14、114。载体410可被提供有可被填充(例如电镀)以金属的孔，以产生导电贯穿连接或通孔。
借助于接合层428将第一半导体芯片120_1和第三半导体芯片120_3安装在第一结构化金属层414上。接合层428在设计、材料和尺寸上分别类似于第一和第二实施例的接合层28、128。为了避免重复，对接合层28、128的对应的说明进行参考。
半导体芯片120_1和120_3被嵌入第一绝缘层430并被该第一绝缘层430覆盖。第一绝缘层430对应于第一和第二实施例的第一绝缘层30、130，并以与以上参考绝缘层30、130所描述的相同的方式涂覆。此外，如从图4可见，通过第二结构化金属层440实现层叠型电子器件400的布线，并因此以与以上参考第二实施例所描述的(指在第二绝缘层150上由第四结构化金属层160提供的布线)相类似的方式产生该布线。
在所有前述实施例中，各种绝缘和传导层的厚度可覆盖宽的范围。举例来说并且对普遍性没有限制，结构化金属层(箔)14、114、115、140、160可具有在10至1000μm之间的范围内的厚度，绝缘层12、112、412可具有大约200至3000μm的厚度，而第一和第二绝缘层30、130、150、430可具有仅稍大于结构化金属层14、114、115的厚度、半导体芯片12、120_1、120_2、120_3的厚度与接合层28、128、428的厚度d的和的厚度，并可例如小到100μm，乃至100μm以下。
在图5中示意了根据第五实施例的另外的层叠型电子器件500。类似于第二和第三实施例的层叠型电子器件200和300，层叠型电子器件500的器件实现例如DC-DC电压转换器的半桥线路。层叠型电子器件500包括由图形化的金属片或板514制成的载体510，例如引线框架。载体510包括彼此被间隔512a、512b分开的金属板区域514a、514b、514c。在一个实施例中(在图5中未示出)，间隔512a、512b可被填充以绝缘聚合物材料，例如预浸料坯或颗粒增强的材料。图形化的金属片或板514可具有足够刚性的厚度。因此，载体510与前述实施例的载体10、110、410的不同之处在于，金属板514及其区域514a、514b、514c显著地厚于第一结构化金属层14、114、414。因此，在载体510中，不必将连续的绝缘层12、112、412用作支撑来提供必要的刚度或劲度。载体510不是PCB。
半导体芯片120_1、120_2和120_3被安装在载体510上。如以上所解释的那样，半导体芯片120_1和120_2是垂直功率MOSFET，而半导体芯片120_3是用于控制半导体芯片120_1和120_2的栅电极垫122的逻辑IC。半导体芯片120_1、120_2和120_3的附接经由接合层528(对应于接合层28、128、428)实现，并且已在上文中详细地被描述。如在第二和第三实施例中一样，在半导体芯片120_1和120_2下方的接合层528被用作电连接，而在半导体芯片120_3下方的接合层528仅被用作机械固定装置和热导体。
层叠型电子器件500包括层叠到载体510和半导体芯片120_1、120_2、120_3上的两个堆积的绝缘层530、550。绝缘层530、550两者都可由与以上参考前述实施例所描述的相同的材料制成，并且可根据与以上参考前述实施例所描述的相同的方法来处理。类似于绝缘层30、130、150、430，第一绝缘层530可以是涂有第二结构化金属层540(其对应于结构化金属层40、140、160、440-对这些层的说明进行参考)的预浸料坯或颗粒增强的树脂层。然而，在这个实施例中，第二结构化金属层540是内部金属层。第二绝缘层550覆盖在第二结构化金属层540上面，并可同样地由预浸料坯或颗粒增强的树脂材料来提供。其形成对第三结构化金属层560的支撑，该第三结构化金属层560可形成层叠型电子器件500的外部接线端，或可形成通向层叠型电子器件500的外部接线端的导体迹线。
在图6中示意了根据第六实施例的另外的层叠型电子器件600。层叠型电子器件600包括由图形化的金属片或板614制成的载体610，例如引线框架。载体610包括彼此被间隔分开的金属板区域614a、614b、614c，其中所述间隔被填充以绝缘聚合物材料612a、612b，例如预浸料坯或颗粒增强的树脂层材料。类似于第五实施例，图形化的金属片或板614可具有足够刚性的厚度。为了避免重复，对第五实施例的金属片或板514的说明进行参考。
半导体芯片620_1、620_2和620_3被安装在载体610上。半导体芯片620_1为功率MOSFET，而半导体芯片620_2和620_3为逻辑IC。在这个实施例中，所有半导体芯片620_1、620_2和620_3都是非垂直器件。因此，逻辑IC620_2、620_3的所有电极垫629和功率MOSFET620_1的所有电极垫(栅极垫622、源极垫624和在这个剖视图中不明显的漏极垫)分别被布置在所述半导体芯片的一个主面上。
半导体芯片620_1、620_2和620_3的附接经由接合层628来实现。接合层628对应于以上已详细描述的接合层28、128、428、528。对这部分说明进行参考以避免重复。
类似于第五实施例的层叠型电子器件500，层叠型电子器件600包括层叠到载体610和半导体芯片620_1、620_2、620_3上的两个堆积的绝缘层630、650。绝缘层630、650对应于第五实施例的层530和550，并对层530和550的以上说明进行参考。
第一绝缘层630可涂有第二结构化金属层(其对应于第二结构化金属层40、140、160、440、540-对这些层的说明进行参考)。类似于第二结构化金属层540，第二结构化金属层是内部金属层。第二绝缘层650覆盖在第二结构化金属层上面，并形成对第三结构化金属层660的支撑，该第三结构化金属层660可形成层叠型电子器件600的外部接线端，或者可形成通向层叠型电子器件600的外部接线端的导体迹线。
另外，虽然可能仅参考若干实现中的一个公开了本发明的实施例的具体特征或方面，但如可能所期望的和对于任何给定或具体的应用有利的那样，这样的特征或方面可与其他实现的一个或多个其他特征或方面结合。举例来说，不同的载体110(例如双面PCB)、410(例如单面PCB)、510(例如引线框架)、610(例如填充以聚合物的引线框架)可与在各种实施例中公开的任何线路或层叠型层堆叠结合。此外，就在详细说明或权利要求中使用的术语“包括”、“具有”、“带有”或它们的其他变化而言，这样的术语意在以类似于术语“包含(comprise)”的方式包括。此外，应理解的是，本发明的实施例可在分立的电路、部分集成的电路或完全集成的电路或编程装置中实现。此外，术语“示例性”的意思仅是作为示例，而非最佳或最优。还应理解的是，为了理解的简单和容易起见，在此描绘的特征和/或元件以相对于彼此的具体尺寸被示意，而实际尺寸可大体上与在此所示意的不同。
尽管已在此示意并描述了特定的实施例，但本领域的技术人员应理解的是，各种替代的和/或等价的实现可代替所示出并描述的特定的实施例而不背离本发明的范围。本申请意在包含在此讨论的特定的实施例的任何调整或变化。因此，意图在于本发明仅受权利要求及其等同的限制。

Claims (28)

1.一种层叠型电子器件，所述层叠型电子器件包括：
第一半导体芯片，所述第一半导体芯片限定第一主面和与所述第一主面相对的第二主面，并在所述第一主面上具有至少一个电极垫；
载体，所述载体限定第一主表面和与所述第一主表面相对的第二主表面，所述载体在所述第一主表面处包括第一结构化金属层，所述第一结构化金属层经由导电材料的第一接合层接合至所述电极垫，其中所述第一接合层具有小于10μm的厚度；
第一绝缘层，所述第一绝缘层覆盖在所述载体的第一主表面和所述第一半导体芯片上面；以及
所述第一半导体芯片在所述第二主面上具有至少一个电极垫；
第二结构化金属层，所述第二结构化金属层覆盖在所述第一绝缘层上面；并且
至少第一贯穿连接，所述至少第一贯穿连接从所述第二结构化金属层延伸至所述第一半导体芯片的第二主面上的电极垫。
2.根据权利要求1所述的层叠型电子器件，其中，
所述第一接合层具有小于3μm的厚度。
3.根据权利要求1所述的层叠型电子器件，其中，
所述第一接合层由扩散焊料制成。
4.根据权利要求1所述的层叠型电子器件，其中，
所述第一接合层由彼此电接触的金属颗粒制成。
5.根据权利要求4所述的层叠型电子器件，其中所述金属颗粒被烧结和/或被嵌入聚合物材料。
6.根据权利要求1所述的层叠型电子器件，其中
所述第一绝缘层为层叠型纤维增强热固性树脂层或层叠型颗粒增强热固性树脂层或未填充的层叠型热固性树脂层或者填充或未填充的热塑性树脂层中的至少一种。
7.根据权利要求1所述的层叠型电子器件，其中
所述载体为印刷电路板。
8.根据权利要求1所述的层叠型电子器件，其中
所述载体为引线框架。
9.根据权利要求1所述的层叠型电子器件，所述层叠型电子器件还包括：
第二半导体芯片，所述第二半导体芯片限定第一主面和与所述第一主面相对的第二主面，并在所述第二主面上具有至少一个电极垫；
在所述载体的第二主表面处的第三结构化金属层，所述第三结构化金属层经由导电材料的第二接合层接合至所述第二半导体芯片的电极垫，其中所述第二接合层具有小于10μm的厚度。
10.根据权利要求9所述的层叠型电子器件，其中，所述第二接合层具有小于3μm的厚度。
11.根据权利要求9或10所述的层叠型电子器件，所述层叠型电子器件还包括：
第二绝缘层，所述第二绝缘层覆盖在所述载体的第二主表面和所述第二半导体芯片上面。
12.根据权利要求11所述的层叠型电子器件，其中
所述第二半导体芯片在所述第一主面上具有至少一个电极垫；
第四结构化金属层覆盖在所述第二绝缘层上面；并且
至少第二贯穿连接从所述第四结构化金属层延伸至所述第二半导体芯片的第一主面上的电极垫。
13.根据权利要求12所述的层叠型电子器件，其中
所述第二绝缘层为层叠型纤维增强热固性树脂层、层叠型颗粒增强热固性树脂层或未填充的层叠型热固性树脂层或者填充或未填充的热塑性树脂层中的至少一种。
14.根据权利要求1所述的层叠型电子器件，其中
所述第一半导体芯片为功率晶体管。
15.根据权利要求9或10所述的层叠型电子器件，其中
所述第二半导体芯片为功率晶体管。
16.一种具有嵌入芯片的多层印刷电路板，所述多层印刷电路板包括：
印刷电路板，所述印刷电路板具有介电衬底和布置在所述介电衬底的第一主表面上的第一结构化金属层；
第一半导体芯片，所述第一半导体芯片经由第一接合层接合至所述第一结构化金属层，所述第一接合层由彼此电接触的金属颗粒或扩散焊料制成；
第一绝缘层，所述第一绝缘层覆盖在所述第一结构化金属层和所述第一半导体芯片上面；以及
第二结构化金属层，所述第二结构化金属层覆盖在所述第一绝缘层上面；并且
至少第一贯穿连接，所述至少第一贯穿连接从所述第二结构化金属层延伸至所述半导体芯片的远离第一接合层的主面上的电极垫。
17.根据权利要求16所述的多层印刷电路板，所述多层印刷电路板还包括：
第三结构化金属层，所述第三结构化金属层被布置在所述介电衬底的与所述第一主表面相对的第二主表面上；
第二半导体芯片，所述第二半导体芯片经由第二接合层接合至所述第三结构化金属层，所述第二接合层由彼此电接触的金属颗粒或扩散焊料制成；以及
第二绝缘层，所述第二绝缘层覆盖在所述第三结构化金属层和所述第二半导体芯片上面。
18.根据权利要求16所述的多层印刷电路板，其中
所述第一半导体芯片为垂直器件。
19.根据权利要求17所述的多层印刷电路板，其中
所述第二半导体芯片为垂直器件。
20.一种制造层叠型电子器件的方法，所述方法包括：
提供载体，所述载体限定第一主表面和与所述第一主表面相对的第二主表面，所述载体在所述第一主表面处包括第一结构化金属层；
提供第一半导体芯片，所述第一半导体芯片在其第一主面上具有至少一个电极垫并且在与第一主面相对的第二主面上具有至少一个电极垫；
经由导电材料的第一接合层使所述第一结构化金属层接合至所述第一主面上的所述电极垫，其中所述第一接合层具有小于10μm的厚度；
形成第一绝缘层，所述第一绝缘层覆盖在所述载体的第一主表面和所述第一半导体芯片上面；
形成覆盖在所述第一绝缘层上面的第二结构化金属层；并且
形成从所述第二结构化金属层延伸至所述第一半导体芯片的第二主面上的电极垫的至少第一贯穿连接。
21.根据权利要求20所述的方法，其中，所述第一接合层具有小于3μm的厚度。
22.根据权利要求20或21所述的方法，所述方法还包括：
将扩散焊接材料溅射在所述电极垫上以建立所述第一接合层。
23.根据权利要求20或21所述的方法，所述方法还包括：
将扩散焊接材料电流沉积在所述电极垫上以建立所述第一接合层。
24.根据权利要求20或21所述的方法，所述方法还包括：
将包括嵌入聚合物材料的金属颗粒的浆料印刷在所述第一结构化金属层上以建立所述第一接合层。
25.根据权利要求24所述的方法，所述方法还包括：
加热所述浆料使得所述聚合物材料固化或使得所述聚合物材料蒸发而所述金属颗粒烧结。
26.根据权利要求20或21所述的方法，所述方法包括：
通过在所述载体的第一主表面和所述第一半导体芯片上层叠纤维增强热固性树脂层或颗粒增强热固性树脂层或未填充的层叠型热固性树脂层或者填充或未填充的热塑性树脂层来形成所述第一绝缘层。
27.根据权利要求20或21所述的方法，其中所述载体在所述第二主表面处包括第三结构化金属层，所述方法包括：
提供第二半导体芯片，所述第二半导体芯片在其第二主面上具有至少一个电极垫；
经由导电材料的第二接合层使所述第三结构化金属层接合至所述第二半导体芯片的电极垫，其中所述第二接合层具有小于10μm的厚度；以及
形成第二绝缘层，所述第二绝缘层覆盖在所述载体的第二主表面和所述第二半导体芯片上面。
28.根据权利要求27所述的方法，其中，所述第二接合层具有小于3μm的厚度。
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