CN101290930A - 包含半导体芯片叠层的半导体器件及其制造方法 - Google Patents

包含半导体芯片叠层的半导体器件及其制造方法 Download PDF

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Publication number
CN101290930A
CN101290930A CNA2008101092999A CN200810109299A CN101290930A CN 101290930 A CN101290930 A CN 101290930A CN A2008101092999 A CNA2008101092999 A CN A2008101092999A CN 200810109299 A CN200810109299 A CN 200810109299A CN 101290930 A CN101290930 A CN 101290930A
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semiconductor device
semiconductor chip
semiconductor
chip
adhesion
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CN101290930B (zh
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K·霍塞尼
J·马勒
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Infineon Technologies AG
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Infineon Technologies AG
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
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Abstract

包含半导体芯片叠层的半导体器件及其制造方法。本发明涉及包含半导体芯片叠层(1)的半导体器件(10)及其制造方法。半导体器件(10)包括作为半导体芯片叠层(1)的基底的至少一个下部半导体芯片(2)和至少一个上部半导体芯片(3)。绝缘中间片(4)设置在半导体芯片(2，3)之间。此外，连接元件(6)用线将半导体芯片(2，3)、中间片(4)和外部端子(7)彼此连接。

Description

包含半导体芯片叠层的半导体器件及其制造方法
技术领域
本发明涉及包含半导体芯片叠层的半导体器件及其制造方法。这种类型的半导体器件具有作为半导体芯片叠层的基底的至少一个下部半导体芯片和至少一个上部半导体芯片。在这种情况中，半导体芯片是直接一个堆叠在另一个顶上。在这种类型的传统堆叠情况中，必须确保在堆叠期间，半导体芯片的各个电势有效地彼此绝缘。
背景技术
这种电绝缘不利于热传导。因此，作为例子，借助于绝缘粘合剂将逻辑芯片固定在晶体管之上，该绝缘粘合剂不利地影响热传导率。这是因为作为通过粘合剂结合施加上部堆叠的半导体芯片的结果，在下部半导体芯片的顶侧形成增加的热阻，该下部半导体芯片形成基底。最后，上部半导体芯片的尺寸不利地受其面积范围的限制，因为它不能伸出超过下部半导体芯片的边缘而不增加半导体芯片叠层破裂的风险。
此外，作为半导体芯片粘附地结合到彼此之上以形成半导体芯片叠层的结果，在成本方面，粘附地结合到彼此之上的半导体芯片的电极之间的再分布布线，即下部半导体芯片的顶侧上的那些和上部半导体芯片的后侧上的那些，不可能没有相当大的费用。因此，在顶侧和后侧上具有电极的功率半导体芯片不能借助于粘接结合技术令人满意地堆叠起来。在这种类型的半导体芯片的情况中，电极只能是相同类型的且面积相等，也就是说，是一致的，以便借助导电粘合剂粘接地结合于彼此之上，使得就电路而言仅有限的功能可以借助堆叠来实现。
此外，在“晶片级封装技术”的情况下，可以通过直通接触将两个复合片与相应嵌入的半导体芯片以及与在共平面顶侧上的布线结构电连接，以这种方式使得产生包括半导体芯片叠层的半导体器件，其半导体芯片通过垂直直通接触和水平布线结构彼此电线接。即使改善了布线可能性，由于半导体芯片叠层的热绝缘，对于堆叠功率半导体芯片来说，这种半导体芯片的堆叠也是不利的。
此外，可以制造多层陶瓷基板，其可在两侧配备有半导体芯片，使得半导体芯片的产生热损失的顶侧在基板片的两侧上被暴露并且可以散热。然而，这需要具有高的材料费用的基板技术。
最后，也可以提供在其将要被连接到的区域上具有金属化和绝缘层的序列的半导体芯片，并且于是将它们粘接地结合于彼此之上。尽管这提供了复杂布线的可能性，但是热效应严重并且对功率半导体器件不利。
发明内容
本发明涉及包含半导体芯片叠层的半导体器件及其制造方法。该半导体器件具有半导体芯片叠层，该半导体芯片叠层具有作为半导体芯片叠层的基底的至少一个下部半导体芯片和至少一个上部半导体芯片。在半导体芯片之间设置绝缘中间片。此外，连接元件使半导体芯片、中间片和半导体器件的外部端子彼此电连接。在这种情况中，该半导体器件在其下侧具有可表面安装的外部接触。
现在将参考附图更详细的解释本发明。
附图说明
图1示出通过本发明的一个实施例的半导体器件的示意性截面图；
图2至图9示出在其制造期间根据图1的半导体器件的部件的示意图；
图2示出对于半导体芯片叠层通过上部半导体芯片的示意性截面图；
图3示出对于半导体芯片叠层通过下部半导体芯片的示意性截面图；
图4示出通过中间片的坯件的示意性截面图；
图5示出通过涂敷根据图4的坯件之后的中间片的示意性截面图；
图6示出通过半导体芯片叠层的示意性截面图，该半导体芯片叠层具有根据图2和3的半导体芯片和根据图5的中间片；
图7示出通过半导体器件载体的半导体器件位置的示意性截面图；
图8示出通过施加根据图6的半导体芯片叠层之后的根据图7的半导体器件载体的示意性截面图；
图9示出安装连接元件后的通过根据图8的半导体器件载体的示意性截面图；
图10示出通过本发明的另一实施例的半导体器件的示意性截面图；
图11示出通过本发明的另一实施例的半导体器件的半导体芯片叠层的示意性截面图；
图12示出通过施加连接元件之后的根据图11的半导体芯片叠层的示意性截面图；
图13示出通过根据本发明的另一实施例的半导体器件的示意性截面图；
具体实施方式
图1示出通过本发明的一个实施例的半导体器件10的示意性截面图。该半导体器件10具有半导体芯片叠层1，该半导体芯片叠层1具有至少一个下部半导体芯片2和堆叠在其上的上部半导体芯片3。在半导体芯片2和3之间设置中间片4，所述中间片在其顶侧9具有导电涂层5。
中间片5可以是陶瓷片。陶瓷片具有其热导率比堆叠半导体芯片2和3的热导率大的优势，因此，通过陶瓷中间片4，下部半导体芯片2中产生的热消耗可通过中间片4和上部半导体芯片3消散。也可以使中间片4比下部半导体芯片2的面积范围所允许的大。
此外，中间片4可以是塑料片。这种作为中间片4的塑料片可具有来自聚酰亚胺、高温热塑性塑料、聚苯并环丁烯或聚苯并噁唑或其混合物的组的物质。这种类型的塑料片可在一侧上配有电镀，所述电镀构成导电涂层。例如，也可图案化所述电镀以为连接元件6提供接触焊盘13并且为上部半导体芯片3提供接触焊盘14。以这种方式图案化所述导电涂层5使得其在中间片4的顶侧9上形成布线结构24。
在这个半导体器件10的示意性截面图中，连接元件6是结合线，并且例如使中间片4的顶侧9上的接触焊盘13连接至上部半导体芯片3的顶侧28上的接触区域27，其借助于其后侧29被固定在中间片4的顶侧9上的布线结构24的接触焊盘14上。
用于半导体芯片3的中间片4的接触区域14的材料和上部半导体芯片3的后侧29之上的涂层34可以这种方式彼此协调：扩散焊料连接是可能的。在这种类型的扩散焊料连接情形中，在扩散焊接期间，形成金属间相，其具有比扩散焊料的成分的熔点高的熔点。在下部半导体芯片2的顶侧15上的用于固定中间片4的可焊接涂层16也可具有扩散焊料层18，其与中间片的下侧31上的电镀8反应。用于可焊接涂层16和接触焊盘14的扩散焊料层18具有优势：由半导体芯片2和3以及在之间设置的中间片4构成的叠层1具有高热稳定性并且因而经得住在这种类型的半导体器件10的制造期间的后续处理温度，而不会被损坏。扩散焊料层18用于其中最初完成半导体芯片叠层1并且然后打算将半导体芯片叠层1固定为例如在半导体器件载体22上的半导体芯片叠层1的区域中。
然而，如果提供与此不同的方法步骤序列，那么可能有利于在半导体器件载体22的芯片岛21与下部半导体芯片2的后侧32之间提供扩散焊料连接，于是有利于施加中间片4并且最后有利于施加半导体芯片叠层1的上部半导体芯片3。在这种情形中，有利于提供第一焊料层17作为扩散焊料层18并且有利于通过软焊料层在中间片4和下部半导体芯片2之间完成第二固定并且最后有利于通过导电粘合剂在堆叠半导体芯片3和中间片4之间具体实现最高固定层，因此在制造工序中，粘合连接部产生温度梯度并且其确保在制造工序期间焊料和粘合剂连接部不彼此损害。
因此，在制造半导体器件的一个形式的实施方式中，设有多个用于芯片固定和用于连接元件固定的互相电绝缘的金属区域的图案化薄陶瓷或聚合物片被施加至下部半导体芯片2的顶侧15。为了通过扩散焊接或软焊接粘合地连接这种中间片4，由例如Ag、Au、Pd或PdAu构成的可焊接表面金属化作为最顶层施加至下部半导体芯片的顶侧，而陶瓷或聚合物片的下侧具有例如由Cu、Ag、Ni或NiPdAu构成的金属电镀。
于是可通过导电或绝缘粘合剂或焊料施加一个或多个上部半导体芯片3至电绝缘中间片4。在金属焊料连接的情况下，陶瓷或聚合物中间片的顶侧于是也同样具有例如由Cu、Ag、Ni或NiPdAu构成的金属电镀。结果，具有垂直电流的功率半导体芯片，其芯片后侧构成漏极端子，例如，也可彼此电绝缘并且一个施加在另一个之上，因此导致“芯片堆叠”或“芯片上芯片”(chip on chip)结构。
另外，例如，在绝缘中间片4和/或下部半导体芯片上，在上部半导体芯片3和布线结构24的金属化区域之间，可通过金属线路实现电连接。而且，可以为下部半导体芯片2上的更多的上部半导体芯片3提供链接区域，所述链接区域显著地大于下部半导体芯片2。因而，用于安装堆叠半导体芯片3的安装区域扩大了。
多种粘着连接部可能在半导体器件载体22的芯片岛21和下部半导体芯片2的后侧电极38之间以及同样在下部半导体芯片2的顶侧15和中间片4之间以及同样在中间片4和上部半导体芯片3之间。为了在半导体器件10之内在半导体芯片叠层1的单独元件之间获得最适宜的粘着连接，半导体器件的设计者可在焊料层、扩散焊料层、绝缘粘接层和导电粘接层之间选择。
此外，可表面安装的外部接触设置在半导体器件10的下侧上并且嵌入塑料外壳结构中，远离作为外部端子7的外部接触区域。为此目的，外部接触由引线框架的引线25构成并且具有用于下部半导体芯片2的芯片岛21，其中芯片岛21和引线25可并入外部端子7。
图2至9示出在其制造期间根据图1的半导体器件10的各部件的示意图。
图2示出对于半导体芯片叠层通过上部半导体芯片3的示意性截面图。这种类型的半导体芯片3可以是功率半导体器件或具有控制功能的集成电路或逻辑元件并且也可以是存储元件。这种类型的半导体芯片3由半导体晶片制造，其中在半导体晶片上以行和列设置多个半导体芯片位置。
这种类型的半导体芯片3由单晶半导体材料制造并且具有不同的掺杂半导体区，其可以实现实际的开关、控制、逻辑或存储功能。所述半导体区连接至接触区域27，所述接触区域27安排在半导体芯片3的上侧28或是作为后侧电极33安排在上部半导体芯片3的后侧29上。
图3示出了通过用于半导体芯片叠层的下部半导体芯片2的示意性截面图。在该制造方法中，提供具有图3的由硅构成的下部半导体芯片2，其顶侧15和后侧32具有比将要堆叠的半导体芯片3大的面积范围，其在图2中示出。用于半导体芯片叠层的基底半导体芯片的半导体芯片2的厚度也大于上部半导体芯片3的厚度，如由图2示出的。
在下部半导体芯片2的顶侧15上，在边缘区域中安排接触区域27，所述接触区域使得能与上部半导体芯片连接以及与具有连接元件包括物的半导体器件的外部端子连接。功率半导体器件也可用作下部半导体芯片2以及用作上部半导体芯片。为了使下部半导体芯片2连接至上部半导体芯片，在下部半导体芯片2的顶侧15提供金属化，该金属化可具有例如用于扩散焊接层的金属。与软焊接层或粘接层相比，这种类型的扩散焊接层具有较高热稳定性的优势。根据包括半导体芯片叠层的本发明，半导体器件的制造不仅仅需要两个半导体芯片2和3，而且，需要另外的中间片，如图4示出的。
图4示出通过中间片4的坯件26的示意性截面图。这种类型的坯件26可由陶瓷制造，例如，为了该目的，首先形成生坯(green body)，其随后在高热工序中收缩以形成烧结陶瓷。而且，为了可以制造坯件26的精确顶侧9和后侧31，习惯于从烧结的陶瓷块用锯切割这样的陶瓷片来用做中间片4。在这种情况中，这种陶瓷坯件的厚度大约是0.5mm。
此外，可以由塑料制造这种坯件26，其中作为塑料来自聚酰亚胺、高温热塑性塑料、聚苯并环丁烯或聚苯并噁唑或其混合物的组的物质用作中间片4的坯件26的材料。随后提供导电层给坯件26。
图5示出通过将图4的坯件26涂敷了之后的中间片4的示意性截面图。布线结构24施加到坯件26的顶侧9上，该布线结构由图案化的电镀形成。为了该目的，首先执行无电镀化学或电解金属沉积。在电解金属沉积中，有必要使陶瓷片的表面变得导电。为此目的，例如，通过溅射方法施加导电种子层(seed layer)并且所述导电种子层随后被接触连接。然后，在电解槽中，沉积封闭的涂层，例如，在中间片4的顶侧9上。
随后通过光刻技术图案化该封闭的涂层，该光刻技术包括形成光致抗蚀剂掩模。多种方法用于图案化，优选湿法化学刻蚀或借助等离子体的干法刻蚀。随后去除该光致抗蚀剂掩模，其可借助于等离子体灰化或借助溶剂实现。该图案化在坯件26的顶侧9上产生布线结构24，其可随后用作至上部半导体芯片的固定或粘着连接或用作连接元件的固定。为此目的，示出的布线结构24具有用于连接元件的接触焊盘13和用于半导体芯片的接触焊盘14。
图6示出通过根据图2和3的具有半导体芯片2和3的半导体芯片叠层1和根据图5的中间片4的示意性截面图。可以多种方式完成在半导体芯片叠层1的三个部件之间的粘着连接；因而可以通过由扩散焊接材料构成的可焊接涂层16，制造与电镀8相互作用的扩散焊料层18，因此下部半导体芯片2和中间片4之间的粘着连接具有高的温度稳定性。
用于上部半导体芯片3的以接触焊盘14的形式存在的芯片岛同样可具有可焊接涂层，其中所述涂层优选包括软焊料，因此中间片4和下部半导体芯片2之间的固定不随叠层半导体器件3的施加而恶化。代替软焊料层，该粘着连接也可通过绝缘或通过导电粘接层19实现。
大体上，可以首先制造具有中间层4的耐热半导体芯片叠层1或在该方法的另一示例性实施方式中，首先接连地提供在其上具有芯片岛的半导体芯片载体，首先施加下部半导体芯片1，然后施加中间片4，最后施加上部半导体芯片3并且因此它们被堆叠。
图7示出通过半导体芯片载体22上的半导体器件位置35的示意性截面图，其中该半导体器件载体22可具有多个这种半导体器件位置35。作为外部端子7的中央芯片岛21设置在所述半导体器件位置35中，被引线25包围的所述芯片岛作为外部端子7。
图8示出通过施加根据图6的半导体芯片叠层1之后的根据图7的半导体器件载体22的示意性截面图。在这种情况下，为了不毁坏半导体芯片叠层1的部件之间的粘着连接，整个半导体芯片叠层1，如图6所示，通过导电粘合剂粘附地粘接或通过芯片岛21之上的软焊料焊接。另一方面，半导体芯片叠层1的部件连续地施加在芯片岛21上是可以的。在这种情况下，焊料层17也可以是扩散焊料层以产生耐热粘着连接，其继续(extend)进一步的处理步骤，例如元件的焊接和粘附结合以形成半导体芯片叠层1而不被破坏。
图9示出固定连接元件6后的通过根据图8的半导体器件载体22的示意性截面图。连接元件6的排列是纯示意性的并且不限于示出的截面图。示出的连接元件6仅仅意图表明对于外部端子7和半导体芯片叠层1的各层之间的电连接之间怎样的可能性是可以的。
因此，在上部半导体芯片3的顶侧28上的接触区域27可连接至中间片4上的上部布线结构24，以及，此外，中间片4的布线结构24的接触焊盘13可通过相应的连接元件6连接至下部半导体芯片2的边缘区域中的接触区域27。也可以使上部半导体芯片3直接与引线25的形式的外部端子7接触和/或可以使下部半导体芯片2的接触区域27与作为外部端子7的相应引线25电连接。上部半导体芯片3与下部半导体芯片2的接触区域27也可通过连接元件6彼此连接。
在通过连接元件6完成连接之后，具有半导体芯片叠层1的半导体器件载体22和连接元件6可嵌入塑料外壳结构中，从其突出，同时使它们释放(free)，外部端子7作为半导体器件10的下侧上的可表面安装的外部接触，如图1所示。
图10示出通过本发明的另一实施例的半导体器件20的示意性截面图。具有与在前的附图中相同功能的部件由相同的参考标记标识，并且不再被单独描述。
在根据图10的本发明的该实施例中，粘着连接主要作为半导体芯片载体和半导体芯片叠层1之间的粘着连接并且也在半导体叠层1之内。为此目的，通过导电的或绝缘的连接膏剂(paste)，施加上部半导体芯片3至作为中间片4的在两侧上用铜金属化的陶瓷片上，其也可使用镍或使用镍合金涂覆，其中通过连接膏剂又将中间片4施加至下部半导体芯片2的顶侧。
关于图1中示出的实施例的不同在于此处功率半导体芯片一个堆叠在另一个之上。进一步的差异在于以下事实：中间片4具有比下部半导体芯片2大的面积范围，因此较大的上部半导体芯片3或相同尺寸的半导体芯片3也可堆叠在中间片4上。而且，在两侧上被涂覆的铜镀层不仅形成为顶侧9上的布线结构24，还可在后侧31上被图案化，因此可将其连接至相应合适的下部半导体器件2的电极，例如源电极S2和栅电极G2。下部半导体芯片2的后侧32构成漏电极D2，其可通过半导体器件载体22的芯片岛21被外部接触连接作为漏电极D1。堆叠半导体芯片3同样具有在其后侧29上的漏电极D3和在其顶侧28上的源电极S3和栅电极G3。下部半导体芯片2的栅电极G2和上部半导体芯片3的栅电极G3通过中间片4和其布线结构24彼此电连接。
在本发明的该实施例中，中间片的边缘侧具有导电轨迹(track)，或者通过中间片4提供直通接触。在该实施例中，两个栅电极G2和G3由半导体器件的公共栅极端子G1驱动。然而，假如提供相应的连接元件6，也可以分别驱动两个半导体芯片。两个源电极S3和S2也可以一起路由(route)至半导体器件20的外部源电极S1。只有漏电极D2和D3可被分别访问。为此目的，D3和外部端子之间的连接线不位于此处示出的截面平面中。
图11示出通过本发明的另一实施例的半导体器件30的半导体芯片叠层1的示意性截面图。具有与在前的附图中相同功能的部件由相同的参考标记际识，并且不再被单独描述。
在本发明的该另一实施例中，半导体器件30具有在中间片4上的两个上部半导体芯片11和12，所述半导体芯片彼此并排固定并且实现多种逻辑或存储功能。
为此目的，上部半导体芯片11和12在它们的顶侧28上具有多个接触区域27，所述接触区域可通过连接元件被不同地布线。中间片4通过焊料层设置在下部半导体芯片2的顶侧之上，其预先假定，例如，如由AgAu或PdAu构成的涂层顶侧的金属化，作为下部半导体芯片上的最高涂层，以固定具有小于0.5mm厚度的薄中间片。在这种情况下，所述薄中间片可包括在两侧上使用铜或使用镍或使用其合金涂覆的绝缘材料，如表示为适于“DCB”片(直接铜结合(direct copperbonding))。此处图示的两个上部半导体芯片11和12通过焊料层固定在其上。
图12示出安装连接元件6之后通过根据图11的半导体芯片叠层1的示意性截面图。在此图示中，示出的连接元件6也仅仅意图显示存在什么样的可能性，大体上，用于在彼此之间电连接半导体芯片叠层1的各层和/或电连接至外部端子7或引线25。在此情况下，作为外部端子7的半导体芯片岛21具有比引线25大的金属厚度，为引线25从塑料外壳横向地突出做准备，同时作为冷却区域的芯片岛21的下侧36和外部端子7作为可表面安装的外部接触从塑料外壳突出。
图13示出通过根据本发明的进一步实施例的半导体器件40的示意性截面图。具有与在前的附图中相同功能的部件由相同的参考标记标识，并且不再被单独描述。
在这种情况下，以类似于根据图10的半导体器件20的情况下的方式，功率半导体芯片一个堆叠在另一个之上，其中中间片4具有比下部半导体芯片2大的面积范围。此处，也在中间片4的两侧上提供布线结构24。两个功率半导体芯片11和12设置在中间片4的顶侧9之上，各个情况中的所述功率半导体芯片在它们的顶侧28上具有源电极S3和栅电极G3。
上部半导体芯片11和12的后侧29作为漏极D3固定在中间片4的布线结构24的相应接触焊盘14上。又一次，两个电极，也就是源电极S2和栅电极G2设置在下部半导体芯片2的顶侧15上，所述电极通过相应中间片4的下部布线结构24的导电轨迹电连接至上部半导体芯片11和12的电极。用于上部半导体芯片11和12的高电流承载连接元件37具体实施为在源电极S3上结合在一起的结合带。
参考标记列表
1    半导体芯片叠层
2    下部半导体芯片
3    上部半导体芯片
4    中间片
5    中间片的导电涂层
6    连接元件
7    外部端子
8     电镀
9     中间片的顶侧
10    半导体器件(实施例)
11    中间片上的半导体芯片
12    中间片上的半导体芯片
13    中间片上的用于连接元件的接触焊盘
14    中间片上的用于半导体芯片的接触焊盘
15    半导体芯片的顶侧
16    可焊接涂层
17    焊料层
18    扩散焊料层
19    导电粘接层
20    半导体器件(另一实施例)
21    芯片岛
22    半导体器件载体
23    塑料外壳结构
24    中间片上的布线结构
25    引线
26    中间片坯件
27    接触区域
28    上部半导体芯片的顶侧
29    上部半导体芯片的后侧
30    半导体器件(另一实施例)
31    中间片的下侧
32    下部半导体芯片的后侧
33    上部半导体芯片的后侧电极
34    上部半导体芯片的后侧上的涂层
35    半导体芯片位置
36    芯片岛的后侧
37    高电流连接元件
38    上部半导体芯片的后侧电极
40    半导体器件(另一实施例)
G1    栅电极
G2    栅电极
G3    栅电极
D1    漏电极
D2    漏电极
D3    漏电极
S1    源电极
S2    源电极
S3    源电极

Claims (40)

1、一种半导体器件，包括：
半导体芯片叠层(1)，
作为该半导体芯片叠层(1)的基底的至少一个下部半导体芯片(2)，和
至少一个上部半导体芯片(3)；
设置在半导体芯片(2、3)之间的绝缘中间片(4)，以及
将半导体芯片(2，3)、该中间片(4)和外部端子(7)彼此电连接的连接元件(6)；
其中该半导体器件具有在其下侧上的可表面安装的外部接触。
2、如权利要求1所述的半导体器件，其中该中间片至少在一侧上具有导电的图案化涂层(5)。
3、如权利要求1或2所述的半导体器件，其中该中间片(4)为陶瓷片。
4、如权利要求1或2所述的半导体器件，其中该中间片(4)为塑料片。
5、如权利要求4所述的半导体器件，其中该塑料片包括来自聚酰亚胺、高温热塑性塑料、聚苯并环丁烯或聚苯并噁唑或其混合物的组中的物质。
6、如前述权利要求之一所述的半导体器件，其中该中间片(4)至少在一侧上具有电镀(8)。
7、如权利要求6所述的半导体器件，其中该电镀(8)被图案化。
8、如权利要求6或7所述的半导体器件，其中该电镀(8)包括来自铜、银、镍、钯、镍/钯/金或其合金的组的物质。
9、如前述权利要求之一所述的半导体器件，其中该中间片(4)具有比半导体芯片(2，3)的硅晶体高的热导率。
10、如前述权利要求之一所述的半导体器件，其中该中间片4具有比下部半导体芯片(2)的面积范围大的面积范围。
11、如前述权利要求之一所述的半导体器件，其中在该中间片(4)上多个半导体芯片(11，12)彼此并排地设置。
12、如前述权利要求之一所述的半导体器件，其中该中间片(4)在其顶侧(9)上具有图案化的金属涂层。
13、如权利要求12所述的半导体器件，其中该图案化的金属涂层具有用于连接元件(6)的接触焊盘(13)和用于堆叠的半导体芯片的接触焊盘。
14、如前述权利要求之一所述的半导体器件，其中该下部半导体芯片(2)在其顶侧(15)上具有可焊接涂层(16)。
15、如权利要求14所述的半导体器件，其中该可焊接涂层(16)包括金属层。
16、如前述权利要求之一所述的半导体器件，其中该下部半导体芯片(2)在其顶侧(15)上具有由金、银、钯或钯/金或它们的合金构成的涂层。
17、如前述权利要求之一所述的半导体器件，其中该中间片(4)和半导体芯片(2，3)借助粘着连接固定在彼此之上。
18、如权利要求17所述的半导体器件，其中所述粘着连接中的至少一个包括焊料层(17)。
19、如权利要求17所述的半导体器件，其中所述粘着连接中的至少一个包括扩散焊料层(18)。
20、如权利要求17所述的半导体器件，其中所述粘着连接中的至少一个包括绝缘粘接层。
21、如权利要求17所述的半导体器件，其中所述粘着连接中的至少一个包括导电粘接层(19)。
22、如前述权利要求之一所述的半导体器件，其中所述可表面安装的外部接触设置在半导体器件(10)的下侧上并且嵌入塑料外壳结构中远离外部接触区域。
23、如权利要求22所述的半导体器件，其中所述可表面安装的外部接触具有用于下部半导体芯片(2)的具有芯片岛(21)的引线框架的引线(25)。
24、一种用于制造半导体器件(10)的方法，具有：
在半导体器件载体(22)的芯片岛(21)上，一个在另一个之上地堆叠下部半导体芯片(2)、中间片(4)和至少一个另外的半导体芯片(3)；
在半导体芯片(2，3)彼此之间，将连接元件(6)从半导体芯片(2，3)安装至该中间片(4)，并且安装至该半导体载体(22)上的半导体器件(10)的外部端子(7)；
将该半导体芯片叠层和连接元件嵌入至塑料外壳结构(23)中。
25、一种用于制造多个半导体器件(10)的方法，具有：
提供半导体芯片(2，3)；
提供具有多个半导体器件位置(35)的半导体器件载体(22)；
提供用于半导体器件位置(35)的中间片(4)；
在半导体器件位置(35)中在该半导体器件载体(22)的芯片岛(21)上施加下部半导体芯片(2)；
在该下部半导体芯片(2)上粘着地固定中间片(4)；
在中间片(4)上粘附地安装至少一个另外的半导体芯片(3)以形成半导体芯片叠层(1)；
安装连接元件(6)；
将该半导体芯片叠层(1)和连接元件(6)嵌入至塑料外壳结构(23)中；
将该半导体器件载体(22)分离成单独的半导体器件(10)。
26、如权利要求24或25中的方法，其中中间片(4)至少在一侧上设有图案化的电镀(8)并且为此目的执行在金属种子层上的无电镀化学或电解金属沉积。
27、如权利要求26中的方法，其中溅射方法用于沉积导电种子层。
28、如权利要求26中的方法，其中光刻技术用于图案化该电镀(8)，在该光刻技术中形成光致抗蚀剂掩模。
29、如权利要求28中的方法，其中使用等离子体灰化来去除该光致抗蚀剂掩模。
30、如权利要求28中的方法，其中使用溶剂来去除该光致抗蚀剂掩模。
31、如权利要求28中的方法，其中使用干法刻蚀方法来去除该种子层。
32、如权利要求24-31中的一项所述的方法，其中布线结构(24)施加到中间片(4)。
33、如权利要求24-32中的一项所述的方法，其中使用烧结陶瓷方法来制造中间片(4)。
34、如权利要求24-32中的一项所述的方法，其中为了制造中间片(4)分离烧结的陶瓷块。
35、如权利要求24-34中的一项所述的方法，其中在下部半导体芯片(2)的顶侧(15)上沉积由金、银或钯/金或其合金构成的涂层。
36、如权利要求24-35中的一项所述的方法，其中中间片(4)和半导体芯片(2，3)借助粘着连接一个堆叠在另一个的顶部上。
37、如权利要求36中的方法，其中施加至少一个焊料层(17)作为粘着连接。
38、如权利要求36中的方法，其中施加至少一个扩散焊料层(18)作为粘着连接。
39、如权利要求36中的方法，其中施加至少一个绝缘粘接层作为粘着连接。
40、如权利要求36中的方法，其中施加至少一个导电粘接层(19)作为粘着连接。
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DE102007018914A1 (de) 2008-10-23

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