CN100397612C - 导电无电镀沉积刻蚀停止层、衬垫层及通孔插塞在互连结构中的使用 - Google Patents
导电无电镀沉积刻蚀停止层、衬垫层及通孔插塞在互连结构中的使用 Download PDFInfo
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Abstract
本发明公开了多层互连结构和用于制造所述互连结构的方法。该互连结构可以包含互连线、在互连线上面形成的无电镀沉积金属层、在金属层上面形成的通孔以及在通孔上面形成的第二互连线。通常金属层包含钴或镍合金,并为形成对应于通孔的开口提供刻蚀停止层。金属层可以向下面的互连线提供保护,并可以取代传统的保护性电介质层。金属层是导电的而非电介质,并为通孔和互连线之间的电流通过提供分路。还可以在互连结构中使用类似金属层作为通孔衬垫层与通孔插塞。
Description
技术领域
本发明的实施例涉及互连结构及制造方法。具体而言,这些实施例涉及新型互连结构,所述互连结构包含导电无电镀沉积刻蚀停止层,并且某些情况下包含衬垫层与通孔插塞,还涉及用于制造所述互连结构的新型方法,以及涉及包含所述互连结构的集成电路。
背景技术
许多集成电路包含有多层电互连结构以向诸如位于半导体衬底上的晶体管之类的逻辑元件提供电信号。互连结构通常包含有互连线,所述互连线在电介质材料中近乎共面的布置中彼此分隔,所述电介质材料使这些互连线相互绝缘。通过穿过绝缘材料而形成的通孔,可以实现不同层面的互连线之间的选择连接。
互连线通常用高导电金属或合金制成。部分地因为与其他金属相比铜具有低电阻,它已经成为广泛使用的材料。然而,铜有一个缺点就是其易于氧化。因此,如果铜表面长时期处于暴露状态,或者受到各种刻蚀或等离子清洁操作,则该表面可能被氧化。与诸如铝之类的其他材料不同,铜的氧化并不会形成可以阻止进一步氧化的薄保护覆层,于是铜的很大一部分可能被氧化。这通常不是想要的,因为它可能显著改变互连结构的电和机械属性。铜的另一个缺点在于它容易被许多常用电介质刻蚀化学剂所刻蚀。因此,如果铜表面处于暴露状态,并且没有受到保护,则它可能被氧化或者在后续工艺操作期间被部分清除。
为了减小氧化和铜刻蚀,通常在铜互连线上形成保护性电介质刻蚀停止层或硬掩膜层。为此目的而常用的材料包括氮化硅(SiN)、碳化硅(SiC)和二氧化硅(SiO2)。虽然这些电介质层在保护铜免于反应上可能是有效的,但是它们通常增加了机械隔离而导致集成电路故障,它们还可能增加互连结构的有效电介质常数并导致性能下降。
保护性电介质层提供了额外的材料界面或者连接点,其中来自保护层的机械隔离经常发生起球、断裂或起泡等。这些种类的机械故障可能减小产品的成品率,以及可能降低所制造的集成电路的有效使用期。当把具有比二氧化硅小的电介质常数的低电介质常数材料(低k)用于互连结构时,此问题可能混杂起来,因为这些材料与保护性电介质层材料通常化学特性相异。
保护性电介质材料还可能增加互连结构的有效电介质常数,尤其是当该结构包含有低k电介质材料的时候。如此增加电介质常数可能显著降低集成电路的速度,该速度有赖于互连信号的传播速度。这可能导致集成电路性能下降。
附图说明
通过参考用来举例说明本发明实施例的以下描述和附图,可以最好地理解本发明。附图中:
图1示出了根据本发明一个实施例的集成电路衬底的截面图,该衬底包含有半导体衬底、在该衬底上形成的电介质层以及在该电介质层内形成的用于容纳互连线的沟槽。
图2示出了根据本发明一个实施例,在图1的电介质层上和沟槽内形成衬垫层和晶种(seed)材料后的集成电路衬底的截面图。
图3示出了根据本发明一个实施例,在图2的晶种层上和沟槽内形成导电层(典型地为金属层)后的集成电路衬底的截面图。
图4示出了根据本发明一个实施例,在从图3的衬底上除去沟槽外面的导电层、衬垫和晶种材料部分后的集成电路衬底的截面图。
图5示出了根据本发明一个实施例,在图4的互连线上形成导电无电镀沉积层后的集成电路衬底的截面图。
图6示出了根据本发明一个实施例,在图5已有电介质层和导电无电镀层上形成第二电介质层后的集成电路衬底的截面图。
图7示出了根据本发明一个实施例,在图6的第二电介质层中形成开口以容纳通孔后的集成电路衬底的截面图。
图8示出了根据本发明一个实施例,在图7的通孔开口顶部形成容纳第二互连线的开口后的集成电路衬底的截面图。
图9示出了根据本发明一个实施例,在加入导电互连材料以填充图8的开口后的集成电路衬底的截面图。
图10示出了根据本发明一个实施例,在图9的导电互连材料(第二互连线)顶部形成导电无电镀沉积层后的集成电路衬底的截面图。
图11示出了根据本发明一个实施例,在诸如图6中所示的电介质层中形成容纳无接底通孔的开口后的集成电路衬底的截面图。
图12示出了根据本发明一个实施例的集成电路衬底的截面图,该衬底包含具有无电镀沉积导电层作为无接底通孔的刻蚀停止层的多层互连结构。
图13示出了根据本发明一个实施例,通过在开口的底部无电镀沉积导电材料以形成无接底通孔后的集成电路衬底的截面图。
图14示出了根据本发明一个实施例的集成电路衬底的截面图,该衬底包含具有导电无电镀沉积通孔插塞的多层互连结构。
图15示出了根据本发明一个实施例,在开口的暴露表面上形成衬垫层后的集成电路衬底的截面图。
图16示出了根据本发明一个实施例的集成电路衬底的截面图,该衬底包含具有无电镀沉积衬垫层作为互连材料与电介质之间的屏障的多层互连结构。
图17示出了根据本发明一个实施例,在从诸如图4所示的互连线的顶部暴露表面上除去材料而形成凹入的互连线后的集成电路衬底的截面图。
图18示出了根据本发明一个实施例,在图17的凹入互连线上面形成嵌入式导电无电镀沉积层后的集成电路衬底的截面图。
图19示出了根据本发明实施例,包含具有互连结构的微处理器的计算机***。
具体实施方式
此处描述了包含导电无电镀沉积刻蚀停止层的互连结构,而且在一些实施例中该互连结构还包含衬垫层或通孔插塞,还描述了制造此类互连结构的方法。在以下描述中,阐述了大量具体细节。然而,应当理解到,没有这些具体细节也可以实施本发明的实施例。例如,可以用公知的等同材料来替代此处描述的那些材料,类似地,可以用公知的等同技术来替代所公开的特定工艺技术。在其他情况下,没有详细示出公知电路、结构和技术,以避免混淆对此描述的理解。
I.包含用于通孔的导电无电镀沉积刻蚀停止接底(landing)的互连结构
图1-10示出了根据本发明的一个实施例,代表制造互连结构的方法的不同阶段的衬底截面图,所述互连结构包含形成于互连线上的导电层。导电层既用作形成于互连线上面的通孔的刻蚀停止接底,又用作互连线与通孔之间电流流动的分路。
图1示出了集成电路衬底的部分截面图,所述集成电路衬底包含具有形成于其内的电路部件的半导体衬底102,在衬底上形成的第一电介质层104,以及在该电介质层内形成的沟槽开口106。可以使用半导体工艺领域内公知的沉积技术在衬底上形成电介质层。例如,可以通过化学气相沉积(CVD)来沉积诸如氟化的硅氧化物(例如SiOF)或掺杂碳的硅氧化物(例如,掺杂碳的二氧化硅SiO2)之类的低k电介质材料。
可以通过使用公知的掩膜、光刻和刻蚀技术在电介质层内形成沟槽106。例如,可以在电介质层上形成辐射敏感层(例如,正或负的光阻材料),并将其暴露于电磁辐射,以创建具有对应于该沟槽的曝光图案的层。然后,可以把该沟槽上覆盖的辐射敏感层的一部分除去,通过刻蚀把对应的电介质层部分除去,然后可以把辐射敏感层的其余部分除去。
图2示出了在图1的电介质层104上形成衬垫层108和晶种(Seed)材料110后的集成电路衬底的部分截面图。衬垫层可以用于阻止随后沉积在沟槽中的材料与层104的电介质材料之间发生不想要的相互作用。可以通过在电介质层的表面上,包括沟槽106的内表面上,沉积适当的材料薄层来形成该衬垫。该衬垫通常具有10-50埃(1埃等于1/10,000,000,000米,或者纳米的十分之一)的厚度。衬垫的适当的材料包括阻碍层难熔金属与合金,例如钼、镍、钴、钴-镍(CoNi)、钛-钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化硅钽(TaSiN)、氮化钛(TiN)、氮化硅钛(TiSiN)、钨(W)、氮化钨(WN)、氮化硅钨(WsiN)以及这些材料的组合物(例如Ta/TaN的多层叠合)。可以使用适当的公知沉积技术CVD、原子层沉积(ALD)或物理气相沉积(PVD)来沉积这些不同的材料。
通过诸如PVD或CVD的沉积工艺可以在衬垫上面形成少量晶种材料110,以改善随后对导电互连材料的沉积。如图所示,可以将少于单层的晶种材料用于随后的无电镀沉积。当然,也可以使用单层或更多的材料。通常,如果将晶种材料用于电镀沉积,则将使用至少单层材料,并且厚度通常在30-3000埃之间。根据本发明的一些实施例,晶种材料包含有铜(Cu)或铜合金(例如铜锡(CuSn)、铜铟(CuIn)、铜镁(CuMg)、铜铝(CuAl)),以帮助随后在其上形成包含铜的材料。可以通过PVD或诸如CVD或ALD的其他公知技术来沉积这些不同的材料。
图3示出了在图2的晶种层110上形成导电层112后的集成电路衬底的部分截面图。导电层通常包含有金属或合金。此后,术语金属将用于包括纯金属、多种金属的混合物或者合金、以及金属与一种或多种非金属(例如类金属或非金属)的混合物或者合金。根据本发明的一个实施例,该层包含导电铜材料。代表性的铜材料包括但不限于纯铜、或者诸如铜锡(CuSn)、铜铟(CuIn)、铜锑(CuSb)、铜铋(CuBi)、铜铼(CuRe)之类的合金。可以通过无电镀、电镀或其他工艺来沉积这些材料。无电镀沉积工艺与电镀工艺的区别在于,前者没有来自电压电源的从外部提供的电流。虽然电镀工艺比较常用,但对于又深、又窄、具有很高纵横比的沟槽来说,可能无电镀沉积是更适合的,因为无电镀沉积不需要连续而厚的晶种层。这两种沉积都是半导体工艺领域公知的技术。
图4示出了在从图3的衬底上除去沟槽外面的导电层112、衬垫108和晶种材料(未示出)部分后的集成电路衬底的部分截面图。典型地,通过利用化学机械抛光(CMP)或者机械抛光将上表面平坦化而除去这些部分,虽然这并不是必须的。从本公开获益的本领域技术人员将意识到,根据平坦化的程度以及通过平坦化操作形成的层的厚度,有可能省略此特殊的平坦化操作。除去这些部分创建了图案化的互连线112,其包含沟槽内的导电材料。互连线代表适合提供信号介质以承载电信号的任何图案化导电材料。在此领域,互连线有时被称为迹线(trace)、电线(wire)、线(line)、互连或者简单地称为金属。
图5示出了在图4的互连线112上面形成包含无电镀沉积金属的导电层114后的集成电路衬底的部分截面图。然而,在形成该导电层之前,可能需要清洁平坦化的表面以除去杂质,形成导电层将在下面进一步讨论。本发明者的实验表明,虽然清洁不是必须的,但它还是有助于形成高质量、均匀的导电层。
有多种清洁剂适用于清洁图4的衬底。一个被发现对除去CMP期间可能在表面形成的有机杂质很有用的具体清洁剂包括热的去离子水溶液,其中包含有效量的表面活化剂以助于湿润表面,足以缓慢地刻蚀铜互连线的刻蚀剂用以帮助除去紧密粘结在铜上的有机质,以及还原剂用以减小铜的氧化量并为随后的无电镀沉积而帮助将铜活化。适当的表面活化剂包括但不限于可以从Rhone-Poulenc获得的RHODAFAC#RE610,和可以从Sigma-Aldrich获得的Triton X100。还可以用诸如乙二醇或异丙醇之类的醇替代此表面活化剂。适当的刻蚀剂包括酸在水中的重量百分比小于10%的适当的稀溶液(例如,强的无机酸,如氢氟酸、硝酸或硫酸,或者弱的有机酸或羧酸,如柠檬酸或丙二酸)。还可以用氨来刻蚀铜材料。适当的还原剂包括乙醛酸,以及别的还原剂。
清洁剂可以包含其他药剂,例如类似TMAH(氢氧化四甲基铵)或氢氧化钾之类的碱,以及诸如过氧化氢之类的氧化剂。使用时,碱在水溶液中的浓度通常小于约10wt%。当然,这些清洁剂可以被其他清洁剂取代,或者完全避免清洁,只要互连线的表面足够清洁以允许无电镀沉积钴合金层。可以使用声波搅动或洗涤以去除微粒并提高清洁性。
现在回到图5,我们记得在图4的互连线112的暴露(通常已清洁)表面上已经形成导电无电镀沉积层。如图所示,通常在衬垫层108上面形成所述层,虽然这依赖于具体材料。该层可以有一个厚度范围,包括一个实施例中约在10-100纳米之间的厚度。层114可以钝化并保护互连线112,且可以在制造期间用作刻蚀停止层,以及在设备运行期间用作导电分路层。
可以利用通过化学反应进行的金属的化学沉积来形成层114。根据本发明的一个实施例,可以通过无电镀沉积来形成该层,其中衬底置于溶液中,所述溶液中包含含金属的化合物(例如金属络合物)和还原剂,并且通过含金属的化合物与还原剂之间在该衬底的电化学活性表面上的自身催化氧化还原反应,将金属沉积在所述表面上。此反应通过向金属离子提供电子而将它们还原,直到它们以非离子金属状态沉积在表面上。
层114可以包含诸如钴、镍之类的金属或者这些金属的合金。可能比起纯钴或纯镍来说,更想要其合金。首先,合金可能基本上是非结晶的,对扩散和电迁移来说是比纯金属的单晶体层更紧密的屏障。例如,实验表明,纯钴金属层可能有很大的结晶区,其允许铜或其他材料沿着结晶颗粒边界容易地扩散,而对于磷化钨钴而言,由于钨填充了结晶边界以减小通过这些区域进行的扩散,因此磷化钨钴的合金层可以提供更好的屏障。通常,该合金包含钴或镍,以及一种到典型地约四种其他材料,例如金属(例如过渡元素、钴、镍和钨)、类金属(例如硼)或者非金属(例如磷)。当然,如果需要,也可以包括超过四种材料。
根据本发明的一个实施例,该层包含钴硼磷(CoBP)合金,其硼的浓度约在1-10原子百分比(at%)之间,磷的浓度约在1-20at%之间,而浓度的余下部分(即,约在70-98at%之间)由钴构成。可以通过以下方法形成这样的层:准备适当的无电镀沉积溶液,将衬底浸入该溶液,允许反应进行直到已经形成具有希望厚度的层,然后从溶液中取出该衬底。
适合于CoBP金属层的无电镀沉积的溶液可以通过将以下成分复合到溶液中而准备好:钴盐(例如硫酸钴、氯化钴);络合剂(例如,EDTA、羧酸、柠檬酸、丙二酸、丁二酸、乙二氨、丙酸、醋酸),用以络合钴并帮助其保持在溶液中;包含硼的第一还原剂(例如硼烷二甲胺(DMAB)或者氢硼化物);以及包含磷的第二还原剂(例如次磷酸盐)。合金成分来自钴的络合物以及还原剂,其中当盐溶解且钴离子被络合剂所络合时,形成所述钴的络合物。典型地,溶液的pH值将影响沉积工艺,希望添加诸如TMAH、氢氧化钾、氢氧化铵或它们的某种组合物之类的碱以维持pH值在大约7和大约11之间。还可能需要包括缓冲剂,例如氯化铵(NH4Cl)或硫酸铵(NH4)2SO4,以进一步稳定溶液pH值。例如,在一个特例中,溶液包含约16-24g/L的CoCl2-6H2O、约10-16g/L的DMAB、约1.8-2.2g/L的H2PO2、约30-46g/L的柠檬酸、约26-40g/L的NH4CL、约266-400cm3/L的25%的TMAH溶液,以给出约在8.9-9.3之间的pH值。
应当了解到,其他无电镀沉积溶液也是可以考虑的。例如,可以通过添加诸如氯化镍之类的镍盐来取代或补充上述镍盐,来创建镍合金。作为另一个例子,可以通过向溶液中添加(NH4)2WO4来引入钨。
在准备好溶液并将衬底浸入后,常用的是加热溶液、衬底或者两者以提高沉积速率。最常用地,在约25℃(室温)和约100℃之间的温度进行反应以避免溶液沸腾。通常,希望温度在约35℃和约85℃之间。示例性的沉积速率通常在约10-200纳米/分钟,所述沉积速率依赖于具体的温度和化学反应。衬底可以保持浸在溶液中直到沉积工艺获得希望的层厚。
半导体工艺领域公知的是,无电镀沉积要有效发生需要活性表面。活性表面应当能够接纳无电镀沉积金属的自身催化生长。对于当前的钴硼磷合金来说铜是活性的。然而,在本发明的另一个实施例中,其中非活性金属对于互连线而言是较为理想的,这就要考虑在无电镀沉积之前就将诸如铜、钴、镍、钯、铂或金之类的活性金属沉积到非活性金属上。
可选地,可以在形成图5的层114后清洁衬底,以除去与无电镀溶液有关的杂质。适当的清洁剂可以包含水溶液,其中含有表面活化剂或者醇以帮助湿润表面,以及酸或氧化剂以温和刻蚀合金材料,从而提高清洁性。
上述沉积工艺通常能够沉积具有小于约70微欧每厘米的电阻和小于约5纳米的表面粗糙度(Ra)(对于厚度高达约200纳米的层而言)的层。这些层属性对于许多应用来说已经足够。然而,通过退火工艺可以进一步减小表面粗糙度和电阻,退火工艺改变了层的结构与材料特性。适当的退火工艺可以包括在惰性气氛(例如惰性气体、氮气)或者还原气氛(例如氢)中,将所述的层加热至约450℃。这可以包括在炉子中进行几分钟到一小时的渐变加热,或者延续几分钟的快速加温退火。这种处理形式可能对于除去在无电镀沉积工艺期间引入的诸如氢气之类的气体来说是有用的。这可以减小所述层的阻抗。加热还可以软化该层并使得粗糙度普遍减小。
在退火期间,可以向气氛中添加痕量的氧气以氧化该层的上表面。此种氧化可以使得该层的接触部分能够与随后沉积的电介质层更相容,从而使得该层和电介质层具有良好的接触与粘合。这可以减小像气泡之类的机械故障,并可以提高生产成品率。
图6示出了图5的第一电介质层104和导电层114上形成第二电介质层116后的集成电路衬底的部分截面图。可以通过使用半导体工艺领域公知的沉积技术来形成该电介质层。例如,该电介质可以包含通过已知的CVD方法沉积的氟化的硅氧化物。
如图所示,可以直接在电介质和无电镀层上形成电介质层116,而无需布置在层104和116之间的、包含诸如SiN、SiC或SiO2之类的材料的电介质硬掩膜或者刻蚀停止层。这些电介质层典型地形成在层114上面以保护该层。因为导电层114提供了对下面的互连线的保护,因此不需要硬掩膜和刻蚀停止层。消除这样的层可以改善第一和第二电介质层之间的接触和粘附性,尤其是当这些层包含类似电介质材料的时候。由于不合格器件数量的减小,这可以提高产品成品率,而且还可以提高集成电路的可靠性和使用寿命。
此外,当第一电介质层和/或第二电介质层包含低k电介质材料时,消除电介质硬掩膜或刻蚀停止层可以避免增大电介质层104和116的有效电介质常数。作为例子,当具有SiN、SiC或SiO2硬掩膜或刻蚀停止层时,它们可能将电介质区域的有效电介质常数增大10%或者更多。避免增大有效电介质常数可以导致电介质区域的电容减小(由于该电介质常数),而不会影响通过互连的阻抗。有益地,这可以提高信号通过互连结构传播的速度,并最终提高集成电路的速度。当然,消除这些层还可以简化制造工艺并帮助降低制造成本。
虽然不在互连线112上形成硬掩膜是本发明一个实施例的一方面,但只要需要,在形成导电层114的清洁操作期间可以除去任何已存在的硬掩膜。例如,如果是SiO2硬掩膜,可以使用包含稀氢氟酸或类似试剂的溶液来溶解并除去该硬掩膜。如上所述,除去该层可以使集成电路有改善的性能和可靠性。
图7示出了在图6的电介质层116中第一互连线上面形成开口118后的集成电路衬底的部分截面图。开口向下朝着电介质层114跨越了层116的整个深度,但基本没有进入电介质层114。开口可以具有足以容纳通孔插塞的宽度,该宽度可能比互连线112的宽度窄。在本领域中术语通孔有时既可以用来描述有待于将结构完成于其中的电介质中的开口,也可以用来描述完整的结构本身。在本公开中,除非另有规定,通孔都是指包括开口内的通孔插塞在内的完整结构。
可以通过相对于导电层材料选择性地除去电介质材料来形成开口。在一个例子中,可以使用诸如用于图案化图1的沟槽106的那些方法的掩膜和光刻方法来形成开口,接着通过刻蚀从开口118除去电介质材料而不从导电层114除去(或者大量除去)材料。导电层114可以是形成通孔开口的刻蚀停止层。一种适合于除去电介质材料而不会大量除去导电层的示例性刻蚀,是利用活性等离子体或者氧/氮或氟的电离气体的干刻蚀,所述电介质材料如氟化的硅氧化物或者掺碳的硅氧化物。
图8示出了从图7的开口118顶部附近除去电介质材料、以形成具有足以容纳互连线的宽度的开口区域118A后的集成电路衬底的部分截面图。可以通过使用掩膜、光刻与选择性刻蚀操作,例如用于形成图7的开口118的那些操作,来除去电介质材料。还设想了本发明的一个变化实施例,其中,在通过向下朝着但不会严重进入层114的选择性刻蚀而形成开口118B之前,通过不需要相对层114有选择性的刻蚀化学而形成区域118A。
在用与导电层114相容的清洁剂对暴露表面进行任何希望的清洁后,可以分别在图8的开口118的各内表面上形成衬垫层112。典型地,可以用诸如图2的层108所用的那些材料通过CVD、PVD或ALD来形成这些层,虽然这并非必须。
图9示出了在加入导电材料124以填充图8的开口118后的集成电路衬底的部分截面图。加入导电材料可以包括,通过适当的沉积方法在电介质层116上和开口118内形成诸如112那样的导电材料层,然后通过用CMP的平坦化工艺(例如,金属镶嵌工艺(damascene process))除去已形成的层的位于开口118以外的部分。以下将会讨论几种所考虑的其他方法。
图10示出了在图9的导电互连材料124顶部上形成导电无电镀沉积层126后的集成电路衬底的部分截面图。可以通过预清洁、无电镀沉积、后清洁以及退火来形成该层,如先前对图5的层114所公开的那样,虽然这并非必须。
因此,图1-10示出了形成互连结构的方法,所述互连结构包含有在互连线上面形成的导电层,所述导电层用作在该互连线上面制造通孔的刻蚀停止接底,所述导电层在器件使用期间用作导体124与互连112之间电流通过的分路。应当了解到,可以在图10的互连结构上面可以形成额外的层面。还应当了解到,图4的互连线112可以连接到衬底102中的电路部件内。
II.包含用于无接底(unlanded)通孔的导电无电镀沉积刻蚀停止层的互连 结构
图11-12示出了根据本发明一个实施例,代表制造互连结构的方法的不同阶段的衬底截面图,所述互连结构包含导电无电镀沉积刻蚀层和形成于导电层上面和下面的无接底通孔。
图11示出了在类似图6所示的衬底的电介质层116、电介质层104、层108中以及可能在铜112的一部分中形成开口128后的集成电路衬底的部分截面图。可以通过公知的掩膜和光刻操作来图案化该开口,开口的图案的一部分覆于层114上,图案的另一部分覆于层114左手边的电介质上,接着进行刻蚀,其选择性地刻蚀电介质材料而不会严重刻蚀层114。即,层114可以用作刻蚀停止层。刻蚀可以在层114上面形成第一开口部分,并在电介质层104中侧向沿着互连线112在层114之下形成第二过度刻蚀开口部分130。如果需要,可以使用更长或更剧烈的刻蚀来除去衬垫层108和互连线112的一部分。
图12示出了根据本发明一个实施例,包含多层互连结构的集成电路衬底的部分截面图。可以通过以下步骤形成该互连结构:除去在开口128顶部的电介质材料以允许开口容纳互连线,在修改后的开口中形成衬垫与晶种层132,在衬垫与晶种层上面形成代表互连线与通孔的导电材料134,然后在互连线134上形成导电层136。可以按照前面所述方法形成每个这些结构,或者也可以用半导体工艺领域公知的其他技术。如果使用PVD工艺来沉积衬垫与晶种层132,则可以用如上所述的无电镀沉积工艺来使得PVD衬垫/晶种在高纵横比结构中连续。
III.用于包含有导电无电镀沉积通孔插塞的无接底通孔的、包含有导电无 电镀沉积刻蚀停止层的互连结构
图13-14示出了根据本发明一个实施例,代表制造包含有导电无电镀沉积通孔插塞138的互连结构的方法的不同阶段的衬垫截面图。
图13示出了通过在开口140的底部上无电镀沉积钴或镍材料、以形成通孔138来容纳无接底通孔和互连线后的集成电路衬底的部分截面图。选择性地将材料沉积在层114、衬垫108的暴露活性表面上以及互连线112的任何暴露部分上。通孔可以从这些活性表面生长起来以填充该开口。当已经获得所希望的通孔插塞尺寸后可以停止沉积。对于窄而且有高纵横比的开口,例如那些具有宽度在约0.05-0.075微米(1微米等于1/1,000,000米)之间的开口,使用这种无电镀沉积通孔插塞可能是所希望的,因为无电镀沉积工艺可以在这种空间中均匀地沉积材料。
图14示出了根据本发明一个实施例的集成电路衬底的部分截面图,该衬底包含具有导电无电镀沉积通孔插塞的多层互连结构,所述插塞包含有钴或镍材料。可以通过以下步骤创建该互连结构:在图13的余下开口140的暴露部分上形成衬垫层142,在衬垫层上形成互连线144,以及在互连线上形成导电无电镀沉积层146。可以用前述方法形成每个这些结构,或者也可以通过半导体工艺领域公知的其他技术。
图14所示的结构的一个实施例的一方面在于插塞138的组合物异于衬垫142的组合物。例如,在合金包含硼和磷的情况下,硼和磷可以增强材料的扩散屏障,这对于衬垫层来说是有用的,虽然同时也可以略微提高电阻,但这对于通孔而言可能不是所希望的。因此,插塞具有的硼和磷的总浓度相对衬垫层来说可能更小。在一个特例中,插塞138可以包含<10at%的磷和<5at%的硼,而衬垫层142可能有>10at%的磷和>5at%的硼。
IV.用于包含有导电无电镀沉积衬垫的无接底通孔的、包含有导电无电镀 沉积刻蚀停止层的互连结构
图15-16示出了根据本发明一个实施例,代表用于在导电互连材料152与电介质材料104、116之间形成导电无电镀沉积衬垫层150的方法的不同阶段的衬底截面图。
图15示出了在开口148的暴露表面上形成衬垫层150以容纳无接底通孔与互连线后的集成电路衬底的部分截面图。在形成衬垫层之前,电介质层104与116的暴露表面可以为无电镀沉积而活化。这可以包括使用PVD来沉积诸如铜、钴或镍之类的活性金属的薄层。之后可以接着在活化表面上无电镀沉积钴或镍合金。在本发明的一个具体实施例中,将大约单层的钴溅射或热蒸发到开口的整个内表面上去,然后将钴硼磷合金无电镀沉积到钴上。与由PVD或类似沉积方法形成的现有屏障层相比,无电镀沉积衬垫层对暴露表面具有更适形和更均匀的覆盖。在高纵横比的开口中这点尤为确实,而且可以使得无电镀沉积的使用对于此类结构来说很理想。本发明者已经发现,具有小于约10纳米厚度的钴硼磷合金的薄层,可以向由于例如电流流动引起的铜的电迁移提供有效的屏障。然而,薄层并不是必须的。
图16示出了在衬垫层150上以代表通孔和互连线的导电互连材料152填充图15的开口148后,以及在导电互连材料152的顶表面上面形成导电无电镀沉积金属层154后的集成电路衬底的部分截面图。根据本发明的一个实施例,可以使用无电镀或电镀工艺在衬垫层上沉积铜材料。如果需要,在沉积导电互连材料之前,可以用包含适当表面活化剂的水溶液,将衬垫层的表面清洁或者预湿润。可以如前所述地形成导电层154,并且应当注意到除了在导电互连材料152上外,还可以在衬垫层150上形成此导电层。
V.包含用于通孔制造的嵌入式导电无电镀沉积刻蚀停止层的互连结构
图17-18示出了根据本发明一个实施例,代表用于制造互连结构的方法的不同阶段的衬底截面图,所述互连结构包含在互连线上面形成的嵌入式导电无电镀沉积层。
图17示出了包含通过从类似图4的线112的互连线的顶部暴露表面上除去材料而形成的凹入互连线156的集成电路衬底的部分截面图。在本发明的一个实施例中,所述材料可以是通过稀硫酸溶液进行化学刻蚀而被除去的铜材料,所述稀硫酸溶液优先刻蚀铜材料,而不是诸如氟化的硅氧化物或掺碳的硅氧化物的电介质材料。这可以允许将互连线相对于电介质材料凹入。还可以设想的是,也可以通过在清洁剂中包括足量的铜刻蚀剂(多于不希望互连线凹入的情况),在后平坦化清洁操作期间进行刻蚀。适当的刻蚀剂包括酸,例如硫酸,以及氢氧化铵等。
图18示出了在图17的互连线156上面形成嵌入式导电无电镀沉积层后的集成电路衬底的部分截面图。可以通过选择性无电镀沉积直到获得平坦表面、或者可以在沉积后进行CMP平坦化来创建平坦表面。
VI.在计算机***中的使用
诸如此处所描述的那些互连结构可以在芯片、集成电路整体器件、半导体器件以及微电子器件中以它们在本领域中通常所理解的方式被使用。这些集成电路可以包含电耦合到所述互连结构以从互连结构接收信号的电路元件。一个示例性的集成电路是微处理器。
包含此处所公开的互连结构的集成电路可以结合到包含计算机***(例如,便携机、笔记本电脑、台式机、大型机等等)的各种形式的电***中。图19示出了示例性的根据本发明实施例的包括微处理器172的计算机***170,所述微处理器172包含具有形成于其中的微处理器逻辑元件的半导体衬底174和互连结构173以向所述部件提供电信号。所述逻辑元件基于通过互连结构接收到的信号而执行指令。该计算机***可以包含其他互相电连接的常规部件,包括但不限于传输数据的总线176、主存储器178、只读存储器180、存储数据的大容量存储器182、显示数据的显示设备184、输入数据的键盘186、输入数据的鼠标控制设备188以及连接到其他电***的通信设备190。在一个例子中,微处理器通过总线从存储器接收数据,并通过互连结构向半导体衬底中的逻辑元件传输数据表达。
因此,已经公开了新型互连结构和用于制造所述互连结构的方法。虽然已经就几个实施例对本发明进行了描述,但本领域技术人员将承认,本发明不限于所描述的实施例,而可以有在所附权利要求书的精神和范围内的修改与变化的情况下实施。因此本描述应当被视为示例性的而非限制性的。
Claims (9)
1.一种互连结构,包括:
第一互连线;
在所述第一互连线上面的第一无电镀材料;
在所述第一无电镀材料上面包括无电镀插塞材料的通孔;
在所述通孔上面的第二互连线;和
布置在所述通孔和所述第二互连线之间的无电镀衬垫材料,其中所述无电镀插塞材料比所述无电镀衬垫材料具有更低的硼和磷的总浓度。
2.如权利要求1所述的互连结构,其中所述无电镀插塞材料包括钴硼磷合金。
3.如权利要求1所述的互连结构,其中所述无电镀插塞材料具有小于10原子百分比的磷和小于5原子百分比的硼,且其中所述衬垫材料具有大于10原子百分比的磷和大于5原子百分比的硼。
4.如权利要求2所述的互连结构,其中所述衬垫材料包括大于10原子百分比的磷和大于5原子百分比的硼。
5.如权利要求1所述的互连结构,其中所述第一互连线在电介质材料中凹入,且其中所述第一无电镀材料包括嵌入在所述凹入的第一互连线中的材料。
6.如权利要求1所述的互连结构,其中所述通孔插塞包括无接底通孔插塞。
7.一种方法,包括:
在形成在电介质层中的开口中无电镀地沉积通孔插塞,其中所述开口至少部分地在第一互连线上面,其中所述无电镀地沉积所述通孔插塞的步骤包括无电镀地沉积包含硼和磷的通孔插塞;
在所述无电镀沉积通孔插塞上面无电镀地沉积衬垫层,其中所述无电镀地沉积所述衬垫层的步骤包括无电镀地沉积包含比所述通孔插塞更高的硼和磷的总浓度的衬垫层;和
在所述衬垫层上面形成第二互连线。
8.如权利要求7所述的方法,
其中所述在所述通孔插塞上面无电镀地沉积所述衬垫层的步骤包括在所述通孔插塞上无电镀地沉积衬垫层;且
其中所述在所述衬垫层上面形成所述第二互连线的步骤包括在所述衬垫层上形成所述第二互连线。
9.如权利要求7所述的方法,
其中所述无电镀地沉积所述通孔插塞的步骤包括无电镀地沉积包括小于10原子百分比的磷和小于5原子百分比的硼的组合物;且
其中所述无电镀地沉积所述衬垫层的步骤包括无电镀地沉积包括大于10原子百分比的磷和大于5原子百分比的硼的组合物。
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TW200403768A (en) | 2004-03-01 |
US7008872B2 (en) | 2006-03-07 |
WO2003094209A3 (en) | 2004-08-05 |
US6958547B2 (en) | 2005-10-25 |
TWI299195B (en) | 2008-07-21 |
EP1466359A2 (en) | 2004-10-13 |
US20030207561A1 (en) | 2003-11-06 |
US20030207560A1 (en) | 2003-11-06 |
AU2003234236A8 (en) | 2003-11-17 |
CN1623228A (zh) | 2005-06-01 |
WO2003094209A2 (en) | 2003-11-13 |
AU2003234236A1 (en) | 2003-11-17 |
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