CN100397612C - Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs - Google Patents

Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs Download PDF

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CN100397612C
CN100397612C CNB038005859A CN03800585A CN100397612C CN 100397612 C CN100397612 C CN 100397612C CN B038005859 A CNB038005859 A CN B038005859A CN 03800585 A CN03800585 A CN 03800585A CN 100397612 C CN100397612 C CN 100397612C
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layer
electroless plating
interconnection line
interconnection
boron
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CN1623228A (en
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瓦莱丽·迪宾
展常·程
马卡连姆·候赛因
披·源
吕特·布雷恩
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Intel Corp
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Intel Corp
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

The invention discloses multiple level interconnect structures and methods for fabricating the interconnect structures. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Description

Conduction electroless deposition etching stop layer, laying and the use of via plug in interconnection structure
Technical field
Embodiments of the invention relate to interconnection structure and manufacture method.Particularly, these embodiment relate to novel interconnection structure, described interconnection structure comprises conduction electroless deposition etching stop layer, and comprise laying and via plug under some situation, also relate to the novel method that is used to make described interconnection structure, and relate to the integrated circuit that comprises described interconnection structure.
Background technology
Many integrated circuits include the multilayer electric interconnection structure provides the signal of telecommunication with the logic element to the transistor on being positioned at Semiconductor substrate.Interconnection structure includes interconnection line usually, and separate in the layout of described interconnection line intimate coplane in dielectric substance, described dielectric substance makes these interconnection line mutually insulateds.By passing the through hole that insulating material forms, can realize that the selection between the interconnection line of different aspects connects.
Interconnection line is made with high-conductive metal or alloy usually.Partly because comparing copper with other metals has low resistance, it has become widely used material.Yet it is exactly that it is easy to oxidation that copper has a shortcoming.Therefore,, perhaps be subjected to the operation of various etchings or plasma cleans if the copper surface is in exposed state over a long time, then should the surface may be oxidized.Different with the other materials such as aluminium, the oxidation of copper can't form the thin protection coating that can stop further oxidation, so a big chunk of copper may be oxidized.This does not want usually, because it may significantly change the electricity and the mechanical attributes of interconnection structure.Another shortcoming of copper is that it is easily by many dielectric etch chemical agents commonly used institute etching.Therefore, if the copper surface is in exposed state, and be not protected, then its may be oxidized or be partly removed in subsequent technique operating period.
In order to reduce oxidation and copper etching, on copper interconnecting line, form the protectiveness dielectric etch usually and stop layer or hard mask layer.For this purpose and material commonly used comprises silicon nitride (SiN), carborundum (SiC) and silicon dioxide (SiO 2).Though it may be that effectively they have increased mechanical isolation usually and have caused the integrated circuit fault that these dielectric layers avoid in the reaction at protection copper, they also may increase effective electric medium constant of interconnection structure and cause decreased performance.
The protectiveness dielectric layer provides extra material interface or tie point, and wherein balling-up, fracture or foaming etc. often take place the mechanical isolation from protective layer.The mechanical breakdown of these kinds may reduce the rate of finished products of product, and the effective life that may reduce the integrated circuit of manufacturing.When being used for interconnection structure, this problem may mix the low-dielectric constant material with electric medium constant littler than silicon dioxide (low k), because these materials and the common chemical characteristic of protectiveness dielectric layer material are different.
The protectiveness dielectric substance also may increase effective electric medium constant of interconnection structure, especially when this structure includes the low K dielectrics material.So increase the speed that electric medium constant may significantly reduce integrated circuit, this speed depends on the propagation velocity of interconnect signal.This may cause performance of integrated circuits to descend.
Description of drawings
By with reference to the following description and drawings that are used for illustrating the embodiment of the invention, can understand the present invention best.In the accompanying drawing:
Fig. 1 shows the sectional view of integrated circuit substrate according to an embodiment of the invention, and this substrate includes Semiconductor substrate, at dielectric layer that forms on this substrate and the groove that is used to hold interconnection line that forms in this dielectric layer.
Fig. 2 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate on the dielectric layer of Fig. 1 and in the groove behind formation laying and crystal seed (seed) material.
Fig. 3 shows according to one embodiment of the invention, forms the sectional view of the integrated circuit substrate behind the conductive layer (typically being metal level) on the crystal seed layer of Fig. 2 and in the groove.
Fig. 4 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after the conductive layer of removing the groove outside from the substrate of Fig. 3, liner and seed crystal material part.
Fig. 5 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after forming conduction electroless deposition layer on the interconnection line of Fig. 4.
Fig. 6 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after forming second dielectric layer on existing dielectric layer of Fig. 5 and the conduction electroless plating.
Fig. 7 shows according to one embodiment of the invention, forms the sectional view of the integrated circuit substrate of opening after with receiving opening in second dielectric layer of Fig. 6.
Fig. 8 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after the opening that holds second interconnection line is formed on the via openings top of Fig. 7.
Fig. 9 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after the adding conductive interconnect material is with the opening of blank map 8.
Figure 10 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after conduction electroless deposition layer is formed on conductive interconnect material (second interconnection line) top of Fig. 9.
Figure 11 shows according to one embodiment of the invention, forms to hold the sectional view that does not have the integrated circuit substrate behind the opening that connects end through hole in the dielectric layer shown in Fig. 6.
Figure 12 shows the sectional view of integrated circuit substrate according to an embodiment of the invention, and this substrate comprises and has the electroless deposition conductive layer connects the etching stop layer of end through hole as nothing multilayer interconnect structure.
Figure 13 shows according to one embodiment of the invention, by there is not the sectional view of the integrated circuit substrate after connecing end through hole with formation at the bottom of opening electroless deposition electric conducting material.
Figure 14 shows the sectional view of integrated circuit substrate according to an embodiment of the invention, and this substrate comprises the multilayer interconnect structure with conduction electroless deposition via plug.
Figure 15 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate after forming laying on the exposed surface of opening.
Figure 16 shows the sectional view of integrated circuit substrate according to an embodiment of the invention, and this substrate comprises and has the multilayer interconnect structure of electroless deposition laying as the barrier between interconnection material and the dielectric.
Figure 17 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate removing material from the top, exposed surface of all interconnection lines as shown in Figure 4 after forming recessed interconnection line.
Figure 18 shows according to one embodiment of the invention, the sectional view of the integrated circuit substrate on the recessed interconnection line of Figure 17 behind the embedded conduction electroless deposition layer of formation.
Figure 19 shows according to the embodiment of the invention, comprises the computer system of the microprocessor with interconnection structure.
Embodiment
Described the interconnection structure that comprises conduction electroless deposition etching stop layer herein, and this interconnection structure also comprises laying or via plug in certain embodiments, has also described the method for making this type of interconnection structure.In the following description, a large amount of details have been set forth.Yet, be to be understood that do not have these details also can implement embodiments of the invention.For example, can substitute those materials described herein, similarly, can substitute disclosed special process technology with known equivalent technologies with known equivalent material.In other cases, be not shown specifically known circuits, structure and technology, to avoid confusion to the understanding of this description.
I. comprise the interconnection structure that the conduction electroless deposition etching stopping that is used for through hole meets the end (landing)
Fig. 1-10 shows according to one embodiment of present invention, the substrate cross-section figure of the different phase of the method for representative manufacturing interconnection structure, and described interconnection structure comprises the conductive layer that is formed on the interconnection line.Conductive layer both connect the end as the etching stopping that is formed at the through hole above the interconnection line, again the shunt of flowing as electric current between interconnection line and the through hole.
Fig. 1 shows the partial cross section figure of integrated circuit substrate, described integrated circuit substrate comprises and has the Semiconductor substrate 102 that is formed at the circuit block in it, first dielectric layer 104 that on substrate, forms, and the groove opening 106 that in this dielectric layer, forms.Can use the interior known deposition technique of field of semiconductor technology on substrate, to form dielectric layer.For example, can deposit Si oxide (for example, the silicon dioxide SiO of doping carbon by chemical vapor deposition (CVD) such as Si oxide of fluoridizing (for example SiOF) or doping carbon 2) and so on the low K dielectrics material.
Can in dielectric layer, form groove 106 by using known mask, photoetching and lithographic technique.For example, can on dielectric layer, form radiation-sensitive layer (for example, the photoresist of plus or minus), and be exposed to electromagnetic radiation, have layer corresponding to the exposing patterns of this groove with establishment.Then, can remove the part of the radiation-sensitive layer that covers on this groove, corresponding dielectric layer partly be removed, can remove the remainder of radiation-sensitive layer then by etching.
Fig. 2 shows the partial cross section figure of the integrated circuit substrate after forming laying 108 and crystal seed (Seed) material 110 on the dielectric layer 104 of Fig. 1.Laying can be used for stoping between the dielectric substance of the material that is deposited on groove subsequently and layer 104 undesired interaction takes place.Can comprise on the inner surface of groove 106 by on the surface of dielectric layer, deposit suitable material thin-layer and form this liner.This liner has the thickness of 10-50 dust (1 dust equals 1/10,000,000,000 meter, perhaps 1/10th of nanometer) usually.The suitable material of liner comprises barrier layer refractory metals and alloy, for example the composition of molybdenum, nickel, cobalt, cobalt-nickel (CoNi), titanium-tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WsiN) and these materials (for example multilayer build-up of Ta/TaN).Can use suitable known deposition technique CVD, ald (ALD) or physical vapor deposition (PVD) to deposit these different materials.
Can on liner, form small amount of seeds material 110 by depositing operation, to improve subsequently deposition to conductive interconnect material such as PVD or CVD.As shown in the figure, the seed crystal material that is less than individual layer can be used for subsequently electroless deposition.Certainly, also can use individual layer or more material.Usually,, then will use monolayer material at least, and thickness is usually between the 30-3000 dust if seed crystal material is used for electroplating deposition.According to some embodiments of the present invention, seed crystal material includes copper (Cu) or copper alloy (for example copper tin (CuSn), copper indium (CuIn), copper magnesium (CuMg), copper aluminium (CuAl)), to help to form subsequently the material that comprises copper thereon.Can deposit these different materials by PVD or such as other known technologies of CVD or ALD.
Fig. 3 shows the partial cross section figure of the integrated circuit substrate after forming conductive layer 112 on the crystal seed layer 110 of Fig. 2.Conductive layer includes metal or alloy usually.After this, the term metal will be used to comprise the mixture of simple metal, multiple metal or the mixture or the alloy of alloy and metal and one or more nonmetal (for example metalloids or nonmetal).According to one embodiment of present invention, this layer comprises conductive copper material.Representational copper product includes but not limited to fine copper or the alloy such as copper tin (CuSn), copper indium (CuIn), copper antimony (CuSb), copper bismuth (CuBi), copper rhenium (CuRe).Can deposit these materials by electroless plating, plating or other technology.The difference of electroless deposition process and electroplating technology is that the electric current that provides from the outside from voltage source is not provided for the former.Though electroplating technology is more commonly used, for not only dark but also narrow, have the very groove of high aspect ratio, possible electroless deposition is more suitable for, because electroless deposition does not need continuous and thick crystal seed layer.These two kinds of depositions all are the field of semiconductor technology technique known.
Fig. 4 shows the partial cross section figure of the integrated circuit substrate after the conductive layer 112 of removing the groove outside from the substrate of Fig. 3, liner 108 and seed crystal material (not shown) part.Typically, by utilizing chemico-mechanical polishing (CMP) or mechanical polishing these parts are removed in the upper surface planarization, though this is not necessary.The thickness of the layer that forms according to the degree of planarization and by the planarization operation from one of skill in the art will appreciate that of benefiting of the disclosure might omit this special planarization operation.Remove the interconnection line 112 that these parts have been created patterning, it comprises the electric conducting material in the groove.The interconnection line representative is fit to provide any patterning conductive material of signal media with the carrying signal of telecommunication.In this field, interconnection line is called as trace (trace), electric wire (wire), line (line), interconnection sometimes or is called metal simply.
Fig. 5 shows on the interconnection line 112 of Fig. 4 the partial cross section figure that forms the integrated circuit substrate behind the conductive layer 114 that comprises electroless deposition of metals.Yet before forming this conductive layer, the surface that may need clear flatization forms conductive layer and will be discussed further below to remove impurity.Present inventor's experiment shows that though cleaning not necessarily, it still helps to form high-quality, uniform conductive layer.
There is multiple cleaning agent to be applicable to the substrate of cleaning Fig. 4.One is found removing the deionized water solution that the organic impurities concrete cleaning agent of great use that may form on the surface during the CMP comprises heat, the surfactant that wherein comprises effective dose is to help wetted surface, the etching agent that is enough to etching copper interconnection line lentamente is in order to helping the removing organic matter of tight bond on copper, and reducing agent helps work in copperization in order to the amount of oxidation that reduces copper and for subsequently electroless deposition.Suitable surfactant includes but not limited to the RHODAFAC#RE610 that can obtain from Rhone-Poulenc and the Triton X100 that can obtain from Sigma-Aldrich.Can also use the alcohol such as ethylene glycol or isopropyl alcohol to substitute this surfactant.Suitable etching agent comprises that the percentage by weight of acid in water is less than 10% suitable weak solution (for example, strong inorganic acid, as hydrofluoric acid, nitric acid or sulfuric acid, perhaps Ruo organic acid or carboxylic acid are as citric acid or malonic acid).Can also come the etching copper material with ammonia.Suitable reducing agent comprises glyoxalic acid, and other reducing agent.
Cleaning agent can comprise other medicaments, the alkali of for example similar TMAH (tetramethyl ammonium hydroxide) or potassium hydroxide and so on, and the oxidant such as hydrogen peroxide.During use, the concentration of alkali in the aqueous solution is usually less than about 10wt%.Certainly, these cleaning agents can be replaced by other cleaning agents, perhaps avoid cleaning fully, as long as the surperficial clean enough of interconnection line is to allow electroless deposition cobalt alloy layer.Can use sound wave stirring or washing to remove particulate and to improve spatter property.
Get back to Fig. 5 now, we remember to have formed conduction electroless deposition layer on exposure (the cleaning usually) surface of the interconnection line 112 of Fig. 4.As shown in the figure, on laying 108, form described layer usually, though this depends on concrete material.This layer can have a thickness range, comprises the thickness between the 10-100 nanometer among the embodiment.Layer 114 can passivation and is protected interconnection line 112, and can be used as etching stop layer during manufacture, and is used as the conducting bridge layer during equipment operation.
Can utilize the chemical deposition of the metal that is undertaken by chemical reaction to come cambium layer 114.According to one embodiment of present invention, can form this layer by electroless deposition, wherein substrate places solution, comprise metallic compound (for example metal complex) and reducing agent in the described solution, and by between metallic compound and the reducing agent in the lip-deep autocatalysis redox reaction of the electro-chemical activity of this substrate, deposit metal on the described surface.This reaction, deposits from the teeth outwards with the nonionic metallic state up to them they reduction by providing electronics to metal ion.
Layer 114 can comprise the metal such as cobalt, nickel or the alloy of these metals.May more want its alloy compared with pure cobalt or pure nickel.At first, alloy may be noncrystalline basically, is than the single crystal layer of simple metal barrier more closely to diffusion and electromigration.For example, experiment shows, pure cobalt metal level has very big crystal region, it allows copper or other materials easily to spread along crystal grain boundaries, and for the tungsten phosphide cobalt, because tungsten has been filled the diffusion of crystalline boundary to reduce to be undertaken by these zones, so the alloy-layer of tungsten phosphide cobalt can provide better barrier.Usually, this alloy comprises cobalt or nickel, and a kind of to about four kinds of other materials typically, for example metal (for example transition elements, cobalt, nickel and tungsten), metalloid (for example boron) or nonmetal (for example phosphorus).Certainly, if desired, also can comprise surpassing four kinds of materials.
According to one embodiment of present invention, this layer comprises cobalt boron phosphorus (CoBP) alloy, and the concentration of its boron is between 1-10 atomic percent (at%), and the concentration of phosphorus is between 1-20at%, and the remaining part of concentration (that is, between 70-98at%) is made of cobalt.Can form such layer by the following method: prepare suitable electroless deposition solution, substrate is immersed this solution, allow reaction to carry out forming and have the layer of wishing thickness, from solution, take out this substrate then up to.
The solution that is suitable for the electroless deposition of CoBP metal level can be ready to by following composition is compound in the solution: cobalt salt (for example cobaltous sulfate, cobalt chloride); Complexing agent (for example, EDTA, carboxylic acid, citric acid, malonic acid, succinic acid, second diamino, propionic acid, acetic acid) is in order to complex cobalt and help it to remain in the solution; First reducing agent (for example borine dimethylamine (DMAB) or borohydrides) that comprises boron; And second reducing agent (for example hypophosphites) that comprises phosphorus.Alloying component is from the complex compound and the reducing agent of cobalt, wherein when salt dissolving and cobalt ions during by the complexing of complexing agent institute, forms the complex compound of described cobalt.Typically, the pH value of solution will influence depositing operation, wish that the alkali of interpolation such as TMAH, potassium hydroxide, ammonium hydroxide or their certain composition is to keep the pH value between about 7 and about 11.Also may need to comprise buffer, for example ammonium chloride (NH 4Cl) or ammonium sulfate (NH 4) 2SO 4, with further stabilizing solution pH value.For example, in a special case, solution comprises the CoCl of about 16-24g/L 2-6H 2The DMAB of O, about 10-16g/L, the H of about 1.8-2.2g/L 2PO 2, the citric acid of about 30-46g/L, the NH of about 26-40g/L 4CL, about 266-400cm 325% the TMAH solution of/L is to provide the pH value between 8.9-9.3.
Should recognize that other electroless deposition solution also are admissible.For example, can replace or additional above-mentioned nickel salt, create nickel alloy by the nickel salt that adds such as nickel chloride.As another example, can be by in solution, adding (NH 4) 2WO 4Introduce tungsten.
After being ready to solution and substrate immersed, commonly used is heated solution, substrate or both are to improve deposition rate.The most frequently used ground, the temperature between about 25 ℃ (room temperatures) and about 100 ℃ is reacted to avoid the solution boiling.Usually, desired temperature is between about 35 ℃ and about 85 ℃.Usually in about 10-200 nm/minute, described deposition rate depends on concrete temperature and chemical reaction to exemplary deposition rate.Substrate can keep being immersed in the bed thickness that obtains hope in the solution up to depositing operation.
Field of semiconductor technology is well known that electroless deposition will effectively need active surface.Active surface should be admitted the autocatalysis growth of electroless deposition of metals.Copper is active for current cobalt boron phosphor alloy.Yet, in another embodiment of the present invention, wherein inactive metal is comparatively desirable for interconnection line, and this will consider just will deposit on the inactive metal such as the reactive metal copper, cobalt, nickel, palladium, platinum or the gold before the electroless deposition.
Alternatively, can be in the layer 114 back clean substrate that form Fig. 5, to remove the impurity relevant with electroless plating solution.Suitable cleaning agent can comprise the aqueous solution, wherein contains surfactant or alcohol helping wetted surface, and acid or oxidant be with gentle etching alloy material, thereby improves spatter property.
Above-mentioned depositing operation can deposit usually to have less than the resistance of every centimetre of about 70 micro-ohm with less than the layer of the surface roughness (Ra) of about 5 nanometers (for thickness up to for the layer of about 200 nanometers).These layers attribute is enough for many application.Yet, can further reduce surface roughness and resistance by annealing process, annealing process has changed the structure and the material behavior of layer.Suitable annealing process can be included in inert atmosphere (for example inert gas, nitrogen) or the reducing atmosphere (for example hydrogen), and described layer is heated to about 450 ℃.This can be included in the gradual change heating of carrying out a few minutes to one hour in the stove, perhaps continues the quick thermal annealing of a few minutes.This processing form may be useful for remove the gas of introducing such as hydrogen during electroless deposition process.This can reduce the impedance of described layer.Heating can also be softened this layer and be made roughness generally reduce.
During annealing, can in atmosphere, add the upper surface of the oxygen of trace with this layer of oxidation.This kind oxidation can so that the contact portion of this layer can with subsequently the deposition dielectric layer more compatible, thereby make this layer and dielectric layer have excellent contact and bonding.This can reduce the mechanical breakdown of picture bubble and so on, and can improve the rate of manufacturing a finished product.
Fig. 6 shows the partial cross section figure that forms the integrated circuit substrate behind second dielectric layer 116 on first dielectric layer 104 of Fig. 5 and the conductive layer 114.Can form this dielectric layer by using the known deposition technique of field of semiconductor technology.For example, this dielectric can comprise the Si oxide of fluoridizing by known CVD method deposition.
As shown in the figure, can be directly on dielectric and electroless plating, form dielectric layer 116, and need not to be arranged between the layer 104 and 116, comprise such as SiN, SiC or SiO 2And so on the dielectric hard mask or the etching stop layer of material.These dielectric layers typically are formed on above the layer 114 to protect this layer.Because conductive layer 114 provides the protection to following interconnection line, therefore do not need hard mask and etching stop layer.Eliminate such layer and can improve contact and adhesiveness between first and second dielectric layers, especially when these layers comprise similar dielectric substance.Because reducing of defective number of devices, this can improve the finished product rate, but also can improve the reliability and the useful life of integrated circuit.
In addition, when first dielectric layer and/or second dielectric layer comprise the low K dielectrics material, eliminate dielectric hard mask or etching stop layer and can avoid increasing effective electric medium constant of dielectric layer 104 and 116.As an example, when having hard mask of SiN, SiC or SiO2 or etching stop layer, they may increase 10% or more with effective electric medium constant of dielectric area.Avoid increasing the electric capacity that effective electric medium constant can cause dielectric area and reduce (because this electric medium constant), and can not influence impedance by interconnection.Valuably, this can improve the speed that signal is propagated by interconnection structure, and finally improves the speed of integrated circuit.Certainly, eliminating these layers can also simplified manufacturing technique and help reduction manufacturing cost.
Though not forming hard mask on interconnection line 112 is the one side of one embodiment of the invention,, during the clean operation that forms conductive layer 114, can remove any already present hard mask as long as need.For example, if SiO 2Hard mask can use the solution that comprises diluted hydrofluoric acid or similar reagents to dissolve and removes this hard mask.As mentioned above, removing this layer can make integrated circuit that the Performance And Reliability of improvement is arranged.
Fig. 7 shows in the dielectric layer 116 of Fig. 6 the partial cross section figure that forms the integrated circuit substrate behind the opening 118 above first interconnection line.Open Side Down has crossed over the entire depth of layer 116 towards dielectric layer 114, but does not enter dielectric layer 114 substantially.Opening can have the width that is enough to the receiving opening connector, and this width may be narrower than the width of interconnection line 112.The term through hole both can be used for sometimes describing and await structure is finished opening in dielectric wherein in the art, also can be used for describing complete structure itself.In the disclosure, unless otherwise prescribed, through hole all is meant the complete structure that comprises the via plug in the opening.
Can form opening by optionally removing dielectric substance with respect to conductive.In an example, can use mask and photoetching method to form opening such as those methods of the groove 106 that is used for patterning Fig. 1, then remove dielectric substance and do not remove (perhaps removing in a large number) material from opening 118 from conductive layer 114 by etching.Conductive layer 114 can be the etching stop layer that forms via openings.A kind of exemplary etching that is suitable for removing dielectric substance and can remove conductive layer in a large number is the dry etching that utilizes the ionized gas of plasma active or oxygen/nitrogen or fluorine, and described dielectric substance is as the Si oxide fluoridized or the Si oxide of carbon dope.
Fig. 8 shows from removing dielectric substance near opening 118 tops of Fig. 7, having the partial cross section figure of the integrated circuit substrate behind the open area 118A of the width that is enough to hold interconnection line with formation.Can for example be used to form those operations of the opening 118 of Fig. 7 by using mask, photoetching and selective etch operation, remove dielectric substance.Also imagined an alternate embodiment of the present invention, wherein, by downwards towards but before the selective etch that can seriously not enter layer 114 forms opening 118B, by do not need opposite layer 114 selectively etch chemistries form regional 118A.
After using the cleaning agent compatible that exposed surface is carried out the cleaning of any hope, can be respectively on each inner surface of the opening 118 of Fig. 8, form laying 112 with conductive layer 114.Typically, can use layer 108 those used material to form these layers, though this is also nonessential by CVD, PVD or ALD such as Fig. 2.
Fig. 9 shows the partial cross section figure of the integrated circuit substrate after adding electric conducting material 124 is with the opening 118 of blank map 8.Adding electric conducting material can comprise, form such as 112 such conductive material layers on dielectric layer 116 and in the opening 118 by suitable deposition process, then by remove the part beyond the opening 118 of being positioned at of established layer with the flatening process (for example, damascene process An (damascene process)) of CMP.Below several additive methods of considering will be discussed.
Figure 10 shows the partial cross section figure of the integrated circuit substrate after forming conduction electroless deposition layer 126 on conductive interconnect material 124 tops of Fig. 9.Can form this layer by precleaning, electroless deposition, back cleaning and annealing, as before to the layer 114 of Fig. 5 disclosed, though this is also nonessential.
Therefore, Fig. 1-10 shows the method that forms interconnection structure, described interconnection structure includes the conductive layer that forms on interconnection line, described conductive layer is as connecing the end in this etching stopping of making through hole above interconnection line, and described conductive layer is used as the shunt that electric current passes through between conductor 124 and the interconnection 112 at device between the operating period.Should recognize, can on the interconnection structure of Figure 10, can form extra aspect.It is also understood that the interconnection line 112 of Fig. 4 can be connected in the circuit block in the substrate 102.
II. Comprise the interconnection that is used for not having the conduction electroless deposition etching stop layer that connects the end (unlanded) through hole Structure
Figure 11-12 shows according to one embodiment of the invention, and the substrate cross-section figure of the different phase of the method for representative manufacturing interconnection structure, described interconnection structure comprise conduction electroless deposition etch layer and connect end through hole with being formed at above the conductive layer with following nothing.
Figure 11 shows in the dielectric layer 116 of similar substrate shown in Figure 6, dielectric layer 104, layer 108 and the partial cross section figure of the integrated circuit substrate after may forming opening 128 in the part of copper 112.Can come this opening of patterning by known mask and lithography operations, the part of the pattern of opening is overlying on the layer 114, another part of pattern is overlying on the dielectric of layer 114 left-hand side, then carries out etching, and it is etching dielectric substance and serious etch layer 114 not optionally.That is, layer 114 can be used as etching stop layer.Etching can form first opening portion on layer 114, and side direction forms the second overetch opening portion 130 along interconnection line 112 under layer 114 in dielectric layer 104.If desired, can use longer or more violent etching to remove the part of laying 108 and interconnection line 112.
Figure 12 shows according to one embodiment of the invention, comprises the partial cross section figure of the integrated circuit substrate of multilayer interconnect structure.Can form this interconnection structure by following steps: the dielectric substance of removing at opening 128 tops holds interconnection line to allow opening, in amended opening, form liner and crystal seed layer 132, form the electric conducting material 134 of representing interconnection line and through hole at liner and above the crystal seed layer, on interconnection line 134, form conductive layer 136 then.Can form each these structure according to method noted earlier, perhaps also can use the known other technologies of field of semiconductor technology.If use PVD technology to come deposit liner and crystal seed layer 132, then can make the PVD liner/seed crystal continuous in high-aspect-ratio structure with aforesaid electroless deposition process.
III. The nothing that is used to include conduction electroless deposition via plug connect end through hole, include conduction and do not have The interconnection structure of electroplating deposition etching stop layer
Figure 13-14 shows according to one embodiment of the invention, represents the liner sectional view of the different phase of the method for making the interconnection structure that includes conduction electroless deposition via plug 138.
Figure 13 shows by at electroless deposition cobalt or nickel material on the bottom of opening 140, to form the partial cross section figure that through hole 138 holds does not have the integrated circuit substrate after connecing end through hole and interconnection line.Optionally material is deposited on layer 114, the exposure active surface of liner 108 and on any expose portion of interconnection line 112.Through hole can be grown to fill this opening from these active surfaces.After obtaining desirable via plug size, can stop deposition.For narrow and the opening of high aspect ratio arranged, for example those have width (1 micron equal 1/1 at about 0.05-0.075 micron, 000,000 meter) between opening, it may be desirable using this electroless deposition via plug because electroless deposition process can be in this space deposition materials equably.
Figure 14 shows the partial cross section figure of integrated circuit substrate according to an embodiment of the invention, and this substrate comprises the multilayer interconnect structure with conduction electroless deposition via plug, and described connector includes cobalt or nickel material.Can create this interconnection structure by following steps: on the expose portion of the remaining opening 140 of Figure 13, form laying 142, on laying, form interconnection line 144, and on interconnection line, form conduction electroless deposition layer 146.Can form each these structure with preceding method, perhaps also can pass through the known other technologies of field of semiconductor technology.
The one side of an embodiment of structure shown in Figure 14 is that the composition of connector 138 differs from the composition of liner 142.For example, comprise at alloy under the situation of boron and phosphorus, the diffusion barrier that boron and phosphorus can reinforcing materials, this is useful for laying, though also can improve resistance slightly simultaneously, this may not be desirable for through hole.Therefore, may be littler the relative laying of total concentration of the boron that has of connector and phosphorus.In a special case, connector 138 can comprise＜phosphorus of 10at% and＜boron of 5at%, and laying 142 has＞phosphorus of 10at% and＞boron of 5at%.
IV. The nothing that is used to include conduction electroless deposition liner connect end through hole, include the conduction electroless plating Deposition-etch stops the interconnection structure of layer
Figure 15-16 shows according to one embodiment of the invention, and representative is used for the substrate cross-section figure of the different phase of the method for formation conduction electroless deposition laying 150 between conductive interconnect material 152 and dielectric substance 104,116.
Figure 15 shows and is forming laying 150 on the exposed surface of opening 148 to hold the partial cross section figure that does not have the integrated circuit substrate after connecing end through hole and interconnection line.Before forming laying, dielectric layer 104 and 116 exposed surface can activate for electroless deposition.This can comprise the thin layer that uses PVD to deposit the reactive metal such as copper, cobalt or nickel.Then electroless deposition cobalt or nickel alloy on activating surface afterwards.In a specific embodiment of the present invention, the cobalt sputter or the thermal evaporation of about individual layer are gone on the total inner surface of opening, then with cobalt boron phosphor alloy electroless deposition to cobalt.Compare with the existing barrier layer that is formed by PVD or similar deposition process, the electroless deposition laying has suitableeer shape and more uniform covering to exposed surface.This point is particularly certain in the opening of high aspect ratio, and can be so that the use of electroless deposition is very desirable for this class formation.The present inventor has been found that the thin layer that has less than the cobalt boron phosphor alloy of about 10 nano thickness, and the electromigration of the copper that can cause to flowing owing to for example electric current provides effective barrier.Yet thin layer is not necessary.
Figure 16 shows after filling the opening 148 of Figure 15 with the conductive interconnect material 152 of representing through hole and interconnection line on the laying 150, and the partial cross section figure that forms the integrated circuit substrate behind the conduction electroless deposition of metals layer 154 on the top surface of conductive interconnect material 152.According to one embodiment of present invention, can use electroless plating or electroplating technology deposited copper material on laying.If desired, before the depositing electrically conductive interconnection material, can be with the aqueous solution that comprises suitable surfactant, with the cleaning surfaces or the pre-wetted of laying.Can form conductive layer 154 as previously mentioned, and should be noted that except on conductive interconnect material 152, can also on laying 150, form this conductive layer.
V. The interconnection structure that comprises the embedded conduction electroless deposition etching stop layer that is used for the through hole manufacturing
Figure 17-18 shows according to one embodiment of the invention, and representative is used to make the substrate cross-section figure of different phase of the method for interconnection structure, and described interconnection structure is included in the embedded conduction electroless deposition layer that interconnection line forms above.
Figure 17 shows the partial cross section figure that comprises by the integrated circuit substrate of removing the recessed interconnection line 156 that material forms from the top, exposed surface of the interconnection line of the line 112 of similar Fig. 4.In one embodiment of the invention, described material can be to carry out the copper product that chemical etching is removed by dilution heat of sulfuric acid, the preferential etching copper material of described dilution heat of sulfuric acid, rather than such as the dielectric substance of the Si oxide of Si oxide of fluoridizing or carbon dope.This can allow interconnection line recessed with respect to dielectric substance.What it is also contemplated that is also can carry out etching during back planarization clean operation by the copper etching agent (more than the situation of not wishing that interconnection line is recessed) that comprises capacity in cleaning agent.Suitable etching agent comprises acid, for example sulfuric acid, and ammonium hydroxide etc.
Figure 18 shows the partial cross section figure of the integrated circuit substrate behind the embedded conduction electroless deposition layer of formation on the interconnection line 156 of Figure 17.Can be by the selectivity electroless deposition up to obtaining flat surfaces or can after deposition, carrying out cmp planarizationization and create flat surfaces.
VI. Use in computer system
All those interconnection structures as described herein can be used in their common in the art modes of being understood in chip, integrated circuit integral device, semiconductor device and microelectronic component.These integrated circuits can comprise and are electrically coupled to described interconnection structure with the circuit element from the interconnection structure received signal.An exemplary integrated circuit is a microprocessor.
The integrated circuit that comprises interconnection structure disclosed herein can be incorporated in the various forms of electric systems that comprise computer system (for example, portable machine, notebook computer, desktop computer, large-scale computer or the like).Figure 19 shows the exemplary computer system that comprises microprocessor 172 170 according to the embodiment of the invention, and described microprocessor 172 comprises Semiconductor substrate 174 with the microprocessor logic element that is formed at wherein and interconnection structure 173 to provide the signal of telecommunication to described parts.Described logic element executes instruction based on the signal that receives by interconnection structure.This computer system can comprise other conventional components that is electrically connected mutually, includes but not limited to transmit bus 176, main storage 178, read-only memory 180, the mass storage 182 of storage data, the display device 184 of video data, the keyboard 186 of input data, the mouse control equipment 188 of input data and the communication equipment 190 that is connected to other electric systems of data.In an example, microprocessor through bus receives data from memory, and by the logic element transmission data representation of interconnection structure in Semiconductor substrate.
Therefore, novel interconnection structure and the method that is used to make described interconnection structure are disclosed.Though invention has been described with regard to several embodiment, those skilled in the art will admit, the invention is not restricted to described embodiment, implement and can have under the situation of modification in the spirit and scope of appended claims and variation.Therefore this description should be regarded as illustrative rather than restrictive.

Claims (9)

1. interconnection structure comprises:
First interconnection line;
The first electroless plating material on described first interconnection line;
The through hole that on the described first electroless plating material, comprises the electroless plating plug material;
Second interconnection line on described through hole; With
Be arranged in the electroless plating gasket material between described through hole and described second interconnection line, wherein said electroless plating plug material has the total concentration of lower boron and phosphorus than described electroless plating gasket material.
2. interconnection structure as claimed in claim 1, wherein said electroless plating plug material comprises the cobalt boron phosphor alloy.
3. interconnection structure as claimed in claim 1, wherein said electroless plating plug material has less than the phosphorus of 10 atomic percents with less than the boron of 5 atomic percents, and wherein said gasket material has greater than the phosphorus of 10 atomic percents with greater than the boron of 5 atomic percents.
4. interconnection structure as claimed in claim 2, wherein said gasket material comprise greater than the phosphorus of 10 atomic percents with greater than the boron of 5 atomic percents.
5. interconnection structure as claimed in claim 1, wherein said first interconnection line are recessed in dielectric substance, and the wherein said first electroless plating material comprises the material in first interconnection line that is embedded in the female.
6. interconnection structure as claimed in claim 1, wherein said via plug comprise that nothing connects end via plug.
7. method comprises:
Electroless plating ground deposition via plug in the opening in being formed on dielectric layer, on first interconnection line, the step of the described via plug of wherein said electroless plating ground deposition comprises that electroless plating ground deposition comprises the via plug of boron and phosphorus to wherein said opening at least in part;
Electroless plating ground deposit liner layer on described electroless deposition via plug, the step of the described laying of wherein said electroless plating ground deposition comprise that electroless plating ground deposition comprises the laying than the total concentration of higher boron of described via plug and phosphorus; With
On described laying, form second interconnection line.
8. method as claimed in claim 7,
The wherein said step that deposits to electroless plating described laying on described via plug is included in electroless plating ground deposit liner layer on the described via plug; And
The wherein said step that forms described second interconnection line on described laying is included in and forms described second interconnection line on the described laying.
9. method as claimed in claim 7,
The step of the described via plug of wherein said electroless plating ground deposition comprises that electroless plating ground deposition comprises less than the phosphorus of 10 atomic percents with less than the composition of the boron of 5 atomic percents; And
The step of the described laying of wherein said electroless plating ground deposition comprises that electroless plating ground deposition comprises greater than the phosphorus of 10 atomic percents with greater than the composition of the boron of 5 atomic percents.
CNB038005859A 2002-05-03 2003-04-25 Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs Expired - Fee Related CN100397612C (en)

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