JP3910973B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Description
図1は、本発明の第1の実施形態による半導体装置の製造方法により作成された半導体装置の多層配線構造の一例を示す断面図である。ここでは、3層の多層配線を例に示している。図では、本発明に直接係わる、低誘電率絶縁膜を配線間及び層間絶縁膜として使用した多層配線構造の形成に関する部分に注目して示している。したがって、実際に配線を形成する半導体(例えば、シリコン)基板には、例えば、素子分離、MOSFET等が形成されているが、ここでは説明を単純化するためにこれらの構造を省略し、半導体基板110上に形成した配線構造のみを図示している。
図5は、本発明の第2の実施形態による半導体装置の製造方法により作成された半導体装置の多層配線構造の一例を示す断面図である。ここでは、3層の多層配線を例に示している。図では、第1の実施形態と同様に本発明に直接係わる、低誘電率絶縁膜を配線間及び層間絶縁膜として使用した多層配線構造の形成に関する部分に注目して、半導体基板上に形成した配線構造のみを図示している。
この第2の実施形態による半導体装置の製造方法により作成された多層配線の構造の特徴は、配線間絶縁膜と層間絶縁膜とが2種類の異なる低誘電率材料からなる低誘電率絶縁膜であること、上記低誘電率絶縁膜は層状構造をなすため界面が周期的に存在し、第1の低誘電率材料からなる第1の低誘電率絶縁膜とその上に堆積する第2の低誘電率材料からなる第2の低誘電率絶縁膜との界面がCu配線の側面に位置すること、第2の低誘電率材料からなる第2の低誘電率絶縁膜とその上に堆積する第1の低誘電率材料からなる第3の低誘電率絶縁膜との界面がプラグと第2のCu配線とが接続する面と一致すること、及びCu配線の上側表面に配線材料拡散防止用のバリア導電性膜を有することである。また、第2のCu配線用溝の形成を選択性のあるエッチング法によって行うことから、第1の実施形態よりプロセス安定性を高くすることができる。
図8は、本発明の第3の実施形態による半導体装置の製造方法により作成された半導体装置の多層配線構造の一例を示す断面図である。ここでは、3層の多層配線を例に示している。図では、第1の実施形態と同様に本発明に直接係わる、低誘電率絶縁膜を層間絶縁膜として使用した多層配線構造の形成に関する部分に注目して、半導体基板上に形成した配線構造のみを図示している。
図12は、本発明の第4の実施形態による半導体装置の製造方法により作成された半導体装置の多層配線構造の一例を示す断面図である。ここでは、3層の多層配線を例に示している。図では、第1から第3の実施形態と同様に本発明に直接係わる、低誘電率絶縁膜を層間絶縁膜として使用した多層配線構造の形成に関する部分に注目して、半導体基板上に形成した配線構造のみを図示している。
図15は、本発明の第5の実施形態による半導体装置の製造方法により作成された半導体装置の多層配線構造の一例を示す断面図である。ここでは、3層の多層配線を例に示している。図では、第1から第4の実施形態と同様に本発明に直接係わる、低誘電率絶縁膜を層間絶縁膜として使用した多層配線構造の形成に関する部分に注目して、半導体基板上に形成した配線構造のみを図示している。
111,121,131,141…低誘電率材料からなる絶縁膜、
111a…第1の低誘電率材料からなる絶縁膜、
111b…第2の低誘電率材料からなる絶縁膜、
112,122…低誘電率材料より機械的強度が大きな材料からなる絶縁膜、
123…層間接続孔、
114,124…配線用溝、
115,125,135…配線材料拡散防止用のバリアメタル、
126,136…プラグ、
117,127,137…Cu配線、
118,128,138…配線材料拡散防止用のバリア導電性膜、
911…低誘電率絶縁膜、
912…高強度絶縁膜、
915…配線材料拡散防止用のバリアメタル、
917…Cu配線、
919…配線材料拡散防止用のバリア絶縁膜。
Claims (3)
- 第1の低誘電率材料からなる第1の絶縁膜を堆積し、
上記第1の絶縁膜上に第1の絶縁膜より機械的強度が大きい第2の絶縁膜を堆積し、
上記第1及び第2の絶縁膜に配線用溝を形成し、
上記配線用溝を配線材料で埋めて第1の配線を形成し、
上記第1の配線の上側表面に配線材料の拡散を防止する導電性膜を形成し、
上記第2の絶縁膜を除去し、
上記第1の絶縁膜上及び上記第1の配線上に配線材料の拡散を防止する第3の絶縁膜を堆積し、
上記第3の絶縁膜上に上記第1の低誘電率材料からなる第4の絶縁膜を堆積し、
上記第4の絶縁膜を上記第1の配線の上面の高さまで平坦化し、
上記第4の絶縁膜上及び上記第3の絶縁膜上に第2の低誘電率材料からなる第5の絶縁膜を形成し、
上記第3の絶縁膜及び上記第5の絶縁膜に上記第1の配線とその上側に形成する第2の配線とを接続するプラグを形成することを特徴とする半導体装置の製造方法。 - 前記導電性膜は、コバルトタングステンを含む高融点金属合金であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第3の絶縁膜は、窒化シリコン、炭化シリコン、及び炭窒化シリコンのいずれか1を含むことを特徴とする請求項1若しくは2に記載の半導体装置の製造方法。
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JP2004126980A JP3910973B2 (ja) | 2004-04-22 | 2004-04-22 | 半導体装置の製造方法 |
US10/888,518 US7205664B2 (en) | 2004-04-22 | 2004-07-12 | Semiconductor device and method for manufacturing the same |
US11/698,149 US7470609B2 (en) | 2004-04-22 | 2007-01-26 | Semiconductor device and method for manufacturing the same |
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JP2004126980A JP3910973B2 (ja) | 2004-04-22 | 2004-04-22 | 半導体装置の製造方法 |
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JP3910973B2 true JP3910973B2 (ja) | 2007-04-25 |
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US7294934B2 (en) * | 2002-11-21 | 2007-11-13 | Intel Corporation | Low-K dielectric structure and method |
US20040183202A1 (en) * | 2003-01-31 | 2004-09-23 | Nec Electronics Corporation | Semiconductor device having copper damascene interconnection and fabricating method thereof |
US6869878B1 (en) * | 2003-02-14 | 2005-03-22 | Advanced Micro Devices, Inc. | Method of forming a selective barrier layer using a sacrificial layer |
US7060619B2 (en) * | 2003-03-04 | 2006-06-13 | Infineon Technologies Ag | Reduction of the shear stress in copper via's in organic interlayer dielectric material |
US7304388B2 (en) * | 2003-06-26 | 2007-12-04 | Intel Corporation | Method and apparatus for an improved air gap interconnect structure |
US7008871B2 (en) * | 2003-07-03 | 2006-03-07 | International Business Machines Corporation | Selective capping of copper wiring |
US7344972B2 (en) * | 2004-04-21 | 2008-03-18 | Intel Corporation | Photosensitive dielectric layer |
JP2006060166A (ja) * | 2004-08-24 | 2006-03-02 | Matsushita Electric Ind Co Ltd | 電子デバイス及びその製造方法 |
-
2004
- 2004-04-22 JP JP2004126980A patent/JP3910973B2/ja not_active Expired - Fee Related
- 2004-07-12 US US10/888,518 patent/US7205664B2/en not_active Expired - Fee Related
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2007
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US20050253266A1 (en) | 2005-11-17 |
US7205664B2 (en) | 2007-04-17 |
JP2005311123A (ja) | 2005-11-04 |
US20070123029A1 (en) | 2007-05-31 |
US7470609B2 (en) | 2008-12-30 |
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