YU117089A - Uređaj i postupak za poboljšano prevođenje virtuelne adrese u realnu radi pristupa jedinici kaše memorije - Google Patents

Uređaj i postupak za poboljšano prevođenje virtuelne adrese u realnu radi pristupa jedinici kaše memorije

Info

Publication number
YU117089A
YU117089A YU117089A YU117089A YU117089A YU 117089 A YU117089 A YU 117089A YU 117089 A YU117089 A YU 117089A YU 117089 A YU117089 A YU 117089A YU 117089 A YU117089 A YU 117089A
Authority
YU
Yugoslavia
Prior art keywords
unit
access
mash
address
memory
Prior art date
Application number
YU117089A
Other languages
English (en)
Inventor
Leonard Rabins
Original Assignee
Bull Hn Information Systems Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Systems Inc. filed Critical Bull Hn Information Systems Inc.
Publication of YU117089A publication Critical patent/YU117089A/sh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Opisan je uredjaj i postupak za ubrzavanje prevodjenja virtuelne adrese, koju dostavlja centralna procesorska jedinica, u realnu adresu radi pristupa kaše memorijskoj jedinici. Tehnika je zasnovana na činjenici da će procedura po pravilu adresirati lokacije u ograničenom broju memorijskih data strana u toku značajnih intervala izvršavanja procedure. Mala pridružujuća memorija je dodata, i ona u odgovor na najmanje deo broja virtuelne strane, brzo obezbedjuje ispitivani deo broja realne strane. Ispitivani deo broja realne strane se koristi, zajedno sa (nepromenjenim) delom reči adrese, za pristup jedinici kaše direktorijuma istovremeno sa kompletnim prevodjenjem broja virtuelne strane u broj realne strane. Kada je poredjenje neuspešno, lokacijska adresa se koristi za pristup jedinici kaše direktorijuma i jedinica kaše memorije radi na tipičan način. Kada je poredjenje uspešno, pristupa se ispravnoj lokaciji jedinice kaše direktorijuma, poredjenje sadržaja jedinice kaše direktorijuma sa prevedenom poredbenom adresom može da se izvrši i pristup kaše skladišnoj jedinici, ako je potrebno, može da se nastavi.
YU117089A 1988-06-07 1989-06-07 Uređaj i postupak za poboljšano prevođenje virtuelne adrese u realnu radi pristupa jedinici kaše memorije YU117089A (sh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US20349088A 1988-06-07 1988-06-07

Publications (1)

Publication Number Publication Date
YU117089A true YU117089A (sh) 1992-07-20

Family

ID=22754220

Family Applications (1)

Application Number Title Priority Date Filing Date
YU117089A YU117089A (sh) 1988-06-07 1989-06-07 Uređaj i postupak za poboljšano prevođenje virtuelne adrese u realnu radi pristupa jedinici kaše memorije

Country Status (13)

Country Link
EP (1) EP0349757B1 (sh)
JP (1) JPH0251755A (sh)
KR (1) KR930002314B1 (sh)
CN (1) CN1024600C (sh)
AU (1) AU612035B2 (sh)
CA (1) CA1328026C (sh)
DE (1) DE68926837T2 (sh)
ES (1) ES2090023T3 (sh)
FI (1) FI96645C (sh)
HR (1) HRP921095A2 (sh)
MX (1) MX173010B (sh)
NO (1) NO176633C (sh)
YU (1) YU117089A (sh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965922B1 (en) * 2000-04-18 2005-11-15 International Business Machines Corporation Computer system and method with internal use of networking switching
US7146484B2 (en) 2004-06-15 2006-12-05 Hitachi, Ltd. Method and apparatus for caching storage system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140521A (en) * 1975-05-30 1976-12-03 Nec Corp Address exchange device
JPS51145227A (en) * 1975-06-09 1976-12-14 Nec Corp Buffer memory system
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
JPS5696334A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Prefetch system
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
JPS6049944B2 (ja) * 1980-12-29 1985-11-06 富士通株式会社 バッファ記憶制御方式
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
JPS5975482A (ja) * 1982-10-22 1984-04-28 Fujitsu Ltd バツフア・ストレ−ジ制御方式
EP0206050A3 (en) * 1985-06-28 1990-03-14 Hewlett-Packard Company Virtually addressed cache memory with physical tags

Also Published As

Publication number Publication date
NO176633B (no) 1995-01-23
CN1040446A (zh) 1990-03-14
EP0349757A2 (en) 1990-01-10
MX173010B (es) 1994-01-28
FI892779A (fi) 1989-12-08
FI892779A0 (fi) 1989-06-07
FI96645B (fi) 1996-04-15
DE68926837T2 (de) 1997-03-06
JPH0251755A (ja) 1990-02-21
EP0349757B1 (en) 1996-07-17
ES2090023T3 (es) 1996-10-16
KR930002314B1 (ko) 1993-03-29
NO176633C (no) 1995-05-03
AU612035B2 (en) 1991-06-27
FI96645C (fi) 1996-07-25
NO892310D0 (no) 1989-06-06
CA1328026C (en) 1994-03-22
KR900000773A (ko) 1990-01-31
AU3592489A (en) 1989-12-14
CN1024600C (zh) 1994-05-18
DE68926837D1 (de) 1996-08-22
HRP921095A2 (hr) 1994-04-30
EP0349757A3 (en) 1990-09-19
NO892310L (no) 1989-12-08

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