ES2090023T3 - Aparato y metodo para una conversion mejorada entre direccion virtual y direccion real para acceder a una unidad de memoria cache. - Google Patents
Aparato y metodo para una conversion mejorada entre direccion virtual y direccion real para acceder a una unidad de memoria cache.Info
- Publication number
- ES2090023T3 ES2090023T3 ES89109786T ES89109786T ES2090023T3 ES 2090023 T3 ES2090023 T3 ES 2090023T3 ES 89109786 T ES89109786 T ES 89109786T ES 89109786 T ES89109786 T ES 89109786T ES 2090023 T3 ES2090023 T3 ES 2090023T3
- Authority
- ES
- Spain
- Prior art keywords
- cache
- access
- pages
- unit
- real
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
SE DESCRIBEN APARATO Y METODO PARA EXPEDIR LA TRASLACION DE UNA DIRECCION VIRTUAL, PROVISTA POR UNA UNIDAD CENTRAL DE PROCESO, A UNA DIRECCION REAL, PARA ACCEDER A UNA UNIDAD DE MEMORIA "CACHE". LA TECNICA SE BASA EN EL HECHO DE QUE UN PROCEDIMIENTO HABITUAL DIRIGIRA LOCALIZACIONES EN UN NUMERO LIMITADO DE PAGINAS DE DATOS DE MEMORIA DURANTE INTERVALOS SIGNIFICATIVOS DE LA EJECUCION DEL PROCESO. SE PROVEE UNA PEQUEÑA MEMORIA ASOCIATIVA, LA CUAL EN RESPUESTA A AL MENOS UNA PORCION DEL NUMERO DE PAGINAS VIRTUALES, PROVEE RAPIDAMENTE UNA PORCION DE PRUEBA DEL NUMERO DE PAGINAS REALES. LA PORCION DE PRUEBA DEL NUMERO DE PAGINAS REALES SE USA, EN ADELANTE CON LAS PORCIONES DE PALABRA (NO CAMBIADAS) DE LAS DIRECCIONES, PARA ACCEDER A LA UNIDAD DE DIRECTORIO DE LA MEMORIA "CACHE" SIMULTANEAMENTE CON LA TRASLACION COMPLETA DEL NUMERO DE PAGINAS VIRTUALES AL NUMERO DE PAGINAS REALES. LA PORCION DE PRUEBA DEL NUMERO DE PAGINAS REALES SE COMPARA CON LA PORCION TRASLADADA DEL NUMERO DE PAGINAS REALES. CUANDO LA COMPARACION ES FALSA, LA DIRECCION DE LOCALIZACION SE USA PARA ACCEDER A LA UNIDAD DE DIRECTORIO CACHE Y A LA UNIDAD DE MEMORIA CACHE OPERADAS DE FORMA HABITUAL. CUANDO LA COMPARACION ES VERDADERA, LA LOCALIZACION CORRECTA DE LA UNIDAD DEL DIRECTORIO CACHE RESULTA ACCEDIDA, LA COMPARACION DE LOS CONTENIDOS DE LA UNIDAD DE DIRECTORIO CACHE CON LAS DIRECCIONES DE COMPARACION TRASLADADAS SE PUEDEN REALIZAR Y EL ACCESO A LA UNIDAD DE ALMACENAMIENTO CACHE SE PUEDE REALIZAR EN EL LUGAR ADECUADO.FIG 1
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US20349088A | 1988-06-07 | 1988-06-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2090023T3 true ES2090023T3 (es) | 1996-10-16 |
Family
ID=22754220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES89109786T Expired - Lifetime ES2090023T3 (es) | 1988-06-07 | 1989-05-31 | Aparato y metodo para una conversion mejorada entre direccion virtual y direccion real para acceder a una unidad de memoria cache. |
Country Status (13)
Country | Link |
---|---|
EP (1) | EP0349757B1 (es) |
JP (1) | JPH0251755A (es) |
KR (1) | KR930002314B1 (es) |
CN (1) | CN1024600C (es) |
AU (1) | AU612035B2 (es) |
CA (1) | CA1328026C (es) |
DE (1) | DE68926837T2 (es) |
ES (1) | ES2090023T3 (es) |
FI (1) | FI96645C (es) |
HR (1) | HRP921095A2 (es) |
MX (1) | MX173010B (es) |
NO (1) | NO176633C (es) |
YU (1) | YU117089A (es) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965922B1 (en) * | 2000-04-18 | 2005-11-15 | International Business Machines Corporation | Computer system and method with internal use of networking switching |
US7146484B2 (en) | 2004-06-15 | 2006-12-05 | Hitachi, Ltd. | Method and apparatus for caching storage system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51140521A (en) * | 1975-05-30 | 1976-12-03 | Nec Corp | Address exchange device |
JPS51145227A (en) * | 1975-06-09 | 1976-12-14 | Nec Corp | Buffer memory system |
US4170039A (en) * | 1978-07-17 | 1979-10-02 | International Business Machines Corporation | Virtual address translation speed up technique |
JPS5696334A (en) * | 1979-12-28 | 1981-08-04 | Fujitsu Ltd | Prefetch system |
US4332010A (en) * | 1980-03-17 | 1982-05-25 | International Business Machines Corporation | Cache synonym detection and handling mechanism |
JPS6049944B2 (ja) * | 1980-12-29 | 1985-11-06 | 富士通株式会社 | バッファ記憶制御方式 |
US4400774A (en) * | 1981-02-02 | 1983-08-23 | Bell Telephone Laboratories, Incorporated | Cache addressing arrangement in a computer system |
JPS5975482A (ja) * | 1982-10-22 | 1984-04-28 | Fujitsu Ltd | バツフア・ストレ−ジ制御方式 |
EP0206050A3 (en) * | 1985-06-28 | 1990-03-14 | Hewlett-Packard Company | Virtually addressed cache memory with physical tags |
-
1989
- 1989-05-31 DE DE68926837T patent/DE68926837T2/de not_active Expired - Fee Related
- 1989-05-31 EP EP89109786A patent/EP0349757B1/en not_active Expired - Lifetime
- 1989-05-31 ES ES89109786T patent/ES2090023T3/es not_active Expired - Lifetime
- 1989-06-01 AU AU35924/89A patent/AU612035B2/en not_active Ceased
- 1989-06-06 CA CA000601865A patent/CA1328026C/en not_active Expired - Fee Related
- 1989-06-06 MX MX016332A patent/MX173010B/es unknown
- 1989-06-06 CN CN89103944A patent/CN1024600C/zh not_active Expired - Fee Related
- 1989-06-06 NO NO892310A patent/NO176633C/no unknown
- 1989-06-07 FI FI892779A patent/FI96645C/fi not_active IP Right Cessation
- 1989-06-07 KR KR1019890007893A patent/KR930002314B1/ko not_active IP Right Cessation
- 1989-06-07 JP JP89145015A patent/JPH0251755A/ja active Pending
- 1989-06-07 YU YU117089A patent/YU117089A/sh unknown
-
1992
- 1992-10-23 HR HRP921095AA patent/HRP921095A2/hr not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
NO176633B (no) | 1995-01-23 |
CN1040446A (zh) | 1990-03-14 |
EP0349757A2 (en) | 1990-01-10 |
MX173010B (es) | 1994-01-28 |
FI892779A (fi) | 1989-12-08 |
FI892779A0 (fi) | 1989-06-07 |
FI96645B (fi) | 1996-04-15 |
YU117089A (sh) | 1992-07-20 |
DE68926837T2 (de) | 1997-03-06 |
JPH0251755A (ja) | 1990-02-21 |
EP0349757B1 (en) | 1996-07-17 |
KR930002314B1 (ko) | 1993-03-29 |
NO176633C (no) | 1995-05-03 |
AU612035B2 (en) | 1991-06-27 |
FI96645C (fi) | 1996-07-25 |
NO892310D0 (no) | 1989-06-06 |
CA1328026C (en) | 1994-03-22 |
KR900000773A (ko) | 1990-01-31 |
AU3592489A (en) | 1989-12-14 |
CN1024600C (zh) | 1994-05-18 |
DE68926837D1 (de) | 1996-08-22 |
HRP921095A2 (hr) | 1994-04-30 |
EP0349757A3 (en) | 1990-09-19 |
NO892310L (no) | 1989-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3687307D1 (de) | Computeranordnungen mit cache-speichern. | |
CA2022656A1 (en) | Translation look-aside buffer for a computer memory system | |
KR840001368A (ko) | 데이타 처리 시스템에서의 선택적 캐쉬 클리어링 방법과 장치 | |
KR920013131A (ko) | 내용 주소화 메모리용 우선 변환 참조 버퍼의 공간 절약을 위한 장치 및 방법 | |
KR890008691A (ko) | 데이타 프로세서 디바이스 | |
ATE254778T1 (de) | Nachschlagtabelle und verfahren zur datenspeicherung darin | |
ES2039351T3 (es) | Sistema de memoria cache virtual, organizado en paginas. | |
CA2020275A1 (en) | Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access | |
SE7706913L (sv) | Databehandlingsanordning | |
KR960018907A (ko) | 가상 기억장치 변환을 효율적으로 공용하기 위한 장치 및 방법 | |
KR840005234A (ko) | 어드레스 변환 제어방식 | |
KR920013135A (ko) | 우선변환참조버퍼에서 적중수를 증가시키기 위한 장치 | |
EP0365117A3 (en) | Data-processing apparatus including a cache memory | |
CA2107056A1 (en) | Method and System for Increased System Memory Concurrency in a Multiprocessor Computer System | |
SE8104981L (sv) | Metod och anordning for adressering av ett minne | |
ES2090023T3 (es) | Aparato y metodo para una conversion mejorada entre direccion virtual y direccion real para acceder a una unidad de memoria cache. | |
KR900018819A (ko) | 캐시 메모리 액세스 장치 및 방법 | |
KR890007161A (ko) | 프로세서-메모리 데이타 전송시에 사용되는 다중-비퍼 | |
WO1988009014A3 (en) | Memory addressing system | |
EP0206050A3 (en) | Virtually addressed cache memory with physical tags | |
KR900013510A (ko) | 캐시 메모리 | |
JPH0383150A (ja) | アドレス変換機構付キャッシュ装置の制御方式 | |
JPH05216767A (ja) | エントリ置き換え制御方式 | |
JPS57108954A (en) | Search system of electronic dictionary | |
KR940000971A (ko) | 계층적 페이지 분할 구조의 가상 메모리를 지원하는 폴리어소시에이티브 테이블 룩 어사이드 버퍼 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
Ref document number: 349757 Country of ref document: ES |
|
FG2A | Definitive protection |
Ref document number: 349757 Country of ref document: ES |