ES459518A1 - Mejoras en sistemas de tratamiento de espacios de direccion virtual plural para sistemas de tratamiento de datos. - Google Patents

Mejoras en sistemas de tratamiento de espacios de direccion virtual plural para sistemas de tratamiento de datos.

Info

Publication number
ES459518A1
ES459518A1 ES459518A ES459518A ES459518A1 ES 459518 A1 ES459518 A1 ES 459518A1 ES 459518 A ES459518 A ES 459518A ES 459518 A ES459518 A ES 459518A ES 459518 A1 ES459518 A1 ES 459518A1
Authority
ES
Spain
Prior art keywords
virtual address
virtual
processing system
addresses
real
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES459518A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES459518A1 publication Critical patent/ES459518A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Mejoras en sistemas de tratamiento de espacios de dirección virtual plural para sistemas de tratamiento de datos, que comprenden un mecanismo de traducción para traducir una dirección virtual en una dirección real y una memoria para almacenar la dirección real traducida por el mecanismo de traducción y en que, al tratar los datos, si se desea una dirección real, se almacena en la memoria, la dirección real se usa para tratamientos de datos, y si no se almacena, la dirección real deseada se obtiene con el mecanismo de traducción.
ES459518A 1976-06-08 1977-06-06 Mejoras en sistemas de tratamiento de espacios de direccion virtual plural para sistemas de tratamiento de datos. Expired ES459518A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6680776A JPS52149444A (en) 1976-06-08 1976-06-08 Multiplex virtual space processing data processing system

Publications (1)

Publication Number Publication Date
ES459518A1 true ES459518A1 (es) 1978-10-01

Family

ID=13326494

Family Applications (1)

Application Number Title Priority Date Filing Date
ES459518A Expired ES459518A1 (es) 1976-06-08 1977-06-06 Mejoras en sistemas de tratamiento de espacios de direccion virtual plural para sistemas de tratamiento de datos.

Country Status (5)

Country Link
US (1) US4145738A (es)
JP (1) JPS52149444A (es)
CA (1) CA1074455A (es)
DE (1) DE2725718C2 (es)
ES (1) ES459518A1 (es)

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* Cited by examiner, † Cited by third party
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US4136385A (en) * 1977-03-24 1979-01-23 International Business Machines Corporation Synonym control means for multiple virtual storage systems
JPS5454536A (en) * 1977-10-08 1979-04-28 Fujitsu Ltd Data processor
US4376297A (en) * 1978-04-10 1983-03-08 Signetics Corporation Virtual memory addressing device
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
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US4215402A (en) * 1978-10-23 1980-07-29 International Business Machines Corporation Hash index table hash generator apparatus
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
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US4520441A (en) * 1980-12-15 1985-05-28 Hitachi, Ltd. Data processing system
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US4374417A (en) * 1981-02-05 1983-02-15 International Business Machines Corp. Method for using page addressing mechanism
US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
JPS57143782A (en) * 1981-03-03 1982-09-06 Toshiba Corp Information processor
US4432053A (en) * 1981-06-29 1984-02-14 Burroughs Corporation Address generating apparatus and method
US4453212A (en) * 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4495565A (en) * 1981-11-09 1985-01-22 At&T Bell Laboratories Computer memory address matcher and process
JPS6047623B2 (ja) * 1982-02-12 1985-10-22 株式会社日立製作所 アドレス変換方式
US4539637A (en) * 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
US4714990A (en) * 1982-09-18 1987-12-22 International Computers Limited Data storage apparatus
USRE37305E1 (en) * 1982-12-30 2001-07-31 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4577274A (en) * 1983-07-11 1986-03-18 At&T Bell Laboratories Demand paging scheme for a multi-ATB shared memory processing system
US4714993A (en) * 1983-10-18 1987-12-22 International Business Machines Corporation Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system
JPS6091462A (ja) * 1983-10-26 1985-05-22 Toshiba Corp 演算制御装置
US4589092A (en) * 1983-12-12 1986-05-13 International Business Machines Corporation Data buffer having separate lock bit storage array
US4731740A (en) * 1984-06-30 1988-03-15 Kabushiki Kaisha Toshiba Translation lookaside buffer control system in computer or virtual memory control scheme
JPS61190638A (ja) * 1985-02-20 1986-08-25 Hitachi Ltd 仮想計算機のフアイル制御方式
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
JPH0658649B2 (ja) * 1985-10-28 1994-08-03 株式会社日立製作所 仮想記憶装置における領域管理方法
US5230045A (en) * 1986-11-12 1993-07-20 Xerox Corporation Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus
US5123101A (en) * 1986-11-12 1992-06-16 Xerox Corporation Multiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator miss
EP0282213A3 (en) * 1987-03-09 1991-04-24 AT&T Corp. Concurrent context memory management unit
US5278840A (en) * 1987-07-01 1994-01-11 Digital Equipment Corporation Apparatus and method for data induced condition signalling
US5008811A (en) * 1988-02-10 1991-04-16 International Business Machines Corp. Control mechanism for zero-origin data spaces
US4945480A (en) * 1988-02-10 1990-07-31 International Business Machines Corporation Data domain switching on program address space switching and return
US4943913A (en) * 1988-02-10 1990-07-24 International Business Machines Corporation Operating system accessing control blocks by using home address space segment table to control instruction and operand fetch and store operations
JPH01255945A (ja) * 1988-04-06 1989-10-12 Hitachi Ltd 仮想計算機におけるアドレス変換装置
GB8825764D0 (en) * 1988-11-03 1988-12-07 Lucas Ind Plc Computer memory addressing system
US5095420A (en) * 1988-11-21 1992-03-10 International Business Machines Method and system for performing virtual address range mapping in a virtual storage data processing system
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
DE4019961C2 (de) * 1989-06-23 1994-11-24 Hitachi Ltd Steuerung für den Zugriff auf einen Adreßumsetzungsspeicher in einem Prozessorsystem
JPH0679296B2 (ja) * 1989-09-22 1994-10-05 株式会社日立製作所 多重仮想アドレス空間アクセス方法およびデータ処理装置
US5497474A (en) * 1993-02-25 1996-03-05 Franklin Electronic Publishers, Incorporated Data stream addressing
US5666556A (en) * 1993-12-30 1997-09-09 Intel Corporation Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
US6385712B1 (en) * 1999-10-25 2002-05-07 Ati International Srl Method and apparatus for segregation of virtual address space
GB2357166B (en) * 1999-12-07 2001-10-31 Marconi Comm Ltd Memory access system
US6560687B1 (en) * 2000-10-02 2003-05-06 International Business Machines Corporation Method of implementing a translation lookaside buffer with support for a real space control
US7227994B2 (en) * 2003-03-20 2007-06-05 International Business Machines Corporation Method and apparatus for imbedded pattern recognition using dual alternating pointers
US7366352B2 (en) * 2003-03-20 2008-04-29 International Business Machines Corporation Method and apparatus for performing fast closest match in pattern recognition
JP4085328B2 (ja) * 2003-04-11 2008-05-14 ソニー株式会社 情報処理装置および方法、記録媒体、プログラム、並びに撮像装置
US20070011429A1 (en) * 2005-07-07 2007-01-11 Vasudevan Sangili Virtual memory key generation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1365593A (es) * 1962-06-22 1964-11-03
JPS532296B2 (es) * 1973-03-19 1978-01-26
US3825904A (en) * 1973-06-08 1974-07-23 Ibm Virtual memory system
JPS5315778B2 (es) * 1973-07-18 1978-05-27
JPS5434577B2 (es) * 1974-06-28 1979-10-27

Also Published As

Publication number Publication date
JPS52149444A (en) 1977-12-12
DE2725718A1 (de) 1977-12-15
CA1074455A (en) 1980-03-25
US4145738A (en) 1979-03-20
DE2725718C2 (de) 1985-05-02

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