JPS51140521A - Address exchange device - Google Patents
Address exchange deviceInfo
- Publication number
- JPS51140521A JPS51140521A JP50065776A JP6577675A JPS51140521A JP S51140521 A JPS51140521 A JP S51140521A JP 50065776 A JP50065776 A JP 50065776A JP 6577675 A JP6577675 A JP 6577675A JP S51140521 A JPS51140521 A JP S51140521A
- Authority
- JP
- Japan
- Prior art keywords
- exchange device
- address exchange
- address
- accomplish
- combining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: By combining a method which uses an address array and the one which uses an association memory, to accomplish an address exchange with high probability by a relatively small hardware.
COPYRIGHT: (C)1976,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50065776A JPS51140521A (en) | 1975-05-30 | 1975-05-30 | Address exchange device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50065776A JPS51140521A (en) | 1975-05-30 | 1975-05-30 | Address exchange device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS51140521A true JPS51140521A (en) | 1976-12-03 |
JPS5760709B2 JPS5760709B2 (en) | 1982-12-21 |
Family
ID=13296762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50065776A Granted JPS51140521A (en) | 1975-05-30 | 1975-05-30 | Address exchange device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS51140521A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01109403A (en) * | 1987-10-09 | 1989-04-26 | Instron Corp | Circuit for interactive control of multiple control elements |
JPH0251755A (en) * | 1988-06-07 | 1990-02-21 | Bull Hn Inf Syst Inc | Virtual/real address converter for cash memory access |
JPWO2008155851A1 (en) * | 2007-06-20 | 2010-08-26 | 富士通株式会社 | Arithmetic processing device, entry control program, and entry control method |
-
1975
- 1975-05-30 JP JP50065776A patent/JPS51140521A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01109403A (en) * | 1987-10-09 | 1989-04-26 | Instron Corp | Circuit for interactive control of multiple control elements |
JPH0251755A (en) * | 1988-06-07 | 1990-02-21 | Bull Hn Inf Syst Inc | Virtual/real address converter for cash memory access |
JPWO2008155851A1 (en) * | 2007-06-20 | 2010-08-26 | 富士通株式会社 | Arithmetic processing device, entry control program, and entry control method |
JP4812876B2 (en) * | 2007-06-20 | 2011-11-09 | 富士通株式会社 | Arithmetic processing device and control method of arithmetic processing device |
US8688952B2 (en) | 2007-06-20 | 2014-04-01 | Fujitsu Limited | Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB |
Also Published As
Publication number | Publication date |
---|---|
JPS5760709B2 (en) | 1982-12-21 |
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