KR840005234A - 어드레스 변환 제어방식 - Google Patents

어드레스 변환 제어방식 Download PDF

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Publication number
KR840005234A
KR840005234A KR1019830002935A KR830002935A KR840005234A KR 840005234 A KR840005234 A KR 840005234A KR 1019830002935 A KR1019830002935 A KR 1019830002935A KR 830002935 A KR830002935 A KR 830002935A KR 840005234 A KR840005234 A KR 840005234A
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KR
South Korea
Prior art keywords
address translation
address
check mode
buffer
control method
Prior art date
Application number
KR1019830002935A
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English (en)
Other versions
KR890000102B1 (ko
Inventor
히로사다 도네
Original Assignee
야마모도 다꾸마
후지쑤 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 야마모도 다꾸마, 후지쑤 가부시기가이샤 filed Critical 야마모도 다꾸마
Publication of KR840005234A publication Critical patent/KR840005234A/ko
Application granted granted Critical
Publication of KR890000102B1 publication Critical patent/KR890000102B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)

Abstract

내용 없음

Description

어드레스 변환 제어방식
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 대상이 되는 데이타 처리장치의 블록선도의 개략도.
제3도는 본 발명의 한가지 실시예의 어드레스 변환 제어방식의 블록선도.
제4도는 제3도에 예시된 동적 어드레스 변환의 일예를 나타낸 블록선도.

Claims (1)

  1. 실효 어드레스를 물리 어드레스로 변환하는 어드레스 변환시스템과 해당 변환된 결과의 변환쌍을 기억하는 어드레스 변환 완충기와, 어드레스 변환 완충기에 축적시킨 기억보호 키이를 구성시킴으로써 어드레스 변환 완충기에 대해 색인하여 보호키이에 입각해서 기억보호 체크를 하도록한 기억보호 체크 모우드와 보호키이에 입각하여 기억보호 체크를 필요로 하지 않는 비체크 모우드를 가진 데이타 처리장치에 있어서 위의 기억보호 체크 모우드시에는 어드레스 변환시스템에 의해 어드레스 변환이 이루어질 경우 해당 변환결과를 어드레스 변환 완충기에 축적시키도록 제어하며, 위의 비체크 모우드시에는 어드레스 변환 시스템에 의해 어드레스 변환이 이루어질 경우 해당 변환 결과를 어드레스 변환 완충기에 축적시킬 필요없이 직접 사용할 수 있도록함을 특징으로 하는 어드레스 변환 제어방식.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830002935A 1982-06-30 1983-06-29 아드레스 변환 제어방식 KR890000102B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP113310 1982-06-30
JP57113310A JPS6047624B2 (ja) 1982-06-30 1982-06-30 アドレス変換制御方式
JP57-113310 1982-06-30

Publications (2)

Publication Number Publication Date
KR840005234A true KR840005234A (ko) 1984-11-05
KR890000102B1 KR890000102B1 (ko) 1989-03-07

Family

ID=14608990

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002935A KR890000102B1 (ko) 1982-06-30 1983-06-29 아드레스 변환 제어방식

Country Status (9)

Country Link
US (1) US4604688A (ko)
EP (1) EP0098168B1 (ko)
JP (1) JPS6047624B2 (ko)
KR (1) KR890000102B1 (ko)
AU (1) AU543336B2 (ko)
BR (1) BR8303526A (ko)
CA (1) CA1195010A (ko)
DE (1) DE3377948D1 (ko)
ES (1) ES8405177A1 (ko)

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US4638426A (en) * 1982-12-30 1987-01-20 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4731740A (en) * 1984-06-30 1988-03-15 Kabushiki Kaisha Toshiba Translation lookaside buffer control system in computer or virtual memory control scheme
IN165278B (ko) * 1984-09-21 1989-09-09 Digital Equipment Corp
JPS61166653A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd アドレス変換エラー処理方法
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US5060137A (en) * 1985-06-28 1991-10-22 Hewlett-Packard Company Explicit instructions for control of translation lookaside buffers
US4777589A (en) * 1985-06-28 1988-10-11 Hewlett-Packard Company Direct input/output in a virtual memory system
JPS62117001A (ja) * 1985-11-16 1987-05-28 Hitachi Ltd プログラマブルシ−ケンスコントロ−ラの入出力処理方法
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5249276A (en) * 1987-06-22 1993-09-28 Hitachi, Ltd. Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge
US5226132A (en) * 1988-09-30 1993-07-06 Hitachi, Ltd. Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (sto) while using space registers as storage devices for a data processing system
US4926481A (en) * 1988-12-05 1990-05-15 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Computer access security code system
US5237668A (en) * 1989-10-20 1993-08-17 International Business Machines Corporation Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
EP0690386A1 (en) * 1994-04-04 1996-01-03 International Business Machines Corporation Address translator and method of operation
US5724551A (en) * 1996-05-23 1998-03-03 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage keys for controlling accesses to the buffers
US5802397A (en) * 1996-05-23 1998-09-01 International Business Machines Corporation System for storage protection from unintended I/O access using I/O protection key by providing no control by I/O key entries over access by CP entity
US5900019A (en) * 1996-05-23 1999-05-04 International Business Machines Corporation Apparatus for protecting memory storage blocks from I/O accesses
US5787309A (en) * 1996-05-23 1998-07-28 International Business Machines Corporation Apparatus for protecting storage blocks from being accessed by unwanted I/O programs using I/O program keys and I/O storage keys having M number of bits
US5809546A (en) * 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
US6442664B1 (en) * 1999-06-01 2002-08-27 International Business Machines Corporation Computer memory address translation system
US20030115476A1 (en) * 2001-10-31 2003-06-19 Mckee Bret Hardware-enforced control of access to memory within a computer using hardware-enforced semaphores and other similar, hardware-enforced serialization and sequencing mechanisms
US7155726B2 (en) * 2003-10-29 2006-12-26 Qualcomm Inc. System for dynamic registration of privileged mode hooks in a device
US9384144B1 (en) * 2014-03-25 2016-07-05 SK Hynix Inc. Error detection using a logical address key
US10255202B2 (en) * 2016-09-30 2019-04-09 Intel Corporation Multi-tenant encryption for storage class memory

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US4038645A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Non-translatable storage protection control system
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US4500952A (en) * 1980-05-23 1985-02-19 International Business Machines Corporation Mechanism for control of address translation by a program using a plurality of translation tables
US4430705A (en) * 1980-05-23 1984-02-07 International Business Machines Corp. Authorization mechanism for establishing addressability to information in another address space
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
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Also Published As

Publication number Publication date
DE3377948D1 (en) 1988-10-13
BR8303526A (pt) 1984-02-07
EP0098168A2 (en) 1984-01-11
AU543336B2 (en) 1985-04-18
ES523748A0 (es) 1984-05-16
KR890000102B1 (ko) 1989-03-07
US4604688A (en) 1986-08-05
AU1641083A (en) 1984-01-05
ES8405177A1 (es) 1984-05-16
CA1195010A (en) 1985-10-08
EP0098168B1 (en) 1988-09-07
JPS6047624B2 (ja) 1985-10-22
JPS595479A (ja) 1984-01-12
EP0098168A3 (en) 1985-11-06

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