WO2015090016A1 - 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置 - Google Patents

薄膜晶体管和阵列基板及其各自制备方法、以及显示装置 Download PDF

Info

Publication number
WO2015090016A1
WO2015090016A1 PCT/CN2014/079743 CN2014079743W WO2015090016A1 WO 2015090016 A1 WO2015090016 A1 WO 2015090016A1 CN 2014079743 W CN2014079743 W CN 2014079743W WO 2015090016 A1 WO2015090016 A1 WO 2015090016A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact region
film transistor
substrate
thin film
thickness
Prior art date
Application number
PCT/CN2014/079743
Other languages
English (en)
French (fr)
Inventor
高涛
周伟峰
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/422,213 priority Critical patent/US9391207B2/en
Publication of WO2015090016A1 publication Critical patent/WO2015090016A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of display technologies, and in particular to a low temperature polysilicon thin film transistor and a method for fabricating the same, comprising the array substrate of the low temperature polysilicon thin film transistor and a method for preparing the array substrate, and a display device including the array substrate.
  • a thin film transistor is generally used as a switching element to control the operation of a pixel unit or as a driving element to drive a pixel unit.
  • Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) according to the properties of their silicon thin films.
  • a-Si amorphous silicon
  • poly-Si polycrystalline silicon
  • a-Si amorphous silicon
  • polysilicon thin film transistors have higher electron mobility, better liquid crystal characteristics and less leakage current, so displays made using polysilicon thin film transistors have higher resolution and faster.
  • the reaction speed has led to polysilicon technology, especially low-temperature polysilicon technology, which has gradually replaced amorphous silicon technology into the mainstream of thin film transistor research and development.
  • a conventional array substrate includes a substrate 101 and a low temperature polysilicon thin film transistor disposed thereon, the low temperature polysilicon thin film transistor including a buffer layer 102 and an active layer 103 sequentially disposed on the substrate 101.
  • the active layer 103 Connected to the active layer 103.
  • the active layer 103 is divided into a source contact region that is in contact with the source electrode 1071, a drain contact region that is in contact with the drain electrode 1072, and is sandwiched between the source contact region and the drain contact region.
  • the semiconductor channel region is ion-implanted into the source contact region and the drain contact region of the active layer 103 such that the source contact region and the drain contact region of the active layer become conductors.
  • a storage capacitor is further disposed on the array substrate, and the first electrode 108 of the storage capacitor may be formed in synchronization with the active layer 103, and the second electrode 109 of the storage capacitor may be synchronized with the gate 105. to make.
  • the inventors have found that at least the following problems exist in the prior art:
  • the process of a low-temperature polysilicon thin film transistor has many disadvantages, such as poor yield, complicated process, high cost, etc.
  • the energy of the implanted ions is extremely high. It is easy to cause the curing of the photoresist, which leads to residual photoresist, which affects the next step; and the mask used in the generation of commonly used low-temperature polysilicon thin film transistors is up to
  • the technical problem to be solved by the present invention includes providing a low-temperature polysilicon thin film transistor with simple structure and easy preparation, a preparation method thereof, an array substrate, a preparation method thereof and a display device, aiming at the above problems existing in the existing low-temperature polysilicon thin film transistor .
  • a technical solution to solve the technical problem of the present invention is to provide a low temperature polysilicon thin film transistor, comprising: an active layer disposed on a substrate, and a source and a drain respectively connected to the active layer, the active The layer includes a source contact region, a drain contact region, and a semiconductor region disposed between the source contact region and the drain contact region, wherein the source contact region and the drain contact region are both electrically conductive, and The source contact region and the drain contact region each include a semiconductor body and ions distributed in the semiconductor body, the source directly covers the source contact region, and the drain directly covers the drain contact Area.
  • the source of the low temperature polysilicon thin film transistor of the present invention directly covers the source contact region of the active layer, and the drain directly covers the drain contact region of the active layer, and does not need to be etched and contacted compared with the existing low temperature polysilicon thin film transistor.
  • the holes are such that the source and the drain of the thin film transistor are respectively connected to the active layer, thereby saving manufacturing cost and improving production efficiency, and at the same time making the structure of the thin film transistor simpler.
  • the low temperature polysilicon thin film transistor further comprises: a buffer layer disposed between the substrate and the active layer.
  • the low temperature polysilicon thin film transistor further includes: a gate insulating layer and a gate, the gate passing through the gate insulating layer and the source, the drain, and the active Layer insulation setting.
  • a technical solution to solve the technical problem of the present invention is to provide a method for preparing a low temperature polycrystalline silicon thin film transistor, which comprises:
  • the active layer including a source contact region, a drain contact region, and a source contact region and a drain contact region
  • the semiconductor region, the source contact region and the drain contact region are both electrically conductive, and the source contact region and the drain contact region each comprise a semiconductor body and ions distributed in the semiconductor body ;
  • step 2) On the substrate on which step 2) is completed, a pattern including a source and a drain of the thin film transistor is formed, wherein the source directly covers the source contact region, and the drain directly covers the drain contact region.
  • the preparation method of the invention shortens the process time, improves the production efficiency, and further saves the production cost.
  • the step 2) specifically includes:
  • the intermediate region of the semiconductor substrate is corresponding to the first thickness of the photoresist, so that the two sides of the semiconductor substrate respectively correspond to the second thickness of the photoresist, and the first thickness of the photoresist is thicker than the second thickness of the photoresist.
  • step 22) performing ashing on the substrate in which step 21) is completed, removing the second thickness of the photoresist corresponding to the two sides of the semiconductor substrate, and changing the first thickness of the photoresist corresponding to the intermediate portion of the semiconductor substrate a three-thickness photoresist, and a thickness of the third thickness of the photoresist is equal to a difference in thickness between the first thickness of the photoresist and the second thickness of the photoresist;
  • step 23) performing ion implantation on the substrate on which step 22) is completed, so that a region of the semiconductor substrate not covered with the third thickness of the photoresist is changed into a conductor region, thereby forming a pattern including the active layer, and the semiconductor substrate is not covered a region of the third thickness of the photoresist, that is, the source contact region and the drain contact region, and a region of the semiconductor substrate covered with the third thickness of the photoresist, that is, the source contact region and the drain contact region Half between Conductor area.
  • the step 3) specifically includes:
  • a thin metal film is formed to form a pattern including a source and a drain of the thin film transistor.
  • the method further includes:
  • a buffer layer is formed on the substrate.
  • the method further includes:
  • step 3) forming a gate insulating layer on the substrate on which step 3) is completed;
  • step 4) On the substrate on which step 4) is completed, a pattern including the gate of the thin film transistor is formed by a patterning process.
  • the step 1) specifically includes:
  • the amorphous silicon semiconductor film after dehydrogenation is recrystallized by an excimer laser annealing process to form a polycrystalline silicon semiconductor film.
  • a technical solution to solve the technical problem of the present invention is to provide an array substrate comprising the above thin film transistor.
  • the array substrate of the present invention includes the above-described thin film transistor, its structure is simple.
  • the array substrate further includes a storage capacitor, and the storage capacitor includes a first electrode and a second electrode.
  • the first electrode of the storage capacitor is in the same layer and the same material as the source contact region and the drain contact region in the active layer of the low temperature polysilicon thin film transistor
  • the second electrode of the storage capacitor is The gate of the low-temperature polysilicon thin film transistor has the same layer and the same material, or the first electrode of the storage capacitor is in the same layer and the same material as the source and the drain of the low-temperature polysilicon thin film transistor.
  • the technical solution for solving the technical problem of the present invention is to provide a method for fabricating an array substrate, the array substrate comprising a low temperature polysilicon thin film transistor, the method for preparing the array substrate comprising the step of forming a low temperature polysilicon thin film transistor, and the low The tempered polysilicon thin film transistor is prepared by the above method.
  • the method for fabricating the array substrate further includes preparing a storage capacitor, and the first electrode of the storage capacitor is formed in synchronization with a source contact region and a drain contact region in an active layer of the low temperature polysilicon thin film transistor.
  • the second electrode of the storage capacitor is formed in synchronization with the gate of the low temperature polysilicon thin film transistor.
  • a technical solution to solve the technical problem of the present invention is to provide a display device including the above array substrate.
  • the display device of the present invention includes the above array substrate, the structure is simple and the cost is relatively low.
  • 1 is a schematic structural view of a conventional array substrate
  • FIG. 2 is a schematic view showing the structure of a low temperature polysilicon thin film transistor of Embodiment 1 of the present invention
  • 3A to 3F are schematic views showing a manufacturing process of a low temperature polysilicon thin film transistor of Embodiment 2 of the present invention.
  • FIG. 4A to 4E are schematic views showing a manufacturing process of the structure shown in Fig. 3B; and Fig. 5 is a schematic structural view of the array substrate of the embodiment 3 of the present invention.
  • the reference numerals are: 101, substrate; 102, buffer layer; 103, active layer; 1031, polysilicon semiconductor film; 103A, semiconductor substrate; 104, gate insulating layer; 105, gate; 106, planarization layer 107, source and drain metal film; 1071, source; 1072, drain; 108, the first electrode of the storage capacitor; 109, the second electrode of the storage capacitor; 110, the first thickness of the photoresist; a thickness of photoresist; 112, a third thickness of photoresist; 113, a passivation layer; 114, a pixel electrode.
  • the embodiment provides a low temperature polysilicon thin film transistor, comprising: an active layer 103 disposed on a substrate 101, and a source 1071 and a drain 1072 respectively connected to the active layer 103,
  • the active layer 103 includes a source contact region, a drain contact region, and a semiconductor region disposed between the source contact region and the drain contact region, the source electrode 1071 directly covering the source contact region, the drain
  • the pole 1072 directly covers the drain contact region, wherein the source contact region and the drain contact region are both electrically conductive, and the source contact region and the drain contact region both comprise a semiconductor substrate and are distributed in the The ions in the semiconductor matrix.
  • the source 1071 of the low temperature polysilicon thin film transistor provided in this embodiment directly covers the source contact region of the active layer 103, and the drain 1072 directly covers the drain contact region of the active layer 103, and is adjacent to the existing low temperature polysilicon thin film transistor. In comparison, it is not necessary to etch the contact vias so that the source 1071 and the drain 1072 of the thin film transistor are respectively connected to the active layer 103, thereby saving manufacturing cost and improving production efficiency, and at the same time making the structure of the thin film transistor simpler.
  • the semiconductor region of the active layer 103, and the semiconductor contact regions of the source contact region and the drain contact region of the active layer 103 are uniform.
  • ions in the semiconductor substrate distributed in the source contact region and ions distributed in the semiconductor substrate in the drain contact region are not particularly specified as long as the source contact region and the drain contact region can be made conductive. can.
  • the ions can be boron ions.
  • a buffer layer 102 is further disposed between the substrate 101 and the active layer 103, and the buffer layer 102 is generally composed of an insulating material. Since the amorphous silicon semiconductor needs to be converted into a polycrystalline silicon semiconductor by laser annealing when preparing the active layer 103 of the low temperature polysilicon thin film transistor, a higher laser annealing temperature is applied to the substrate 101 (for example, glass) disposed under the active layer 103. The substrate has an influence, so it is necessary to provide the buffer layer 102 between the substrate 101 and the active layer 103.
  • the thin film transistor further includes a gate insulating layer 104 and a gate electrode 105,
  • the gate insulating layer 104 separates the gate electrode 105 from the source electrode 1071, the drain electrode 1072, and the active layer 103, thereby insulating the gate electrode 105 from the source electrode 1071, the drain electrode 1072, and the active layer 103.
  • Example 2
  • this embodiment provides a method for fabricating a low-temperature polysilicon thin film transistor, which specifically includes the following steps:
  • Step 1 A buffer layer 102 is formed on the substrate 101 by a plasma enhanced chemical vapor deposition (PECVD) process, as shown in FIG. 3A.
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the buffer layer 102 may be silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), and aluminum oxide (AlOx).
  • the corresponding reaction gas may be a mixed gas of SiH 4 , ⁇ 3 and N 2 , or SiH 2 Cl 2 bandit mixed gas of N 2 and 3, the buffer layer 102 in a thickness between 2000 a -3000 a, skilled in the art may be specifically set according to the thickness of the buffer layer 102 to the actual situation.
  • the active layer 103 includes a source contact region, a drain contact region, and a source. a semiconductor region between the contact region and the drain contact region, wherein the source contact region and the drain contact region are both electrically conductive, and the source contact region and the drain contact region both comprise a semiconductor body and Ions distributed within the semiconductor matrix.
  • step two As shown in FIG. 4A-4E, the specific steps of step two include:
  • amorphous silicon ( a- Si) semiconductor film on the substrate 101 of the first step; dehydrogenating the amorphous silicon semiconductor film by an annealing process; and removing the hydrogen after excimer by an excimer laser annealing process
  • the crystalline silicon semiconductor film is recrystallized to form a polycrystalline silicon semiconductor film 1031 as shown in Fig. 4A.
  • the thickness of the amorphous silicon semiconductor film may be between 300 A and 1000 A, and the corresponding reaction gas may be a mixed gas of SiH 4 and H 2 or a mixed gas of SiH 2 Cl 2 and H 2 . 52.
  • a photoresist 110 of a first thickness is applied, as shown in FIG. 4B, and passed through a gray mask.
  • the halftone mask exposes and develops the substrate 101 coated with the photoresist 110 of the first thickness to form a pattern including the semiconductor substrate 103 A while lithography corresponding to the first thickness of the semiconductor substrate 103A.
  • the photoresist 110 has two sides of the semiconductor substrate 103A corresponding to the second thickness of the photoresist 111, and the first thickness of the photoresist 110 is thicker than the second thickness of the photoresist 111, as shown in FIG. 4C;
  • the exposure process by the gray mask or the halftone mask is an existing process, and will not be described in detail herein.
  • removing the photoresist 111 of the second thickness corresponding to the two sides of the semiconductor substrate 103A, and making the first thickness of the photoresist corresponding to the intermediate region of the semiconductor substrate 103A. 110 becomes a third thickness of the photoresist 112, and the thickness of the third thickness of the photoresist 112 is equal to the difference in thickness between the first thickness of the photoresist 110 and the second thickness of the photoresist 111, as shown in FIG. 4D. ;
  • Performing ion implantation on the substrate 101 completing step S3 such that both side regions of the semiconductor substrate 103A, that is, regions of the semiconductor substrate 103A not covered with the third thickness of the photoresist 111 are changed into conductor regions, thereby forming active includes The pattern of the layer 103, as shown in FIG.
  • the active layer 103 includes a source contact region, a drain contact region, and a semiconductor region disposed between the source contact region and the drain contact region, and the semiconductor substrate 103A is not A region of the photoresist 111 covered with a third thickness, that is, the source contact region and the drain contact region, and a region of the semiconductor substrate 103A covered with the third thickness of the photoresist 111, that is, the source contact region And a semiconductor region between the drain contact regions; wherein, in the ion implantation process, the implanted ions are shed ions, and the reaction gas has a concentration of 10% B 2 H 6o
  • Step 3 On the substrate 101 on which the second step is completed, a source/drain metal film 107 is deposited by magnetron sputtering. As shown in FIG. 3C, a pattern including the thin film transistor source 1071 and the drain 1072 is formed, such as As shown in FIG. 3D, the source electrode 1071 directly covers the source contact region, and the drain electrode 1072 directly covers the drain contact region. It should be noted that the third thickness of the photoresist 112 over the semiconductor region of the active layer 103 and the third thickness may be removed by a lift off process. The source/drain metal film 107 over the photoresist 112 is removed by lift-off, and finally a pattern including the thin film transistor source 1071 and the drain 1072 is formed.
  • the material of the source electrode 1071 and the drain electrode 1072 may be molybdenum (Mo), molybdenum rhenium H (MoNb), 4 Lu (A1), 4 Lu (AlNd), 4 (Ti) and 4 (Cu) a single layer film formed of any one of materials, or a single layer film or a multilayer composite film formed of any two or more of the materials, and the materials of the source electrode 1071 and the drain electrode 1072 are preferably Mo, A1 and Mo a single layer film formed of any one of the alloys of A1, or a multilayer composite film formed of any two or more of the materials, the source 1071 and the drain 1072 are each 1500 A - 4000 A Between the person skilled in the art, the thickness of the source 1071 and the drain 1072 can be specifically set according to specific conditions.
  • Step 4 On the substrate 101 on which the third step is completed, the gate insulating layer 104 is formed by a method such as thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition or sputtering.
  • Figure 3E shows.
  • the material of the gate insulating layer 104 may be silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), and aluminum oxide.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • Step 5 On the substrate 101 on which the step 4 is completed, a gate metal film is deposited by magnetron sputtering, and a pattern including the thin film transistor gate 105 is formed by a patterning process, as shown in FIG. 3F.
  • the material of the gate electrode 105 may be any one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • the preparation method of the low-temperature polysilicon thin film transistor provided by the embodiment is simple in process and easy to implement, especially in the S2 of the second step, using a gray mask or a half
  • the color mask mask exposes and develops the first thickness of the photoresist 110, which reduces the number of masks used in the process, shortens the process time, and improves the production efficiency.
  • the low temperature polysilicon thin film transistor of Embodiment 1 can be prepared by the preparation method of this embodiment.
  • Example 3 Example 3:
  • the embodiment provides an array substrate including the low temperature polysilicon thin film transistor described in Embodiment 1, and a storage capacitor, wherein the first electrode 108 of the storage capacitor and the low temperature polysilicon
  • the source contact region and the drain contact region of the active layer 103 of the thin film transistor are the same layer and the same material
  • the second electrode 109 of the storage capacitor is in the same layer and the same material as the gate 105 of the low temperature polysilicon thin film transistor.
  • the first electrode 108 of the storage capacitor may also be of the same layer and the same material as the source 1071 and the drain 1072 of the low temperature polysilicon film transistor.
  • the specific formation method is the same as the existing method, and will not be described in detail herein.
  • the array substrate of the embodiment further includes a passivation layer 113 disposed above the gate electrode 105 of the low temperature polysilicon thin film transistor, and a pixel electrode 114 disposed above the passivation layer 113, the pixel electrode 114 passing through the passivation
  • the contact vias of the layer 113 and the gate insulating layer 104 are connected to the drain 1072 of the low temperature polysilicon thin film transistor.
  • the array substrate of the present embodiment includes the low temperature polysilicon film transistor described in Embodiment 1, the structure is simple and the preparation method is simple.
  • the embodiment provides a method for preparing an array substrate.
  • the array substrate comprises a low temperature polysilicon thin film transistor.
  • the low temperature polysilicon thin film transistor is prepared by the preparation method described in Embodiment 2, and details are not described herein.
  • the preparation method of the array substrate further includes the preparation of a storage capacitor, and the first electrode 108 of the storage capacitor is formed in synchronization with the source contact region and the drain contact region of the active layer 103 of the low temperature polysilicon thin film transistor.
  • the second electrode 109 of the storage capacitor is formed in synchronization with the gate 105 of the low temperature polysilicon thin film transistor.
  • the first electrode 108 of the storage capacitor may also be formed in synchronization with the source 1071 and the drain 1072 of the low temperature polysilicon thin film transistor.
  • the embodiment provides a display device, which includes the array substrate in Embodiment 3.
  • the display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like. Or parts.
  • the display device of this embodiment has the array substrate of the third embodiment, so that the cost is low.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅薄膜晶体管及其制备方法、阵列基板及其制备方法和显示装置，属于液晶显示领域，其可解决现有的低温多晶硅薄膜晶体管结构复杂且制作步骤繁琐的问题。该低温多晶硅薄膜晶体管包括：设置在基底（101）上的有源层（103），以及分别与有源层（103）连接的源极（1071）和漏极（1072），所述有源层（103）包括源极接触区、漏极接触区，以及设于源极接触区和漏极接触区之间的半导体区，所述源极接触区和所述漏极接触区均能够导电，且所述源极接触区和所述漏极接触区均包括半导体基体和分布在所述半导体基体内的离子，所述源极（1071）直接覆盖所述源极接触区，所述漏极（1072）直接覆盖漏极接触区。

Description

薄膜晶体管和阵列基板及其各自制备方法、 以及显示装置 技术领域
本发明属于显示技术领域， 具体涉及一种低温多晶硅薄膜晶 体管及其制备方法， 包括所述低温多晶硅薄膜晶体管的阵列基板 及该阵列基板的制备方法， 和包括该阵列基板的显示装置。 背景技术
在显示技术领域， 薄膜晶体管一般用作开关元件， 以控制像 素单元的工作， 或是用作驱动元件来驱动像素单元。 薄膜晶体管 按照其硅薄膜的性质通常可分为非晶硅 ( a-Si )与多晶硅 ( poly-Si ) 两种。 与非晶硅薄膜晶体管相比较， 多晶硅薄膜晶体管有更高的 电子迁移率， 更佳的液晶特性以及较少的漏电流， 因此利用多晶 硅薄膜晶体管制作的显示器会有较高的分辨率以及较快的反应速 度， 导致多晶硅技术， 尤其是低温多晶硅技术已逐渐取代非晶硅 技术成为薄膜晶体管研发的主流。
如图 1所示， 现有的一种阵列基板包括基底 101和设于其上 的低温多晶硅薄膜晶体管， 所述低温多晶硅薄膜晶体管包括依次 设置在基底 101上的緩冲层 102、 有源层 103、 栅极绝缘层 104、 栅极 105、平坦化层 106、源极 1071和漏极 1072,其中，源极 1071 和漏极 1072分别通过贯穿栅极绝缘层 104和平坦化层 106的接触 过孔与有源层 103连接。 需要说明的是， 所述有源层 103分为与 源极 1071接触的源极接触区， 与漏极 1072接触的漏极接触区， 以及夹在源极接触区与漏极接触区之间的半导体沟道区， 通过对 有源层 103 的源极接触区与漏极接触区进行离子注入， 使得有源 层的源极接触区与漏极接触区变为导体。 当然， 该阵列基板上还 设置有存储电容，所述存储电容的第一电极 108可以与有源层 103 同步形成， 所述存储电容的第二电极 109可以与栅极 105 同步形 成。
发明人发现， 现有技术中至少存在如下问题： 低温多晶硅薄 膜晶体管的工艺有着许多缺点， 例如合格率较差、 工艺复杂、 成 本较高等； 而且， 在离子注入工艺过程中， 注入离子的能量极易 引起光刻胶的固化， 导致光刻胶残留， 从而影响下步工序； 并且 常用的低温多晶硅薄膜晶体管的生成过程中需使用的掩膜板多达
9道， 严重降低了工业化生产的产能， 增加了成本。 发明内容
本发明所要解决的技术问题包括， 针对现有的低温多晶硅薄 膜晶体管存在的上述的问题， 提供一种结构简单且制备容易的低 温多晶硅薄膜晶体管及其制备方法、 阵列基板及其制备方法和显 示装置。
解决本发明技术问题所釆用的技术方案是提供一种低温多晶 硅薄膜晶体管， 其包括： 设置在基底上的有源层， 以及分别与有 源层连接的源极和漏极， 所述有源层包括源极接触区、 漏极接触 区， 以及设于源极接触区和漏极接触区之间的半导体区， 其中， 所述源极接触区和所述漏极接触区均能够导电， 且所述源极接触 区和所述漏极接触区均包括半导体基体和分布在所述半导体基体 内的离子， 所述源极直接覆盖所述源极接触区， 所述漏极直接覆 盖漏极接触区。
本发明的低温多晶硅薄膜晶体管的源极直接覆盖有源层的源 极接触区、 漏极直接覆盖有源层的漏极接触区， 与现有的低温多 晶硅薄膜晶体管相比较， 无需刻蚀接触过孔以使得薄膜晶体管的 源极和漏极分别与有源层连接， 进而可以节约制造成本、 提高生 产效率， 同时使得薄膜晶体管的结构更加简单。
优选的是， 所述低温多晶硅薄膜晶体管还包括： 设置在基底 与有源层之间的緩冲层。
优选的是， 所述低温多晶硅薄膜晶体管还包括： 栅极绝缘层 和栅极， 所述栅极通过所述栅极绝缘层与所述源极、 漏极和有源 层绝缘设置。
解决本发明技术问题所釆用的技术方案是提供一种低温多晶 硅薄膜晶体管的制备方法， 其包括：
1 ) 在基底上形成多晶硅半导体薄膜；
2 )在完成步骤 1 ) 的基底上， 通过构图工艺形成包括有源层 的图形， 该有源层包括源极接触区、 漏极接触区， 以及设于源极 接触区和漏极接触区之间的半导体区， 所述源极接触区和所述漏 极接触区均能够导电， 且所述源极接触区和所述漏极接触区均包 括半导体基体和分布在所述半导体基体内的离子；
3 )在完成步骤 2 ) 的基底上， 形成包括薄膜晶体管源极和漏 极的图形， 其中， 所述源极直接覆盖所述源极接触区， 所述漏极 直接覆盖漏极接触区。
本发明的制备方法缩短了工艺时间， 提高了生产效率， 进而 节约了生产成本。
优选的是， 所述步骤 2 ) 具体包括：
21 ) 在形成有所述多晶硅半导体薄膜的基底上， 涂覆第一厚 度的光刻胶， 并对涂覆有第一厚度的光刻胶的基底进行曝光、 显 影， 形成包括半导体基体的图形， 同时使半导体基体的中间区域 对应第一厚度的光刻胶， 使半导体基体的两侧区域分别对应第二 厚度的光刻胶， 且第一厚度的光刻胶比第二厚度的光刻胶厚；
22 )对完成步骤 21 ) 的基底进行灰化， 去除半导体基体的两 侧区域分别对应的第二厚度的光刻胶， 并使半导体基体的中间区 域对应的第一厚度的光刻胶变成第三厚度的光刻胶， 且第三厚度 的光刻胶的厚度等于第一厚度的光刻胶与第二厚度的光刻胶的厚 度差；
23 )对完成步骤 22 ) 的基底进行离子注入， 使得半导体基体 的未覆盖有第三厚度的光刻胶的区域变为导体区， 从而形成包括 有源层的图形， 且半导体基体的未覆盖有第三厚度的光刻胶的区 域即所述源极接触区和漏极接触区， 半导体基体的覆盖有第三厚 度的光刻胶的区域即所述设于源极接触区和漏极接触区之间的半 导体区。
优选的是， 所述步骤 3 ) 具体包括：
在形成有有源层的基底上涂覆源漏金属薄膜， 通过离地剥离 工艺去除有源层的半导体区上方的第三厚度的光刻胶， 以及该第 三厚度的光刻胶上方的源漏金属薄膜， 形成包括薄膜晶体管源极 和漏极的图形。
优选的是， 所述步骤 1 )之前还包括：
在基底上形成緩冲层。
优选的是， 所述步骤 3 )之后还包括：
4 ) 在完成步骤 3 ) 的基底上形成栅极绝缘层；
5 )在完成步骤 4 ) 的基底上， 通过构图工艺形成包括薄膜晶 体管栅极的图形。
优选的是， 所述步骤 1 ) 具体包括：
11 ) 在基底上形成非晶硅半导体薄膜；
12 ) 通过退火工艺， 对非晶硅半导体薄膜进行去氢处理；
13 ) 通过准分子激光退火工艺， 使去氢后的非晶硅半导体薄 膜再结晶， 从而形成多晶硅半导体薄膜。
解决本发明技术问题所釆用的技术方案是提供一种阵列基 板， 其包括上述薄膜晶体管。
由于本发明的阵列基板包括上述薄膜晶体管，故其结构简单。 优选的是， 所述阵列基板还包括存储电容， 所述存储电容包 括第一电极和第二电极。
进一步优选的是， 所述存储电容的第一电极与所述低温多晶 硅薄膜晶体管的有源层中的源极接触区和漏极接触区同层且同材 质， 所述存储电容的第二电极与所述低温多晶硅薄膜晶体管的栅 极同层且同材质， 或者， 所述存储电容的第一电极与所述低温多 晶硅薄膜晶体管的源极和漏极同层且同材质。
解决本发明技术问题所釆用的技术方案是提供一种阵列基板 的制备方法， 该阵列基板包括低温多晶硅薄膜晶体管， 所述阵列 基板的制备方法包括形成低温多晶硅薄膜晶体管的步骤， 且该低 温多晶硅薄膜晶体管是通过上述方法制备的。
优选的是，所述阵列基板的制备方法还包括存储电容的制备， 所述存储电容的第一电极与所述低温多晶硅薄膜晶体管的有源层 中的源极接触区和漏极接触区同步形成， 所述存储电容的第二电 极与所述低温多晶硅薄膜晶体管的栅极同步形成。
解决本发明技术问题所釆用的技术方案是提供一种显示装 置， 其包括上述阵列基板。
由于本发明的显示装置包括上述阵列基板， 故其结构简单， 且成本相对较低。 附图说明
图 1为现有的一种阵列基板的结构示意图；
图 2为本发明的实施例 1的低温多晶硅薄膜晶体管的结构示 意图；
图 3A至图 3F为本发明的实施例 2的低温多晶硅薄膜晶体管 的制作过程的示意图；
图 4A至图 4E为图 3B所示结构的制作过程的示意图； 以及， 图 5本发明的实施例 3的阵列基板的结构示意图。 其中附图标记为： 101、 基底； 102、 緩冲层； 103、 有源层； 1031、 多晶硅半导体薄膜； 103A、 半导体基体； 104、栅极绝缘层； 105、 栅极； 106、 平坦化层； 107、 源漏金属薄膜； 1071、 源极； 1072、 漏极； 108、 存储电容的第一电极； 109、 存储电容的第二 电极； 110、 第一厚度的光刻胶； 111、 第二厚度的光刻胶； 112、 第三厚度的光刻胶； 113、 钝化层； 114、 像素电极。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明作进一步详细描述。 实施例 1 :
如图 2所示， 本实施例提供一种低温多晶硅薄膜晶体管， 其 包括： 设置在基底 101 上的有源层 103， 以及分别与有源层 103 连接的源极 1071和漏极 1072， 所述有源层 103包括源极接触区、 漏极接触区， 以及设于源极接触区和漏极接触区之间的半导体区， 所述源极 1071直接覆盖所述源极接触区， 所述漏极 1072直接覆 盖漏极接触区， 其中， 所述源极接触区和所述漏极接触区均能够 导电， 且所述源极接触区和所述漏极接触区均包括半导体基体和 分布在所述半导体基体内的离子。
本实施例所提供的低温多晶硅薄膜晶体管的源极 1071 直接 覆盖有源层 103的源极接触区、 漏极 1072直接覆盖有源层 103的 漏极接触区， 与现有的低温多晶硅薄膜晶体管相比较， 无需刻蚀 接触过孔以使得薄膜晶体管的源极 1071和漏极 1072分别与有源 层 103连接， 进而可以节约制造成本、 提高生产效率， 同时使得 薄膜晶体管的结构更加简单。
本领域技术人员容易理解的是， 由于本实施例提供的是低温 多晶硅薄膜晶体管， 因此有源层 103的半导体区， 以及有源层 103 的源极接触区和漏极接触区的半导体基体均釆用低温多晶硅材料 制成。 在本发明中， 对分布在源极接触区的半导体基体中的离子 以及分布在漏极接触区的半导体基体中的离子并没有特殊规定， 只要可以使源极接触区和漏极接触区导电即可。 例如， 所述离子 可以为硼离子。
本实施例的低温多晶硅薄膜晶体管， 优选地， 在基底 101与 有源层 103之间还设置有緩冲层 102，所述緩冲层 102—般由绝缘 物质组成。 由于在制备低温多晶硅薄膜晶体管的有源层 103 时， 需要利用激光退火使非晶硅半导体转变为多晶硅半导体， 较高的 激光退火温度会对设置在有源层 103之下的基底 101(例如玻璃基 底）产生影响， 所以在基底 101与有源层 103之间设置緩冲层 102 是很有必要的。
当然， 上述薄膜晶体管还包括栅极绝缘层 104以及栅极 105， 所述栅极绝缘层 104将栅极 105与所述源极 1071、漏极 1072和有 源层 103隔开，从而使栅极 105与源极 1071、 漏极 1072和有源层 103绝缘设置。 实施例 2:
结合图 3A-3F、 4A-4E 所示， 本实施例提供一种低温多晶硅 薄膜晶体管的制备方法， 其具体包括如下步骤：
步骤一、 在基底 101 上通过等离子体增强化学气相沉积法 ( PECVD; Plasma Enhanced Chemical Vapor Deposition ) 等工艺 形成一层緩冲层 102， 如图 3A所示。
其中， 緩冲层 102的材料可以为硅的氧化物 （SiOx ) 、 硅的 氮化物 （SiNx ) 、 铪的氧化物 （HfOx ) 、 硅的氮氧化物 （SiON ) 和铝的氧化物 （AlOx ) 中的任意一种材料形成的单层膜， 或它们 中的任意两种材料形成的多层复合膜， 对应的反应气体可以为 SiH4、 匪3和 N2的混合气体， 或 SiH2Cl2、 匪3和 N2的混合气体， 所述緩冲层 102的厚度在 2000 A -3000 A之间，本领域技术人员可 根据实际情况具体设定緩冲层 102的厚度。
步骤二、 在完成步骤一的基底 101上， 通过构图工艺形成包 括有源层 103的图形， 如图 3B所示， 该有源层 103包括源极接触 区、 漏极接触区， 以及设于源极接触区和漏极接触区之间的半导 体区， 所述源极接触区和所述漏极接触区均能够导电， 且所述源 极接触区和所述漏极接触区均包括半导体基体和分布在所述半导 体基体内的离子。
如图 4A-4E所示， 步骤二的具体步骤包括：
Sl、 在完成步骤一的基底 101上形成非晶硅（ a-Si )半导体薄 膜； 通过退火工艺， 对非晶硅半导体薄膜进行去氢处理； 通过准 分子激光退火工艺， 使去氢后的非晶硅半导体薄膜再结晶， 从而 形成多晶硅半导体薄膜 1031， 如图 4A所示。 非晶硅半导体薄膜 的厚度可以在 300 A - 1000 A之间， 对应的反应气体可以是 SiH4和 H2的混合气体， 或者 SiH2Cl2和 H2的混合气体。 52、 在形成有所述多晶硅半导体薄膜 1031的基底 101上（即 完成步骤 S2的基底 101上） ， 涂覆第一厚度的光刻胶 110， 如图 4B所示， 并通过灰度掩膜板或者半色调掩膜板对涂覆有第一厚度 的光刻胶 110的基底 101进行曝光、 显影， 形成包括半导体基体 103 A的图形， 同时使半导体基体 103A的中间区域对应第一厚度 的光刻胶 110， 使半导体基体 103A的两侧区域分别对应第二厚度 的光刻胶 111， 且第一厚度的光刻胶 110比第二厚度的光刻胶 111 厚， 如图 4C所示； 其中， 通过灰度掩膜板或者半色调掩膜板曝光 工艺为现有的工艺手段， 在此不详细描述。
53、 对完成步骤 S2 的基底 101 进行灰化， 去除半导体基体 103A的两侧区域分别对应的第二厚度的光刻胶 111， 并使半导体 基体 103A的中间区域对应的第一厚度的光刻胶 110变成第三厚度 的光刻胶 112，且第三厚度的光刻胶 112的厚度等于第一厚度的光 刻胶 110与第二厚度的光刻胶 111的厚度差， 如图 4D所示；
54、对完成步骤 S3的基底 101进行离子注入，使得半导体基 体 103A的两侧区域， 即半导体基体 103A的未覆盖有第三厚度的 光刻胶 111的区域变为导体区， 从而形成包括有源层 103的图形， 如图 4E所示， 有源层 103包括源极接触区、 漏极接触区， 以及设 于源极接触区和漏极接触区之间的半导体区， 且半导体基体 103A 的未覆盖有第三厚度的光刻胶 111 的区域即所述源极接触区和漏 极接触区，半导体基体 103A的覆盖有第三厚度的光刻胶 111的区 域即所述设于源极接触区和漏极接触区之间的半导体区； 其中， 进行离子注入工艺， 注入的离子为棚离子， 反应气体为浓度为 10%B2H6o
步骤三、 在完成步骤二的基底 101上， 釆用磁控溅射的方法 沉积一层源漏金属薄膜 107， 如图 3C所示， 形成包括薄膜晶体管 源极 1071和漏极 1072的图形， 如图 3D所示， 其中， 所述源极 1071直接覆盖所述源极接触区，所述漏极 1072直接覆盖漏极接触 区。 需要说明的是， 釆用离地剥离 （lift off ) 工艺可以将有源层 103 的半导体区上方的第三厚度的光刻胶 112 与以及该第三厚度 的光刻胶 112上方的源漏金属薄膜 107 —同剥离去除， 最终形成 包括薄膜晶体管源极 1071和漏极 1072的图形。
其中， 源极 1071和漏极 1072的材料可以是钼 （ Mo ) 、 钼铌 H ( MoNb ) 、 4吕（ A1 ) 、 4吕 ( AlNd ) 、 4太（ Ti )和 4同 ( Cu ) 中的任意一种材料形成的单层膜， 或有其中的任意两种或两种以 上材料形成的单层膜或多层复合膜， 源极 1071和漏极 1072的材 料优选为 Mo、 A1和含 Mo、 A1的合金中的任意一种材料形成的单 层膜， 或其中的任意两种或两种以上材料形成的多层复合膜， 源 极 1071和漏极 1072的厚度均在 1500 A -4000 A之间，本领域技术 人员可根据具体情况具体设定源极 1071和漏极 1072的厚度。
步骤四、 在完成步骤三的基底 101上， 釆用热生长、 常压化 学气相沉积、 低压化学气相沉积、 等离子辅助体化学气相淀积或 溅射等制备方法， 形成栅极绝缘层 104， 如图 3E所示。
其中，所述栅极绝缘层 104的材料可以为硅的氧化物（SiOx )、 硅的氮化物（ SiNx )、铪的氧化物（ HfOx )、硅的氮氧化物（ SiON ) 和铝的氧化物 （AlOx ) 中的任意一种材料形成的单层膜， 或其中 的任意两种或两种以上材料形成的多层复合膜， 其厚度在 1000 A -4000 A之间， 本领域技术人员可根据具体情况具体设定栅极绝缘 层 104的厚度。
步骤五、 在完成步骤四的基底 101上， 釆用磁控溅射的方法 沉积一层栅极金属层薄膜， 并通过构图工艺形成包括薄膜晶体管 栅极 105的图形， 如图 3F所示。
其中， 所述栅极 105 的材料可以为钼 （Mo ) 、 钼铌合金 ( MoNb ) 、 铝 （ A1 ) 、 铝钕合金 ( AlNd ) 、 钛（ Ti ) 和铜 ( Cu ) 中的任意一种材料形成的单层膜， 或其中的任意两种或两种以上 材料形成的单层膜或多层复合膜， 栅极 105 的材料优选为 Mo、 A1和含 Mo、 A1的合金中的任意一种材料形成的单层膜， 或其中 的任意两种或两种以上材料形成的多层复合膜。
本实施例所提供的低温多晶硅薄膜晶体管的制备方法， 工艺 简单， 容易实现， 特别是在步骤二的 S2中釆用灰度掩膜板或者半 色调掩膜板对第一厚度的光刻胶 110进行曝光、 显影， 减少了工 艺中使用的掩膜板的数量， 缩短了工艺时间， 提高了生产效率。 需要说明的是， 实施例 1 中的低温多晶硅薄膜晶体管可以釆用本 实施例的制备方法制备。 实施例 3:
如图 5所示， 本实施例提供了一种阵列基板， 其包括实施例 1中所述的低温多晶硅薄膜晶体管， 和存储电容， 其中， 所述存储 电容的第一电极 108 与所述低温多晶硅薄膜晶体管的有源层 103 中的源极接触区和漏极接触区同层且同材质， 所述存储电容的第 二电极 109与所述低温多晶硅薄膜晶体管的栅极 105 同层且同材 质。 当然， 存储电容的第一电极 108也可以与所述低温多晶硅薄 膜晶体管的源极 1071和漏极 1072同层且同材质。 具体形成方法 与现有的方法相同， 在此不详细描述。
当然本实施例的阵列基板还包括设置在所述低温多晶硅薄膜 晶体管的栅极 105上方的钝化层 113，以及设置在钝化层 113上方 的像素电极 114,所述像素电极 114通过贯穿钝化层 113以及栅极 绝缘层 104 的接触过孔与低温多晶硅薄膜晶体管的漏极 1072连 接。
由于本实施例的阵列基板包括实施例 1所述的低温多晶硅薄 膜晶体管， 故其结构简单， 制备方法简便。 实施例 4:
本实施例提供了一种阵列基板的制备方法， 该阵列基板包括 低温多晶硅薄膜晶体管，该低温多晶硅薄膜晶体管是通过实施例 2 所述的制备方法制备的， 在此不重复赘述了。
当然该阵列基板的制备方法还包括存储电容的制备， 所述存 储电容的第一电极 108 与所述低温多晶硅薄膜晶体管的有源层 103中的源极接触区和漏极接触区同步形成，所述存储电容的第二 电极 109与所述低温多晶硅薄膜晶体管的栅极 105 同步形成。 当 然， 存储电容的第一电极 108 也可以与所述低温多晶硅薄膜晶体 管的源极 1071和漏极 1072同步形成。 上述形成方法为本领域技 术人员所公知， 在此不详细描述。 实施例 5:
本实施例提供一种显示装置，其包括实施例 3中的阵列基板， 该显示装置可以为： 手机、 平板电脑、 电视机、 显示器、 笔记本 电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例 3 中的阵列基板， 故其成 本低。
当然， 本实施例的显示装置中还可以包括其他常规结构， 如 电源单元、 显示驱动单元等。
而釆用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

权 利 要 求 书
1. 一种低温多晶硅薄膜晶体管， 包括： 设置在基底上的有源 层， 以及分别与有源层连接的源极和漏极， 所述有源层包括源极 接触区、 漏极接触区， 以及设于源极接触区和漏极接触区之间的 半导体区， 其特征在于， 所述源极接触区和所述漏极接触区均能 够导电， 且所述源极接触区和所述漏极接触区均包括半导体基体 和分布在所述半导体基体内的离子， 所述源极直接覆盖所述源极 接触区， 所述漏极直接覆盖漏极接触区。
2. 根据权利要求 1所述的低温多晶硅薄膜晶体管， 其特征在 于， 所述低温多晶硅薄膜晶体管还包括： 设置在基底与有源层之 间的緩冲层。
3. 根据权利要求 1或 2所述的低温多晶硅薄膜晶体管， 其特 征在于， 所述低温多晶硅薄膜晶体管还包括： 栅极绝缘层和栅极， 所述栅极通过所述栅极绝缘层与所述源极、 漏极和有源层绝缘设 置。
4. 一种低温多晶硅薄膜晶体管的制备方法， 其特征在于， 包 括如下步骤：
1 ) 在基底上形成多晶硅半导体薄膜；
2 )在完成步骤 1 ) 的基底上， 通过构图工艺形成包括有源层 的图形， 该有源层包括源极接触区、 漏极接触区， 以及设于源极 接触区和漏极接触区之间的半导体区， 所述源极接触区和所述漏 极接触区均能够导电， 且所述源极接触区和所述漏极接触区均包 括半导体基体和分布在所述半导体基体内的离子；
3 )在完成步骤 2 ) 的基底上， 形成包括薄膜晶体管源极和漏 极的图形， 其中， 所述源极直接覆盖所述源极接触区， 所述漏极 直接覆盖漏极接触区。
5. 根据权利要求 4所述的制备方法， 其特征在于， 所述步骤 2 ) 具体包括：
21 ) 在形成有所述多晶硅半导体薄膜的基底上， 涂覆第一厚 度的光刻胶， 并对涂覆有第一厚度的光刻胶的基底进行曝光、 显 影， 形成包括半导体基体的图形， 同时使半导体基体的中间区域 对应第一厚度的光刻胶， 使半导体基体的两侧区域分别对应第二 厚度的光刻胶， 且第一厚度的光刻胶比第二厚度的光刻胶厚；
22 )对完成步骤 21 ) 的基底进行灰化， 去除半导体基体的两 侧区域分别对应的第二厚度的光刻胶， 并使半导体基体的中间区 域对应的第一厚度的光刻胶变成第三厚度的光刻胶， 且第三厚度 的光刻胶的厚度等于第一厚度的光刻胶与第二厚度的光刻胶的厚 度差；
23 )对完成步骤 22 ) 的基底进行离子注入， 使得半导体基体 的未覆盖有第三厚度的光刻胶的区域变为导体区， 从而形成包括 有源层的图形， 且半导体基体的未覆盖有第三厚度的光刻胶的区 域即所述源极接触区和漏极接触区， 半导体基体的覆盖有第三厚 度的光刻胶的区域即所述设于源极接触区和漏极接触区之间的半 导体区。
6. 根据权利要求 5 所述的低温多晶硅薄膜晶体管的制备方 法， 其特征在于， 所述步骤 3 ) 具体包括：
在形成有有源层的基底上涂覆源漏金属薄膜， 通过离地剥离 工艺去除有源层的半导体区上方的第三厚度的光刻胶， 以及该第 三厚度的光刻胶上方的源漏金属薄膜， 形成包括薄膜晶体管源极 和漏极的图形。
7. 根据权利要求 4 所述的低温多晶硅薄膜晶体管的制备方 法， 其特征在于， 所述步骤 1 )之前还包括：
在基底上形成緩冲层。
8. 根据权利要求 4 所述的低温多晶硅薄膜晶体管的制备方 法， 其特征在于， 所述步骤 3 )之后还包括：
4 ) 在完成步骤 3 ) 的基底上形成栅极绝缘层；
5 )在完成步骤 4 ) 的基底上， 通过构图工艺形成包括薄膜晶 体管栅极的图形。
9. 根据权利要求 4~8中任意一项所述的低温多晶硅薄膜晶体 管的制备方法， 其特征在于， 所述步骤 1 ) 具体包括：
11 )在基底上形成非晶硅半导体薄膜；
12 )通过退火工艺， 对非晶硅半导体薄膜进行去氢处理；
13 ) 通过准分子激光退火工艺， 使去氢后的非晶硅半导体薄 膜再结晶， 从而形成多晶硅半导体薄膜。
10. 一种阵列基板， 其特征在于， 所述阵列基板包括权利要 求 1~3中任意一项所述的低温多晶硅薄膜晶体管。
11. 根据权利要求 10所述的阵列基板， 其特征在于， 所述阵 列基板还包括存储电容， 所述存储电容包括第一电极和第二电极。
12. 根据权利要求 11所述的阵列基板， 其特征在于， 所述存 储电容的第一电极与所述低温多晶硅薄膜晶体管的有源层中的源 极接触区和漏极接触区同层且同材质， 所述存储电容的第二电极 与所述低温多晶硅薄膜晶体管的栅极同层且同材质， 或者， 所述 存储电容的第一电极与所述低温多晶硅薄膜晶体管的源极和漏极 同层且同材质。
13. 一种阵列基板的制备方法， 其特征在于， 所述阵列基板 包括低温多晶硅薄膜晶体管， 所述阵列基板的制备方法包括形成 低温多晶硅薄膜晶体管的步骤， 且该低温多晶硅薄膜晶体管是通 过权利要求 4~9中任意一种方法制备的。
14. 根据权利要求 13所述的阵列基板的制备方法， 其特征在 于， 所述阵列基板的制备方法包括存储电容的制备， 所述存储电 容的第一电极与所述低温多晶硅薄膜晶体管的有源层中的源极接 触区和漏极接触区同步形成， 所述存储电容的第二电极与所述低 温多晶硅薄膜晶体管的栅极同步形成。
15. 一种显示装置， 其特征在于， 包括权利要求 10~12 中任 意一项所述的阵列基板。
PCT/CN2014/079743 2013-12-16 2014-06-12 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置 WO2015090016A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/422,213 US9391207B2 (en) 2013-12-16 2014-06-12 Thin film transistor, array substrate and manufacturing method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310687276.7A CN103700706B (zh) 2013-12-16 2013-12-16 薄膜晶体管制备方法和阵列基板制备方法
CN201310687276.7 2013-12-16

Publications (1)

Publication Number Publication Date
WO2015090016A1 true WO2015090016A1 (zh) 2015-06-25

Family

ID=50362178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/079743 WO2015090016A1 (zh) 2013-12-16 2014-06-12 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置

Country Status (3)

Country Link
US (1) US9391207B2 (zh)
CN (1) CN103700706B (zh)
WO (1) WO2015090016A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700706B (zh) * 2013-12-16 2015-02-18 京东方科技集团股份有限公司 薄膜晶体管制备方法和阵列基板制备方法
TW201622158A (zh) * 2014-12-10 2016-06-16 中華映管股份有限公司 薄膜電晶體以及其製作方法
CN104600080B (zh) * 2014-12-30 2018-10-19 深圳市华星光电技术有限公司 阵列基板、显示面板及阵列基板的制备方法
CN105140238A (zh) * 2015-08-05 2015-12-09 深圳市华星光电技术有限公司 阵列基板及其制作方法
CN105428313A (zh) 2016-01-05 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN105870197A (zh) * 2016-04-21 2016-08-17 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板、显示装置
CN105679775B (zh) * 2016-04-21 2019-04-23 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板和显示装置
CN107168589B (zh) 2017-07-20 2020-09-18 上海天马微电子有限公司 一种显示基板及其制作方法、显示面板和显示装置
CN107393830A (zh) * 2017-07-21 2017-11-24 京东方科技集团股份有限公司 薄膜晶体管的制备方法
CN109427843A (zh) * 2017-08-22 2019-03-05 上海和辉光电有限公司 一种显示面板及其制备方法、显示装置
CN108321186A (zh) * 2018-02-11 2018-07-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板与显示装置
CN108288455A (zh) * 2018-03-05 2018-07-17 昆山国显光电有限公司 有机发光显示面板和显示装置
CN108565247B (zh) * 2018-04-19 2020-09-29 武汉华星光电技术有限公司 Ltps tft基板的制作方法及ltps tft基板
US10957713B2 (en) * 2018-04-19 2021-03-23 Wuhan China Star Optoelectronics Technology Co., Ltd. LTPS TFT substrate and manufacturing method thereof
KR20200050266A (ko) * 2018-11-01 2020-05-11 엘지디스플레이 주식회사 패널, 전자장치 및 트랜지스터
CN109638174B (zh) * 2018-11-13 2021-02-26 武汉华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN110600381A (zh) * 2019-08-26 2019-12-20 深圳市华星光电半导体显示技术有限公司 阵列基板和阵列基板的制备方法
CN111628005A (zh) * 2020-06-08 2020-09-04 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060214564A1 (en) * 2005-03-24 2006-09-28 Hsi-Ming Chang Organic electroluminescent display and method for fabricating the same
CN101740524A (zh) * 2008-11-21 2010-06-16 统宝光电股份有限公司 薄膜晶体管阵列基板的制造方法
CN102054874A (zh) * 2010-11-01 2011-05-11 友达光电股份有限公司 薄膜晶体管及其制造方法
CN103700706A (zh) * 2013-12-16 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040021758A (ko) * 2002-09-04 2004-03-11 엘지.필립스 엘시디 주식회사 다결정 실리콘 박막트랜지스터 제조방법
KR100652216B1 (ko) * 2003-06-27 2006-11-30 엘지.필립스 엘시디 주식회사 폴리실리콘 액정표시소자 제조 방법
CN100530605C (zh) * 2007-07-09 2009-08-19 友达光电股份有限公司 画素结构及其制作方法
CN100521165C (zh) * 2007-10-16 2009-07-29 友达光电股份有限公司 一种薄膜晶体管及其形成方法
JP2009212504A (ja) * 2008-02-08 2009-09-17 Advanced Lcd Technologies Development Center Co Ltd 薄膜半導体装置およびその製造方法
CN101582381B (zh) * 2008-05-14 2011-01-26 鸿富锦精密工业（深圳）有限公司 薄膜晶体管及其阵列的制备方法
KR101049805B1 (ko) * 2008-12-30 2011-07-15 삼성모바일디스플레이주식회사 다결정 실리콘의 제조방법, 박막트랜지스터, 그의 제조방법및 이를 포함하는 유기전계발광표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060214564A1 (en) * 2005-03-24 2006-09-28 Hsi-Ming Chang Organic electroluminescent display and method for fabricating the same
CN101740524A (zh) * 2008-11-21 2010-06-16 统宝光电股份有限公司 薄膜晶体管阵列基板的制造方法
CN102054874A (zh) * 2010-11-01 2011-05-11 友达光电股份有限公司 薄膜晶体管及其制造方法
CN103700706A (zh) * 2013-12-16 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置

Also Published As

Publication number Publication date
US20160043212A1 (en) 2016-02-11
CN103700706A (zh) 2014-04-02
US9391207B2 (en) 2016-07-12
CN103700706B (zh) 2015-02-18

Similar Documents

Publication Publication Date Title
WO2015090016A1 (zh) 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置
WO2019000493A1 (zh) 薄膜晶体管阵列基板及其制备方法、oled显示装置
JP6416128B2 (ja) 薄膜トランジスターの製作方法
WO2017092142A1 (zh) 低温多晶硅tft基板的制作方法
CN106558593A (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
WO2018188146A1 (zh) 一种阵列基板、显示装置及其制作方法
WO2017173712A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
WO2015180269A1 (zh) 一种阵列基板、其制作方法及显示装置
US9748398B2 (en) Thin film transistor and manufacturing method thereof, display device
JP4095074B2 (ja) 半導体素子製造方法
CN107170759B (zh) 一种阵列基板及其制作方法、显示装置
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
WO2017140036A1 (zh) 低温多晶硅薄膜晶体管及其制造方法
US20190006448A1 (en) Thin film transistor array substrate and preparing method therefor, and oled display device
WO2020177080A1 (en) Method of forming crystallized semiconductor layer, method of fabricating thin film transistor, thin film transistor, and display apparatus
WO2013139128A1 (zh) 顶栅型n-tft、阵列基板及其制备方法和显示装置
WO2017092172A1 (zh) Tft基板的制作方法
WO2020103419A1 (zh) 有机电致发光显示面板及其制作方法、显示装置
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN105702586A (zh) 一种薄膜晶体管、阵列基板、其制作方法及显示装置
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置
WO2019071693A1 (zh) 低温多晶硅薄膜及晶体管的制造方法
WO2019071694A1 (zh) 低温多晶硅薄膜及晶体管的制造方法
WO2016165223A1 (zh) 一种多晶硅薄膜晶体管及其制作方法和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14422213

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14872977

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.11.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14872977

Country of ref document: EP

Kind code of ref document: A1