CN105428313A - 阵列基板及其制备方法、显示装置 - Google Patents
阵列基板及其制备方法、显示装置 Download PDFInfo
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
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- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
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- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 1
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- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 239000010931 gold Substances 0.000 description 1
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical group [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 description 1
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- GTLACDSXYULKMZ-UHFFFAOYSA-N pentafluoroethane Chemical compound FC(F)C(F)(F)F GTLACDSXYULKMZ-UHFFFAOYSA-N 0.000 description 1
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- 239000011787 zinc oxide Substances 0.000 description 1
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Abstract
本发明提供一种阵列基板及其制备方法、显示装置,属于显示技术领域,其可解决现有的阵列基板制备工艺复杂的问题。本发明的制备方法包括:在基底上方通过构图工艺形成包括源极和漏极的图形;形成第一绝缘层;通过构图工艺形成包括有源层的图形;形成第二绝缘层,并在位于源、漏极上方的第一绝缘层和第二绝缘层中层刻蚀形成第一过孔和第二过孔;在位于有源层的源极接触区和漏极接触区上方的第二绝缘层中刻蚀形成第三过孔和第四过孔;通过构图工艺形成包括第一连接线、第二连接线、像素电极的图形;第一连接线通过第一过孔和第三过孔将源极与有源层的源极接触区连接;第二连接线通过第二过孔和第四过孔将漏极与有源层的漏极接触区以及像素电极连接。
Description
技术领域
本发明属于显示技术领域,具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
随着显示技术的发展,人们对显示画质的需求日益增长,高画质、高分辨率的平板显示装置的需求越来越普遍,也越来越得到显示面板厂家的重视。
薄膜晶体管(ThinFilmTransistor,简称TFT)是平板显示面板的主要驱动器件,直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构,制备相应结构的薄膜晶体管的材料也具有多种,例如:非晶硅和多晶硅都是目前常用的薄膜晶体管制备材料。然而,非晶硅本身存在很多无法避免的缺点,比如:低迁移率、低稳定性等;与此相比,低温多晶硅(LowTemperaturePoly-Silicon,简称LTPS)具有较高的迁移率及稳定性,其迁移率可达非晶硅的几十甚至几百倍。因此,采用低温多晶硅材料形成薄膜晶体管的技术得到了迅速发展,由LTPS衍生的新一代液晶显示装置(LiquidCrystalDisplay:简称LCD)或有机电致发光显示装置(OrganicLight-EmittingDiode:简称OLED)成为重要的显示技术,尤其是OLED显示装置,由于OLED具有超薄、低功耗、同时自身发光等特点,备受用户的青睐。
图1为现有技术中LTPSTFT阵列基板的一种结构剖视图。其中,该阵列基板包括依次设置于基板1上方的缓冲层2、有源层3、第一绝缘层4′、栅极5、第二绝缘层6′、源极71、漏极72、第三绝缘层8′、平坦化层9和像素电极10。目前,该结构的阵列基板需要采用八张掩模板进行八次构图工艺才能制备完成,这八次构图工艺分别是:
利用有源层掩模板(a-SiMask),通过第一次构图工艺形成包括有源层3的图形;
利用存储电容掩模板(CSMask),将第一绝缘层4′通过第二次构图工艺进行部分p-Si掺杂以形成包括存储电容CS的第一极板11的图形。在该步骤中,即通过第一次离子注入掺杂形成存储电容CS的第一极板11,采用离子注入方法形成了第一极板11的存储电容,存在充放电速度较慢的缺点;
利用栅极掩模板(GateMask),通过第三次构图工艺形成包括栅极5及存储电容CS的第二极板12的图形。在该步骤中,即采用栅金属作为存储电容CS的第二极板;
利用接触孔掩模板(ContactMask),在第二绝缘层6′中,通过第四次构图工艺形成包括用于连接源极71、漏极72与有源层3的接触孔的图形;
利用源漏极掩模板(S/DMask),通过第五次构图工艺形成包括源极71、漏极72的图形;
利用过孔掩模板(VIAHoleMask),在第三绝缘层8′中,通过第六次构图工艺形成包括像素电极10与漏极72之间的桥接过孔的图形;
利用平坦层掩模板(PLNMask),在平坦层9中,通过第七次构图工艺形成包括像素电极10与漏极72之间的桥接过孔的图形,并使阵列基板平坦化,以便在平坦的基板上沉积电极层;
利用像素电极掩模板(ITOMask),通过第八次构图工艺形成像素电极10的图形。
可见,现有技术制作LTPSTFT和CS的阵列基板工艺复杂、流程较多,造成了较高的生产成本。
发明内容
本发明所要解决的技术问题包括,针对现有的阵列基板的制备方法存在的上述问题,提供一种工艺简单、成本较低的阵列基板及其制备方法、显示装置。
解决本发明技术问题所采用的技术方案是一种阵列基板的制备方法,包括如下步骤:
在基底上方,通过构图工艺形成包括薄膜晶体管源极和漏极的图形;
形成第一绝缘层;
通过构图工艺形成包括薄膜晶体管有源层的图形;
形成第二绝缘层,并在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中层刻蚀形成第一过孔和第二过孔;在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀形成第三过孔和第四过孔;
通过构图工艺形成包括第一连接线、第二连接线、像素电极的图形;其中,所述第一连接线通过所述第一过孔和所述第三过孔将所述源极与所述有源层的源极接触区连接;所述第二连接线通过所述第二过孔和所述第四过孔将所述漏极与所述有源层的漏极接触区,以及所述像素电极连接。
优选的是,所述形成第二绝缘层包括:
形成栅极绝缘层和形成平坦化层的步骤;所述制备方法还包括:
在形成所述栅极绝缘层和所述平坦化层之间,通过构图工艺形成包括薄膜晶体管的栅极的图形。
进一步优选的是,所述栅极与所述有源层的导电沟道区在所述基底上的正投影完全重合;所述通过构图工艺形成包括栅极的图形之后,还包括:
对所述有源层的源极接触区和漏极接触区进行离子注入。
更进一步优选的是,所述通过构图工艺形成包括薄膜晶体管有源层的图形的同时,还包括:
形成包括存储电容的第一极板的图形;
所述对所述有源层的源极接触区和漏极接触区进行离子注入的同时,还包括:
对所述存储电容的第一极板进行离子注入。
优选的是,所述通过构图工艺形成包括薄膜晶体管源极和漏极的图形的同时,还包括:
形成包括薄膜晶体管的栅极的图形。
优选的是,所述通过构图工艺形成包括薄膜晶体管源极和漏极的图形的同时,还包括:
形成包括存储电容的第二极板的图形。
优选的是,所述在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中层刻蚀形成第一过孔和第二过孔;在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀形成第三过孔和第四过孔,具体包括:
首先,在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中刻蚀第一过孔和第二过孔对应的区域;
之后,在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀第三过孔和第四过孔对应的区域。
进一步优选的是,刻蚀所述第二绝缘层,形成所述第三过孔和第四过孔所采用的刻蚀气体为CxFy。
优选的是,所述形成包括像素电极的图形之后,还包括:
通过一次构图工艺形成包括像素限定层和隔垫物的图形。
解决本发明技术问题所采用的技术方案是一种阵列基板,包括:
基底;
位于基底上方的薄膜晶体管的源极和漏极;
位于所述源极和漏极所在层上方第一绝缘层;
位于所述第一绝缘层上方的薄膜晶体管的有源层;
位于所述有源层所在层上方的第二绝缘层;
位于所述第二绝缘层所在层上方的第一连接线、第二连接线、像素电极;其中,
所述第一连接线通过贯穿位于所述源极上方的所述第一绝缘层和所述第二绝缘层的第一过孔,以及贯穿位于所述有源层的源极接触区上方的所述第二绝缘层的第三过孔,将所述源极与所述有源层的源极接触区连接;所述第二连接线通过贯穿位于所述漏极上方的所述第一绝缘层和所述第二绝缘层的第二过孔,以及贯穿位于所述有源层的漏极接触区上方的所述第二绝缘层的第四过孔,将所述漏极与所述有源层的漏极接触区和所述像素电极连接。
优选的是,所述第二绝缘层包括栅极绝缘层和形成平坦化层;所述阵列基板还包括位于所述栅极绝缘层和所述平坦化层之间的薄膜晶体管的栅极。
优选的是,所述栅极与所述有源层的导电沟道区在所述基底上的正投影完全重合;且在所述有源层的源极接触区和漏极接触区中掺杂有离子。
进一步优选的是,所述阵列基板还包括与所述有源层同层且材料相同的存储电容的第一极板,且在所述第一极板中掺杂有离子。
优选的是,所述阵列基板还包括与所述源极和所述漏极同层且材料相同的薄膜晶体管的栅极。
优选的是,所述阵列基板还包括与所述源极和所述漏极同层且材料相同的存储电容的第二极板。
解决本发明技术问题所采用的技术方案是一种显示装置,其包括上述的阵列基板。
本发明具有如下有益效果:
本发明的阵列基板的薄膜晶体管的漏极与有源层接触区连接的过孔和漏极与像素电极连接过孔采用一次刻蚀工艺完成,因此简化了工艺步骤;而且存储电容的两个极板中,其中一个极板采用与薄膜晶体管TFT的源极和漏极相同的金属材料形成,另一个极板采用与薄膜晶体管的有源层相同的材料形成,因此,减小了存储电容的两个极板之间的距离,避免了存储电容值过小的问题。
附图说明
图1为现有的阵列基板的结构示意图;
图2为本发明的实施例1的阵列基板的制备方法中的步骤一的示意图;
图3为本发明的实施例1的阵列基板的制备方法中的步骤二的示意图;
图4为本发明的实施例1的阵列基板的制备方法中的步骤三的示意图;
图5为本发明的实施例1的阵列基板的制备方法中的步骤四的示意图;
图6为本发明的实施例1的阵列基板的制备方法中的步骤五的示意图;
图7为本发明的实施例1的阵列基板的制备方法中的步骤六的示意图。
其中附图标记为:1、基底;2、缓冲层;3、有源层;4'、第一绝缘层;5、栅极;6、栅极绝缘层;6'、第二绝缘层;71、源极;72、漏极;8′、第三绝缘层;81、第一连接线;82、第二连接线;9、平坦化层;10、像素电极;11、第一极板;12、第二极板;13、树脂层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
在本发明中,构图工艺,可只包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
实施例1:
结合图2-7所示,本实施例提供一种阵列基板的制备方法,具体包括如下步骤:
步骤一、在基底1上依次沉积缓冲层2和源漏金属薄膜,并通过一次构图工艺形成包括薄膜晶体管的源极71、漏极72和存储电容的第二极板12(下极板)的图形,如图2所示。
在该步骤中,基底1采用玻璃等透明材料制成、且经过预先清洗。具体的,在基底1上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积(PlasmaEnhancedVaporDeposition:简称PECVD)方式、低压化学气相沉积(LowPressureChemicalVaporDeposition:简称LPCVD)方式、大气压化学气相沉积(AtmosphericPressureChemicalVaporDeposition:简称APCVD)方式或电子回旋谐振化学气相沉积(ElectronCyclotronResonanceChemicalVaporDeposition:简称ECR-CVD)方式形成源漏金属薄膜;然后,通过第一次构图工艺(成膜、曝光、显影、湿法刻蚀或干法刻蚀),同时形成包括源极71、漏极72和第二极板12的图形。
步骤二、在完成步骤一的基底1上,依次沉积第一绝缘层4′和非晶硅薄膜(a-Si),通过构图工艺形成包括薄膜晶体管的有源层3和存储电容的第一极板11(上极板)的图形,如图3所示。
在该步骤中,首先,沉积方式包括等离子体增强化学气相沉积方式、低压化学气相沉积方式;
之后,对非晶硅薄膜进行晶化,晶化方式包括采用准分子激光晶化方式、金属诱导晶化方式或固相晶化方式,将非晶硅膜30转变为多晶硅薄膜(p-Si),然后,对多晶硅薄膜(p-Si)进行掺杂(P型掺杂或者N型掺杂),以决定薄膜晶体管TFT的导电沟道区的导电类型。其中,准分子激光晶化方式、金属诱导晶化方式为两种低温多晶硅的方法,是较为常用的把非晶硅转变为多晶硅的方法。然而,本发明将非晶硅转变为多晶硅的方法,并不限制于采用低温多晶硅的方法,只要能够将有源层3转变为所需的多晶硅薄膜就可以。
步骤三、在完成步骤二的基底1上,依次沉积形成栅极绝缘层6(第二绝缘层的第一层结构)和栅金属薄膜,并通过构图工艺形成栅极5的图形,如图4所示。
在该步骤中,首先,采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式在有源层3和第一极板11的上方形成栅绝缘层;接着,采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成栅金属薄膜;最后,通过构图工艺形成包括薄膜晶体管栅极5的图形,其中栅极5与所述有源层3的导电沟道区在基底1上的正投影完全重合。
该步骤中,进一步的包括:采用离子注入法,将有源层3(p-Si)对应着源极接触区和漏极接触区进行掺杂,以增强有源层3与源极71和漏极72的欧姆接触,保证P-Si与源极71漏极72形成良好的欧姆接触;而有源层3在对应着栅极5的区域不需进行掺杂,因为,此次掺杂是在栅极5的图形刻蚀完成后进行的,因为有栅极5的阻挡作用,对与栅极5对应的区域的有源层3的部分P-Si无法进行掺杂;同时,因为这部分P-Si是作为沟道存在的,也无需进行掺杂。其中,离子注入方式包括具有质量分析仪的离子注入方式、不具有质量分析仪的离子云式注入方式、等离子注入方式或固态扩散式注入方式。即本实施例中,由低温多晶硅材料经晶化、掺杂、离子注入等多个步骤,最终形成具有良好半导体性质的有源层3。当然,在对源极接触区和漏极接触区进行掺杂的同时还对存储电容的第一极板11进行离子注入,以增强第一极板11的电学特性。
步骤四、在完成步骤三的基底1上,沉积平坦化层9(第二绝缘层的第二层结构),并在位于所述源极71和所述漏极72上方的所述第一绝缘层4′、栅极绝缘层6、平坦化层9中层刻蚀形成第一过孔和第二过孔;在位于所述有源层3的源极接触区和漏极接触区上方的栅极绝缘层6、平坦化层9中刻蚀形成第三过孔和第四过孔,如图5所示。
在该步骤中,首先,通过采用半色调掩模(HalfToneMask,简称HTM)或灰色调掩模(GrayToneMask,简称GTM),使得有源层3的源极接触区和漏极接触区为半透光区,曝光之后,该区域保留部分光刻胶;之后,在等离子刻蚀时,先刻蚀第一过孔和第二过孔对应的区域,随着阵列基板表面上的光刻胶的脱落,刻蚀第三过孔和第四过孔对应的区域。具体的,可以先刻蚀形成第一过孔和第二过孔;随着阵列基板表面上的光刻胶的脱落,最后刻蚀形成第三过孔和第四过孔。由于在第一过孔和第二过孔下方是对应的源极71和漏极72,因此在刻蚀时所采用的刻蚀气体为CxFy,该种刻蚀气体不会刻蚀金属,破坏源极71和漏极72的结构。需要说明的是,这里的CxFy气体是指含C(碳)以及F(氟)的化合物,如:CF4(四氟化碳)、C4F8(八氟环丁烷)、C2HF5(五氟乙烷)等。
步骤五、在完成步骤四的基底1上,通过构图工艺形成包括第一连接线81、第二连接线82、像素电极10的图形;其中,所述第一连接线81通过所述第一过孔和所述第三过孔将所述源极71与所述有源层3的源极接触区连接;所述第二连接线82通过所述第二过孔和所述第四过孔将所述漏极72与所述有源层3的漏极接触区,以及所述像素电极10连接,如图6所示。
在该步骤中,采用溅射方式、热蒸发方式或等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式沉积导电金属膜。其中,导电金属膜具有高反射率并且满足一定的金属功函数要求,常采用双层膜或三层膜结构:比如ITO(氧化铟锡)/Ag(银)/ITO(氧化铟锡)或者Ag(银)/ITO(氧化铟锡)结构;或者,把上述结构中的ITO换成IZO(氧化铟锌)、IGZO(氧化铟镓锌)或InGaSnO(氧化铟镓锡)。当然,也可以采用具有导电性能及高功函数值的无机金属氧化物、有机导电聚合物或金属材料形成,无机金属氧化物包括氧化铟锡或氧化锌,有机导电聚合物包括PEDOT:SS、PANI,金属材料包括金、铜、银或铂。
然后,采用一次构图工艺形成包括一连接线、第二连接线82、像素电极10的图形;其中,所述第一连接线81通过所述第一过孔和所述第三过孔将所述源极71与所述有源层3的源极接触区连接;所述第二连接线82通过所述第二过孔和所述第四过孔将所述漏极72与所述有源层3的漏极接触区,以及所述像素电极10连接。
步骤六、在完成步骤五的基底1上,通过一次构图工艺形成包括像素限定层(PixelDefineLayer,简称PDL)和隔垫物(PS)的图形。
在该步骤中,具体是采用半色调掩模(HalfToneMask,简称HTM)或灰色调掩模(GrayToneMask,简称GTM),对所涂覆的树脂层13(PI)材料,如图7所示,在一次构图工艺中形成像素限定层和隔垫物的图形。
在上述阵列基板的结构基础上,进一步的蒸镀或者涂覆发光层(EmittingLayer:简称EL),最后溅射或蒸镀形成金属阴极层,经封装即可形成带有OLED器件的阵列基板。
在本实施例中,薄膜晶体管的漏极72与有源层3接触区连接的过孔和漏极72与像素电极10连接过孔采用一次刻蚀工艺完成,因此简化了工艺步骤;而且存储电容的两个极板中,其中一个极板采用与薄膜晶体管TFT的源极71和漏极72相同的金属材料形成,另一个极板采用与薄膜晶体管的有源层3相同的材料形成,因此,减小了存储电容的两个极板之间的距离,避免了存储电容值过小的问题。
在此需要说明的是,本实施例中的薄膜晶体管的栅极5也可以与源、漏电极同层设置,采用一次构图工艺制备,此时,栅极5位于有源层3下方,也就是顶栅型薄膜晶体管,阵列基板上的其他步骤均与上述步骤相同,因此不再详细描述。
实施例2:
本实施例提供一种阵列基板,该阵列基板可以采用实施例1中的制备方法制备,该阵列基板适用于OLED显示装置。
该阵列基板包括基底1,位于基底1上的薄膜晶体管、存储电容、OLED器件。
该阵列基板具体包括:基底1;位于基底1上方的薄膜晶体管的源极71和漏极72;位于所述源极71和漏极72所在层上方第一绝缘层4′;位于所述第一绝缘层4′上方的薄膜晶体管的有源层3;位于所述有源层3所在层上方的第二绝缘层;位于所述第二绝缘层所在层上方的第一连接线81、第二连接线82、像素电极10;其中,所述第一连接线81通过贯穿位于所述源极71上方的所述第一绝缘层4′和所述第二绝缘层的第一过孔,以及贯穿位于所述有源层3的源极接触区上方的所述第二绝缘层的第三过孔,将所述源极71与所述有源层3的源极接触区连接;所述第二连接线82通过贯穿位于所述漏极72上方的所述第一绝缘层4′和所述第二绝缘层的第二过孔,以及贯穿位于所述有源层3的漏极接触区上方的所述第二绝缘层的第四过孔,将所述漏极72与所述有源层3的漏极接触区和所述像素电极10连接。
其中,所述第二绝缘层包括栅极绝缘层6和形成平坦化层9;所述阵列基板还包括位于所述栅极绝缘层6和所述平坦化层9之间的薄膜晶体管的栅极5。进一步的,所述栅极5与所述有源层3的导电沟道区在所述基底1上的正投影完全重合;且在所述有源层3的源极接触区和漏极接触区中掺杂有离子。也就是说,在对有源层3的源极接触区和漏极接触区进行离子掺杂时,栅极5作为掩模板,因此可以省一张掩模板,从而降低工艺成本。
其中,存储电容的第一极板11与所述有源层3同层且材料相同,且在所述第一极板11中掺杂有离子;第二极板12与源极71和所述漏极72同层且材料相同;故减小了存储电容的两个极板之间的距离,避免了存储电容值过小的问题;而且,储电容的第一极板11与所述有源层3同层且材料相同,且在所述第一极板11中掺杂有离子;第二极板12与源极71和所述漏极72同层且材料相同,故第一极板11可以与有源层3同步形成,第二极板12可以与源极71和漏极72同步形成,因此可以降低生产成本。
在此需要说明的是,本实施例中的薄膜晶体管的栅极5也可以与源、漏电极同层设置,采用一次构图工艺制备,此时,栅极5位于有源层3下方,也就是顶栅型薄膜晶体管,阵列基板上的其他步骤均与上述步骤相同,因此不再详细描述。
实施例3:
本实施例提供一种显示装置,包括实施例1中的阵列基板。
其中,显示装置可以为液晶显示装置或者电致发光显示装置,例如液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例中的显示装置具有较好的显示质量。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (16)
1.一种阵列基板的制备方法,其特征在于,包括如下步骤:
在基底上方,通过构图工艺形成包括薄膜晶体管源极和漏极的图形;
形成第一绝缘层;
通过构图工艺形成包括薄膜晶体管有源层的图形;
形成第二绝缘层,并在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中层刻蚀形成第一过孔和第二过孔;在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀形成第三过孔和第四过孔;
通过构图工艺形成包括第一连接线、第二连接线、像素电极的图形;其中,所述第一连接线通过所述第一过孔和所述第三过孔将所述源极与所述有源层的源极接触区连接;所述第二连接线通过所述第二过孔和所述第四过孔将所述漏极与所述有源层的漏极接触区,以及所述像素电极连接。
2.根据权利要求1所述的阵列基板的制备方法,其特征在于,所述形成第二绝缘层包括:
形成栅极绝缘层和形成平坦化层的步骤;所述制备方法还包括:
在形成所述栅极绝缘层和所述平坦化层之间,通过构图工艺形成包括薄膜晶体管的栅极的图形。
3.根据权利要求2所述的阵列基板的制备方法,其特征在于,所述栅极与所述有源层的导电沟道区在所述基底上的正投影完全重合;所述通过构图工艺形成包括栅极的图形之后,还包括:
对所述有源层的源极接触区和漏极接触区进行离子注入。
4.根据权利要求3所述的阵列基板的制备方法,其特征在于,所述通过构图工艺形成包括薄膜晶体管有源层的图形的同时,还包括:
形成包括存储电容的第一极板的图形;
所述对所述有源层的源极接触区和漏极接触区进行离子注入的同时,还包括:
对所述存储电容的第一极板进行离子注入。
5.根据权利要求1所述的阵列基板的制备方法,其特征在于,所述通过构图工艺形成包括薄膜晶体管源极和漏极的图形的同时,还包括:
形成包括薄膜晶体管的栅极的图形。
6.根据权利要求1-5中任意一项所述的阵列基板的制备方法,其特征在于,所述通过构图工艺形成包括薄膜晶体管源极和漏极的图形的同时,还包括:
形成包括存储电容的第二极板的图形。
7.根据权利要求1所述的阵列基板的制备方法,其特征在于,所述在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中层刻蚀形成第一过孔和第二过孔;在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀形成第三过孔和第四过孔,具体包括:
首先,在位于所述源极和所述漏极上方的所述第一绝缘层和所述第二绝缘层中刻蚀第一过孔和第二过孔对应的区域;
之后,在位于所述有源层的源极接触区和漏极接触区上方的所述第二绝缘层中刻蚀第三过孔和第四过孔对应的区域。
8.根据权利要求7所述的阵列基板的制备方法,其特征在于,刻蚀所述第二绝缘层,形成所述第三过孔和第四过孔所采用的刻蚀气体为CxFy。
9.根据权利要求1所述的阵列基板的制备方法,其特征在于,所述形成包括像素电极的图形之后,还包括:
通过一次构图工艺形成包括像素限定层和隔垫物的图形。
10.一种阵列基板,其特征在于,包括:
基底;
位于基底上方的薄膜晶体管的源极和漏极;
位于所述源极和漏极所在层上方第一绝缘层;
位于所述第一绝缘层上方的薄膜晶体管的有源层;
位于所述有源层所在层上方的第二绝缘层;
位于所述第二绝缘层所在层上方的第一连接线、第二连接线、像素电极;其中,
所述第一连接线通过贯穿位于所述源极上方的所述第一绝缘层和所述第二绝缘层的第一过孔,以及贯穿位于所述有源层的源极接触区上方的所述第二绝缘层的第三过孔,将所述源极与所述有源层的源极接触区连接;所述第二连接线通过贯穿位于所述漏极上方的所述第一绝缘层和所述第二绝缘层的第二过孔,以及贯穿位于所述有源层的漏极接触区上方的所述第二绝缘层的第四过孔,将所述漏极与所述有源层的漏极接触区和所述像素电极连接。
11.根据权利要求10所述的阵列基板,其特征在于,所述第二绝缘层包括栅极绝缘层和形成平坦化层;所述阵列基板还包括位于所述栅极绝缘层和所述平坦化层之间的薄膜晶体管的栅极。
12.根据权利要求11所述的阵列基板,其特征在于,所述栅极与所述有源层的导电沟道区在所述基底上的正投影完全重合;且在所述有源层的源极接触区和漏极接触区中掺杂有离子。
13.根据权利要求12所述阵列基板,其特征在于,所述阵列基板还包括与所述有源层同层且材料相同的存储电容的第一极板,且在所述第一极板中掺杂有离子。
14.根据权利要求10所述的阵列基板,其特征在于,所述阵列基板还包括与所述源极和所述漏极同层且材料相同的薄膜晶体管的栅极。
15.根据权利要求10-14中任一项所述的阵列基板,其特征在于,所述阵列基板还包括与所述源极和所述漏极同层且材料相同的存储电容的第二极板。
16.一种显示装置,其特征在于,包括权利要求10-15中任一项所述的阵列基板。
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