WO2016201725A1 - 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 - Google Patents

低温多晶硅tft基板的制作方法及低温多晶硅tft基板 Download PDF

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WO2016201725A1
WO2016201725A1 PCT/CN2015/082667 CN2015082667W WO2016201725A1 WO 2016201725 A1 WO2016201725 A1 WO 2016201725A1 CN 2015082667 W CN2015082667 W CN 2015082667W WO 2016201725 A1 WO2016201725 A1 WO 2016201725A1
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layer
polysilicon
insulating layer
low
thermally conductive
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PCT/CN2015/082667
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English (en)
French (fr)
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李松杉
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深圳市华星光电技术有限公司
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Priority to US14/771,502 priority Critical patent/US9520421B1/en
Publication of WO2016201725A1 publication Critical patent/WO2016201725A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon TFT substrate and a low temperature polysilicon TFT substrate.
  • Low Temperature Poly-Silicon has received industry attention in liquid crystal display (LCD) and Organic Light Emitting Diode (OLED) technology due to its high electron mobility. It is regarded as an important material for realizing low-cost full-color flat panel display.
  • low temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, low energy consumption, etc., and low temperature polysilicon can be fabricated at low temperature and can be used to fabricate C-MOS circuits. Widely researched to meet the needs of high resolution, low energy consumption.
  • Low temperature polysilicon is a branch of polysilicon (poly-Si) technology.
  • the molecular structure of polycrystalline silicon is neat and directional in a grain, so the electron mobility is 200-300 times faster than the disordered amorphous silicon (a-Si), which greatly improves the plate. The speed of the reaction shown.
  • low-temperature polysilicon is mainly produced by chemical vapor deposition (CVD), solid phase crystallization (SPC), metal-induced crystallography (MIC), and metal-induced lateral crystallization (Metal-Induced Lateral). Crystallization, MILC, Excimer Laser Annealing (ELA) and other crystallization processes.
  • a method for fabricating a conventional low-temperature polysilicon TFT substrate mainly includes the following steps: Step 1. Providing a substrate 100 to deposit a buffer layer 200 on the glass substrate 100; and Step 2: depositing a non-deposit on the buffer layer 200 A crystalline silicon (a-Si) layer 300; step 3, implanting a dose of boron on the amorphous silicon layer 300 by ion implantation, and heating by Rapid Thermal Anneal (RTA) crystallization technique 20 -30min, crystallizes amorphous silicon into polycrystalline silicon (poly-Si), and then etches away a small conductive layer deposited from the polycrystalline silicon surface during crystallization, leaving the required polysilicon layer 400; step 4, passing yellow light The etching process is performed on the polysilicon layer 400 to form a polysilicon semiconductor layer 450.
  • RTA Rapid Thermal Anneal
  • step 5 a photoresist is coated on the polysilicon semiconductor layer 450, and the photoresist is exposed and developed to obtain light on the polysilicon semiconductor layer 450.
  • a resist layer 550 exposing both end regions of the polysilicon semiconductor layer 450; 550 is a shielding layer, and boron ions are implanted into the both end regions of the polysilicon semiconductor layer 450 by ion implantation to form a source/drain contact region 451; step 6, stripping the photoresist layer 550, sequentially on the polysilicon semiconductor layer 450
  • a gate insulating layer 500, a gate electrode 600, an interlayer insulating layer 700, and source/drain electrodes 800 are formed.
  • a conventional SPC crystallization process is adopted for the formation of low-temperature polysilicon.
  • the SPC crystallization process can obtain crystal grains having good uniformity, the crystal grains are small and the grain boundaries are large, which may affect the loading.
  • the mobility of the carriers and the leakage current of the TFT device can be obtained.
  • the object of the present invention is to provide a method for fabricating a low-temperature polysilicon TFT substrate, which can effectively improve the crystallization efficiency of the crystallization process, increase the grain size, and reduce the number of grain boundaries, thereby enhancing the mobility of the carrier of the TFT device.
  • the influence of the small grain boundary on the leakage current improves the electrical conductivity of the TFT.
  • Another object of the present invention is to provide a low-temperature polysilicon TFT substrate in which the crystal grain size of the polycrystalline silicon crystal is large, the number of grain boundaries is small, the mobility of carriers of the TFT device is high, and the electrical conductivity of the TFT is good.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a thermal conductive insulating film on the buffer layer, and patterning the thermally conductive insulating film to obtain a thermally conductive insulating layer;
  • Step 3 depositing an amorphous silicon layer on the buffer layer, the amorphous silicon layer completely covering the thermal conductive insulating layer;
  • Step 4 implanting boron ions into the amorphous silicon layer by ion implantation technology, and then rapidly annealing the amorphous silicon layer to crystallize the amorphous silicon into polycrystalline silicon, and then etching away the crystallization process from the polycrystalline silicon by an etching process.
  • Step 5 patterning the polysilicon layer to form a polysilicon semiconductor layer
  • Step 6 Applying a photoresist on the polysilicon semiconductor layer, and exposing and developing the photoresist to obtain a photoresist layer on the polysilicon semiconductor layer to expose both end regions of the polysilicon semiconductor layer. And using the photoresist layer as a shielding layer, implanting boron ions into the two end regions of the polysilicon semiconductor layer by ion implantation to form source/drain contact regions;
  • Step 7 stripping the photoresist layer, sequentially forming a gate insulating layer, a gate electrode, an interlayer insulating layer, a source/drain, and a source/drain at both ends of the source/drain and the polysilicon semiconductor layer on the polysilicon semiconductor layer
  • the polar contact areas are in contact.
  • the material of the buffer layer is SiNx, SiOx, or a combination of the two.
  • the thermally conductive insulating layer is patterned by a yellow light and an etching process; the material of the thermally conductive insulating layer is Al 2 O 3 ; and the thickness of the thermally conductive insulating layer is 30-50 nm.
  • the amorphous silicon layer has a thickness of 200-300 nm.
  • the temperature of the rapid thermal annealing treatment is 650 ° C - 700 ° C, and the time is 15-25 minutes; the thickness of the conductive layer deposited on the surface of the polysilicon is etched away to a thickness of 100-150 nm.
  • the polysilicon layer is patterned by a yellow light or etching process; the pattern of the thermally conductive insulating layer corresponds to the pattern of the polysilicon semiconductor layer.
  • the material of the gate insulating layer is SiOx.
  • the invention also provides a method for manufacturing a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing a thermal conductive insulating film on the buffer layer, and patterning the thermally conductive insulating film to obtain a thermally conductive insulating layer;
  • Step 3 depositing an amorphous silicon layer on the buffer layer, the amorphous silicon layer completely covering the thermal conductive insulating layer;
  • Step 4 implanting boron ions into the amorphous silicon layer by ion implantation technology, and then rapidly annealing the amorphous silicon layer to crystallize the amorphous silicon into polycrystalline silicon, and then etching away the crystallization process from the polycrystalline silicon by an etching process.
  • Step 5 patterning the polysilicon layer to form a polysilicon semiconductor layer
  • Step 6 Applying a photoresist on the polysilicon semiconductor layer, and exposing and developing the photoresist to obtain a photoresist layer on the polysilicon semiconductor layer to expose both end regions of the polysilicon semiconductor layer. And using the photoresist layer as a shielding layer, implanting boron ions into the two end regions of the polysilicon semiconductor layer by ion implantation to form source/drain contact regions;
  • Step 7 stripping the photoresist layer, sequentially forming a gate insulating layer, a gate electrode, an interlayer insulating layer, a source/drain, and a source/drain at both ends of the source/drain and the polysilicon semiconductor layer on the polysilicon semiconductor layer
  • the contact areas of the poles are in contact;
  • the material of the buffer layer is SiNx, SiOx, or a combination of the two;
  • the thermally conductive insulating film is patterned by a yellow light, an etching process;
  • the material of the thermally conductive insulating layer is Al 2 O 3 ;
  • the thickness of the thermally conductive insulating layer is 30-50 nm;
  • the amorphous silicon layer has a thickness of 200-300 nm.
  • the present invention also provides a low-temperature polysilicon TFT substrate, comprising a substrate, a buffer layer disposed on the substrate, a thermally conductive insulating layer disposed on the buffer layer, and a polysilicon semiconductor layer disposed on the thermally conductive insulating layer.
  • a gate insulating layer Covering the thermal conductive insulating layer and the polysilicon semiconductor layer on the buffer layer a gate insulating layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate insulating layer covering the gate electrode, and an interlayer insulating layer disposed on the interlayer insulating layer Source/drain;
  • the two ends of the polysilicon semiconductor layer are source/drain contact regions implanted with boron ions; the gate insulating layer and the interlayer insulating layer are respectively provided with via holes above the source/drain contact regions The source/drain are in contact with the source/drain contact regions via the vias, respectively.
  • the material of the buffer layer is SiNx, SiOx, or a combination of the two; the material of the thermally conductive insulating layer is Al 2 O 3 ; and the material of the gate insulating layer is SiOx.
  • the thermally conductive insulating layer has a thickness of 30 to 50 nm; a pattern of the thermally conductive insulating layer corresponds to a pattern of the polycrystalline silicon semiconductor layer.
  • the invention has the beneficial effects that the low-temperature polysilicon TFT substrate of the invention is formed by forming a thermal conductive insulating layer with good insulating property and thermal conductivity on the buffer layer, so that it can be quickly absorbed in the rapid thermal annealing process. A large amount of heat is transferred to the amorphous silicon layer in contact therewith, so that the crystallization efficiency of the amorphous silicon here is improved, and polycrystalline silicon having larger crystal grains and less grain boundaries is obtained, thereby enhancing the mobility of carriers of the corresponding TFT device, Reduce the effect of grain boundaries on leakage current.
  • a thermal conductive insulating layer is disposed under the corresponding polysilicon semiconductor layer on the buffer layer, the crystal grain size of the polycrystalline silicon crystal is large, the number of grain boundaries is small, and the mobility of carriers of the TFT device is high, TFT The electrical properties are better.
  • FIG. 1 is a schematic view showing a step 1 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 2 is a schematic view showing a step 2 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 3 is a schematic view showing a step 3 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 4 is a schematic view showing a step 4 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 5 is a schematic view showing a step 5 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 6 is a schematic view showing a step 6 of a method for fabricating a conventional low-temperature polysilicon TFT substrate
  • FIG. 7 is a flow chart showing a method of fabricating a low temperature polysilicon TFT substrate of the present invention.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon TFT substrate of the present invention
  • step 9 is a schematic diagram of step 2 of a method for fabricating a low temperature polysilicon TFT substrate of the present invention.
  • step 3 is a schematic diagram of step 3 of a method for fabricating a low temperature polysilicon TFT substrate of the present invention
  • step 11 is an amorphous silicon in step 4 of the method for fabricating a low temperature polysilicon TFT substrate of the present invention; a schematic diagram of implanting a certain amount of boron in the layer;
  • step 4 is a schematic view showing the completion of step 4 of the method for fabricating the low temperature polysilicon TFT substrate of the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a low temperature polysilicon TFT substrate of the present invention
  • step 6 is a schematic diagram of step 6 of a method for fabricating a low temperature polysilicon TFT substrate of the present invention
  • 15 is a schematic view showing a step 7 of a method for fabricating a low-temperature polysilicon TFT substrate of the present invention and a schematic cross-sectional structure of the low-temperature polysilicon TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate 1, depositing a buffer layer 2 on the substrate 1;
  • the substrate 1 is a common transparent substrate.
  • the substrate 1 is a glass substrate;
  • the material of the buffer layer 2 may be SiNx, SiOx, or a combination of both.
  • Step 2 as shown in FIG. 9, a thermal insulating film is deposited on the buffer layer 2, and the thermally conductive insulating film is patterned to obtain a thermally conductive insulating layer 3;
  • the material of the thermally conductive insulating layer 3 is Al 2 O 3 .
  • the thermally conductive insulating layer 3 has a thickness of 30-50 nm.
  • the thermally conductive insulating layer 3 is patterned by a yellow light or etching process so that the size of the thermally conductive insulating layer 3 is equal to the size of the polysilicon semiconductor layer 5 to be subsequently formed.
  • Step 3 as shown in Figure 10, depositing an amorphous silicon layer 4 on the buffer layer 2, the amorphous silicon layer 4 completely covers the thermally conductive insulating layer 3;
  • the amorphous silicon layer 4 has a thickness of 200-300 nm.
  • Step 4 implanting a certain amount of boron ions into the amorphous silicon layer 4 by ion implantation, and then rapidly annealing the amorphous silicon layer 4 to crystallize the amorphous silicon.
  • the rapid thermal annealing treatment temperature is 650 ° C - 700 ° C, the time is 15-25 minutes;
  • the thickness of the conductive layer deposited on the surface of the polysilicon is etched away to a thickness of 100-150 nm, and the conductive layer is completely removed, leaving only the polysilicon structure.
  • Step 5 as shown in FIG. 13, patterning the polysilicon layer 5 by a yellow light or etching process Processing, forming a polysilicon semiconductor layer 50;
  • the pattern of the polysilicon semiconductor layer 50 corresponds to the pattern of the thermally conductive insulating layer 3.
  • Step 6 as shown in FIG. 14, a photoresist is coated on the polysilicon semiconductor layer 50, and the photoresist is exposed and developed to obtain a photoresist layer 55 on the polysilicon semiconductor layer 50, which is exposed. Both ends of the polysilicon semiconductor layer 50; with the photoresist layer 55 as a shielding layer, boron ions are implanted into the two end regions of the polysilicon semiconductor layer 50 by ion implantation to form source/drain contacts District 51;
  • Step 7 as shown in FIG. 15, the photoresist layer 55 is peeled off, and a gate insulating layer 6, a gate electrode 7, an interlayer insulating layer 8, and a source/drain electrode 9 are sequentially formed on the polysilicon semiconductor layer 50, the source The /drain 9 is in contact with the source/drain contact regions 51 in the regions of both ends of the polysilicon semiconductor layer 50.
  • the fabrication of the low temperature polysilicon TFT substrate is completed. Since the thermally conductive insulating layer 3 has good insulating properties and thermal conductivity properties, the thermally conductive insulating layer 3 can quickly absorb a large amount of heat and transfer it to the amorphous silicon layer 4 in contact with it during the RTA process, thereby making the amorphous layer there.
  • the silicon crystallization efficiency is improved, and the polycrystalline silicon layer 5 formed in the polysilicon layer 5 in the step 4 has larger crystal grains and fewer grain boundaries, and the polysilicon semiconductor layer 50 formed in the step 5 has better electrical properties, thereby enhancing the corresponding TFT device.
  • the mobility of carriers reduces the influence of grain boundaries on leakage current and improves the electrical properties of TFTs.
  • the present invention further provides a low temperature polysilicon TFT substrate, comprising a substrate 1 , a buffer layer 2 disposed on the substrate 1 , and a thermal conductive insulating layer 3 disposed on the buffer layer 2 .
  • a polysilicon semiconductor layer 50 on the thermally conductive insulating layer 3 a gate insulating layer 6 on the buffer layer 2 covering the thermally conductive insulating layer 3 and the polysilicon semiconductor layer 50, and a gate provided on the gate insulating layer 6.
  • the electrode 7 is provided on the gate insulating layer 6 to cover the interlayer insulating layer 8 of the gate electrode 7 and the source/drain electrodes 9 provided on the interlayer insulating layer 8.
  • the two end regions of the polysilicon semiconductor layer 50 are source/drain contact regions 51 implanted with boron ions; the gate insulating layer 6 and the interlayer insulating layer 8 correspond to the source/drain contact regions 51.
  • Via holes 91 are respectively provided; the source/drain electrodes 9 are in contact with the source/drain contact regions 51 via the via holes 91, respectively.
  • the material of the buffer layer 2 may be SiNx, SiOx, or a combination of the two.
  • the material of the thermally conductive insulating layer 3 is Al 2 O 3 .
  • the material of the gate insulating layer 6 is SiOx.
  • the thermally conductive insulating layer 3 has a thickness of 30-50 nm.
  • the pattern of the thermally conductive insulating layer 3 corresponds to the pattern of the polysilicon semiconductor layer 50.
  • the low-temperature polysilicon TFT substrate is provided below the corresponding polysilicon semiconductor layer on the buffer layer
  • the thermal conductive insulating layer, the crystal grain size of the polycrystalline silicon crystal is large, the number of grain boundaries is small, the mobility of carriers of the TFT device is high, and the electrical properties of the TFT are good.
  • the method for fabricating the low-temperature polysilicon TFT substrate of the present invention can form a thermal conductive insulating layer with good thermal conductivity and thermal conductivity on the buffer layer, so that it can quickly absorb a large amount in the rapid thermal annealing process.
  • the heat is transferred to the amorphous silicon layer in contact with it, so that the crystallization efficiency of the amorphous silicon here is improved, and polycrystalline silicon having larger crystal grains and less grain boundaries is obtained, thereby enhancing the mobility of carriers of the corresponding TFT device, and reducing The effect of small grain boundaries on leakage current.
  • a thermal conductive insulating layer is disposed under the corresponding polysilicon semiconductor layer on the buffer layer, the crystal grain size of the polycrystalline silicon crystal is large, the number of grain boundaries is small, and the mobility of carriers of the TFT device is high, TFT The electrical properties are better.

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Abstract

一种低温多晶硅TFT基板的制作方法及一种低温多晶硅TFT基板，所述低温多晶硅TFT基板的制作方法包括：通过在缓冲层（2）上形成一层绝缘性能及导热性质很好的导热绝缘层（3），使其在快速热退火处理过程中能很快吸收大量热量并且传给与之接触的非晶硅层（4），使此处的非晶硅结晶效率提高，得到晶粒更大、晶界更少的多晶硅（5），从而增强相应TFT器件载流子的迁移率，减小晶界对漏电流的影响。所述低温多晶硅TFT基板，在缓冲层（2）上对应多晶硅半导体层（50）的下方设有导热绝缘层（3），多晶硅结晶的晶粒尺寸较大，晶界数量较少，TFT器件载流子的迁移率较高，TFT的电性较好。

Description

低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板的制作方法及低温多晶硅TFT基板。
背景技术
随着平板显示的发展，高分辨率，低能耗的面板需求不断被提出。低温多晶硅(Low Temperature Poly-Silicon，LTPS)由于具有较高的电子迁移率，而在液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器Organic Light Emitting Diode，OLED)技术中得到了业界的重视，被视为实现低成本全彩平板显示的重要材料。对平板显示而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点，而且低温多晶硅可在低温下制作，并可用于制作C-MOS电路，因而被广泛研究，用以达到面板高分辨率，低能耗的需求。
低温多晶硅是多晶硅(poly-Si)技术的一个分支。多晶硅的分子结构在一颗晶粒中的排列状态是整齐而有方向性的，因此电子迁移率比排列杂乱的非晶硅(a-Si)快了200-300倍，极大的提高了平板显示的反应速度。目前制作低温多晶硅主要有：化学气相沉积(Chemical Vapor Deposition，CVD)、固相结晶(Solid Phase Crystallization，SPC)、金属诱导结晶(Metal-Induced Crystallization，MIC)、金属诱导横向结晶(Metal-Induced Lateral Crystallization，MILC)、准分子激光退火(Excimer Laser Annealing，ELA)等多种结晶制程方法。
请参阅图1至图6，现有低温多晶硅TFT基板的制作方法主要包括如下步骤：步骤1、提供一基板100，在玻璃基板100上沉积缓冲层200；步骤2、在缓冲层200上沉积非晶硅(a-Si)层300；步骤3、非晶硅层300上利用离子植入技术植入一定剂量的硼(boron)，再通过快速热退火(Rapid Thermal Anneal，RTA)结晶技术加热20-30min，使非晶硅结晶成多晶硅(poly-Si)，然后蚀刻掉结晶过程中从多晶硅表面析出的一层电阻很小的导电层，剩下需要的多晶硅层400；步骤4、通过黄光、蚀刻制程对多晶硅层400进行图案化处理，形成多晶硅半导体层450；步骤5、在多晶硅半导体层450上涂布光阻，通过对光阻进行曝光、显影，得到位于多晶硅半导体层450上的光阻层550，暴露出多晶硅半导体层450的两端区域；以光阻层 550为遮蔽层，对多晶硅半导体层450的两端区域，通过离子植入技术植入硼离子，形成源/漏极接触区451；步骤6、剥离光阻层550，在多晶硅半导体层450上依次形成栅极绝缘层500、栅极600、层间绝缘层700、源/漏极800。
上述低温多晶硅TFT基板的制作方法中关于低温多晶硅的形成采用传统的SPC结晶制程，该SPC结晶制程虽然能得到均一性较好的晶粒，但是晶粒偏小，晶界较多，会影响载流子的迁移率和TFT器件的漏电流。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板的制作方法，能够有效提高结晶制程的晶化效率，增大晶粒尺寸，减少晶界数量，从而可以增强TFT器件载流子的迁移率，减小晶界对漏电流的影响，提高TFT的电性。
本发明的另一目的在于提供一种低温多晶硅TFT基板，多晶硅结晶的晶粒尺寸较大，晶界数量较少，TFT器件载流子的迁移率较高，TFT的电性较好。
为实现上述目的，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在基板上沉积缓冲层；
步骤2、在缓冲层上沉积一层导热绝缘薄膜，并对该导热绝缘薄膜进行图案化处理，得到导热绝缘层；
步骤3、在缓冲层上沉积非晶硅层，所述非晶硅层完全覆盖所述导热绝缘层；
步骤4、采用离子植入技术在非晶硅层内植入硼离子，再对非晶硅层进行快速热退火处理，使非晶硅结晶成多晶硅，然后通过蚀刻工艺蚀刻掉结晶过程中从多晶硅表面析出的导电层，得到多晶硅层；
步骤5、对多晶硅层进行图案化处理，形成多晶硅半导体层；
步骤6、在所述多晶硅半导体层上涂布光阻，通过对所述光阻进行曝光、显影，得到位于所述多晶硅半导体层上的光阻层，暴露出所述多晶硅半导体层的两端区域；以所述光阻层为遮蔽层，对所述多晶硅半导体层的两端区域通过离子植入技术植入硼离子，形成源/漏极接触区；
步骤7、剥离所述光阻层，在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层两端的源/漏极接触区相接触。
所述步骤1中，所述缓冲层的材料为SiNx、SiOx、或二者的组合。
所述步骤2中，通过黄光、蚀刻制程对所述导热绝缘层进行图案化处理；所述导热绝缘层的材料为Al2O3；所述导热绝缘层的厚度为30-50nm。
所述步骤3中，所述非晶硅层的厚度为200-300nm。
所述步骤4中，快速热退火处理的温度为650℃-700℃，时间为15-25分钟；蚀刻掉多晶硅表面上析出的导电层的厚度为100-150nm。
所述步骤5中，通过黄光、蚀刻制程对多晶硅层进行图案化处理；所述导热绝缘层的图形与所述多晶硅半导体层的图形相对应。
所述步骤7中，所述栅极绝缘层的材料为SiOx。
本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在基板上沉积缓冲层；
步骤2、在缓冲层上沉积一层导热绝缘薄膜，并对该导热绝缘薄膜进行图案化处理，得到导热绝缘层；
步骤3、在缓冲层上沉积非晶硅层，所述非晶硅层完全覆盖所述导热绝缘层；
步骤4、采用离子植入技术在非晶硅层内植入硼离子，再对非晶硅层进行快速热退火处理，使非晶硅结晶成多晶硅，然后通过蚀刻工艺蚀刻掉结晶过程中从多晶硅表面析出的导电层，得到多晶硅层；
步骤5、对多晶硅层进行图案化处理，形成多晶硅半导体层；
步骤6、在所述多晶硅半导体层上涂布光阻，通过对所述光阻进行曝光、显影，得到位于所述多晶硅半导体层上的光阻层，暴露出所述多晶硅半导体层的两端区域；以所述光阻层为遮蔽层，对所述多晶硅半导体层的两端区域通过离子植入技术植入硼离子，形成源/漏极接触区；
步骤7、剥离所述光阻层，在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层两端的源/漏极接触区相接触；
其中，所述步骤1中，所述缓冲层的材料为SiNx、SiOx、或二者的组合；
其中，所述步骤2中，通过黄光、蚀刻制程对所述导热绝缘薄膜进行图案化处理；所述导热绝缘层的材料为Al2O3；所述导热绝缘层的厚度为30-50nm；
其中，所述步骤3中，所述非晶硅层的厚度为200-300nm。
本发明还提供一种低温多晶硅TFT基板，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的导热绝缘层、设于所述导热绝缘层上的多晶硅半导体层、设于所述缓冲层上覆盖所述导热绝缘层与多晶硅半导体层 的栅极绝缘层、设于所述栅极绝缘层上的栅极、设于所述栅极绝缘层上覆盖所述栅极的层间绝缘层、及设于所述层间绝缘层上的源/漏极；
所述多晶硅半导体层的两端区域为植入硼离子的源/漏极接触区；所述栅极绝缘层、及层间绝缘层上对应所述源/漏极接触区上方分别设有过孔；所述源/漏极分别经由所述过孔与所述源/漏极接触区相接触。
所述缓冲层的材料为SiNx、SiOx、或二者的组合；所述导热绝缘层的材料为Al2O3；所述栅极绝缘层的材料为SiOx。
所述导热绝缘层的厚度为30-50nm；所述导热绝缘层的图形与所述多晶硅半导体层的图形相对应。
本发明的有益效果：本发明的低温多晶硅TFT基板的制作方法，通过在缓冲层上形成一层绝缘性能及导热性质很好的导热绝缘层，使其在快速热退火处理过程中能很快吸收大量热量并且传给与之接触的非晶硅层，使此处的非晶硅结晶效率提高，得到晶粒更大、晶界更少的多晶硅，从而增强相应TFT器件载流子的迁移率，减小晶界对漏电流的影响。本发明的低温多晶硅TFT基板，缓冲层上对应多晶硅半导体层的下方设有导热绝缘层，多晶硅结晶的晶粒尺寸较大，晶界数量较少，TFT器件载流子的迁移率较高，TFT的电性较好。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图2为现有的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图3为现有的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图4为现有的低温多晶硅TFT基板的制作方法的步骤4的示意图；
图5为现有的低温多晶硅TFT基板的制作方法的步骤5的示意图；
图6为现有的低温多晶硅TFT基板的制作方法的步骤6的示意图；
图7为本发明的低温多晶硅TFT基板的制作方法的流程图；
图8为本发明的低温多晶硅TFT基板的制作方法的步骤1的示意图；
图9为本发明的低温多晶硅TFT基板的制作方法的步骤2的示意图；
图10为本发明的低温多晶硅TFT基板的制作方法的步骤3的示意图；
图11为本发明的低温多晶硅TFT基板的制作方法的步骤4中在非晶硅 层内植入一定量硼的示意图；
图12为本发明的低温多晶硅TFT基板的制作方法的步骤4完成之后的示意图；
图13为本发明的低温多晶硅TFT基板的制作方法的步骤5的示意图；
图14为本发明的低温多晶硅TFT基板的制作方法的步骤6的示意图；
图15为本发明的低温多晶硅TFT基板的制作方法的步骤7的示意图暨本发明的低温多晶硅TFT基板的剖面结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图7至图15，本发明首先提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图8所示，提供一基板1，在基板1上沉积缓冲层2；
所述基板1为普通的透明基板，优选的，所述基板1为玻璃基板；
具体地，所述缓冲层2的材料可以是SiNx、SiOx、或二者的组合。
步骤2、如图9所示，在缓冲层2上沉积一层导热绝缘薄膜，并对该导热绝缘薄膜进行图案化处理，得到导热绝缘层3；
具体的，所述导热绝缘层3的材料为的Al2O3。
优选的，所述导热绝缘层3的厚度为30-50nm。
具体地，通过黄光、蚀刻制程对所述导热绝缘层3进行图案化处理，使所述导热绝缘层3的尺寸大小等于后续要制作的多晶硅半导体层5的大小。
步骤3、如图10所示，在缓冲层2上沉积非晶硅层4，所述非晶硅层4完全覆盖所述导热绝缘层3；
优选的，所述非晶硅层4的厚度为200-300nm。
步骤4、如图11、图12所示，采用离子植入技术在非晶硅层4内植入一定量的硼离子，再对非晶硅层4进行快速热退火处理，使非晶硅结晶成多晶硅，然后通过蚀刻工艺蚀刻掉结晶过程中从多晶硅表面析出的导电层，得到多晶硅层5；
具体地，快速热退火处理的温度为650℃-700℃，时间为15-25分钟；
优选的，蚀刻掉多晶硅表面上析出的导电层的厚度为100-150nm，将所述导电层完全去除，仅剩下多晶硅结构。
步骤5、如图13所示，通过黄光、蚀刻制程对多晶硅层5进行图案化 处理，形成多晶硅半导体层50；
具体的，所述多晶硅半导体层50的图形与所述导热绝缘层3的图形相对应。
步骤6、如图14所示，在所述多晶硅半导体层50上涂布光阻，通过对所述光阻进行曝光、显影，得到位于所述多晶硅半导体层50上的光阻层55，暴露出所述多晶硅半导体层50的两端区域；以所述光阻层55为遮蔽层，对所述多晶硅半导体层50的两端区域，通过离子植入技术植入硼离子，形成源/漏极接触区51；
步骤7、如图15所示，剥离所述光阻层55，在多晶硅半导体层50上依次形成栅极绝缘层6、栅极7、层间绝缘层8、源/漏极9，所述源/漏极9与多晶硅半导体层50两端区域的源/漏极接触区51相接触。
至此，完成该低温多晶硅TFT基板的制作。由于导热绝缘层3具有很好的绝缘性能及导热性质，在RTA处理过程中，导热绝缘层3能很快吸收大量热量并且传给与之接触的非晶硅层4，使此处的非晶硅结晶效率提高，所述步骤4中形成的多晶硅层5内的多晶硅的晶粒更大、晶界更少，步骤5中形成的多晶硅半导体层50的电性较好，从而可以增强相应TFT器件载流子的迁移率，减小晶界对漏电流的影响，改善TFT的电性。
请参阅图15，本发明还提供一种低温多晶硅TFT基板，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的导热绝缘层3、设于所述导热绝缘层3上的多晶硅半导体层50、设于所述缓冲层2上覆盖所述导热绝缘层3与多晶硅半导体层50的栅极绝缘层6、设于所述栅极绝缘层6上的栅极7、设于所述栅极绝缘层6上覆盖所述栅极7的层间绝缘层8、及设于所述层间绝缘层8上的源/漏极9。
所述多晶硅半导体层50的两端区域为植入硼离子的源/漏极接触区51；所述栅极绝缘层6、及层间绝缘层8上对应所述源/漏极接触区51上方分别设有过孔91；所述源/漏极9分别经由所述过孔91与所述源/漏极接触区51相接触。
具体的，所述缓冲层2的材料可以是SiNx、SiOx、或二者的组合。
优选的，所述导热绝缘层3的材料为Al2O3。具体的，所述栅极绝缘层6的材料为SiOx。
优选的，所述导热绝缘层3的厚度为30-50nm。
具体的，所述导热绝缘层3的图形与所述多晶硅半导体层50的图形相对应。
上述低温多晶硅TFT基板，缓冲层上对应多晶硅半导体层的下方设有 导热绝缘层，多晶硅结晶的晶粒尺寸较大，晶界数量较少，TFT器件载流子的迁移率较高，TFT的电性较好。
综上所述，本发明的低温多晶硅TFT基板的制作方法，通过在缓冲层上形成一层绝缘性能及导热性质很好的导热绝缘层，使其在快速热退火处理过程中能很快吸收大量热量并且传给与之接触的非晶硅层，使此处的非晶硅结晶效率提高，得到晶粒更大、晶界更少的多晶硅，从而增强相应TFT器件载流子的迁移率，减小晶界对漏电流的影响。本发明的低温多晶硅TFT基板，缓冲层上对应多晶硅半导体层的下方设有导热绝缘层，多晶硅结晶的晶粒尺寸较大，晶界数量较少，TFT器件载流子的迁移率较高，TFT的电性较好。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在基板上沉积缓冲层；
    步骤2、在缓冲层上沉积一层导热绝缘薄膜，并对该导热绝缘薄膜进行图案化处理，得到导热绝缘层；
    步骤3、在缓冲层上沉积非晶硅层，所述非晶硅层完全覆盖所述导热绝缘层；
    步骤4、采用离子植入技术在非晶硅层内植入硼离子，再对非晶硅层进行快速热退火处理，使非晶硅结晶成多晶硅，然后通过蚀刻工艺蚀刻掉结晶过程中从多晶硅表面析出的导电层，得到多晶硅层；
    步骤5、对多晶硅层进行图案化处理，形成多晶硅半导体层；
    步骤6、在所述多晶硅半导体层上涂布光阻，通过对所述光阻进行曝光、显影，得到位于所述多晶硅半导体层上的光阻层，暴露出所述多晶硅半导体层的两端区域；以所述光阻层为遮蔽层，对所述多晶硅半导体层的两端区域通过离子植入技术植入硼离子，形成源/漏极接触区；
    步骤7、剥离所述光阻层，在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层两端的源/漏极接触区相接触。
  2. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤1中，所述缓冲层的材料为SiNx、SiOx、或二者的组合。
  3. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤2中，通过黄光、蚀刻制程对所述导热绝缘薄膜进行图案化处理；所述导热绝缘层的材料为Al2O3；所述导热绝缘层的厚度为30-50nm。
  4. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤3中，所述非晶硅层的厚度为200-300nm。
  5. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤4中，快速热退火处理的温度为650℃-700℃，时间为15-25分钟；蚀刻掉多晶硅表面上析出的导电层的厚度为100-150nm。
  6. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤5中，通过黄光、蚀刻制程对多晶硅层进行图案化处理；所述导热绝缘层的图形与所述多晶硅半导体层的图形相对应。
  7. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述 步骤7中，所述栅极绝缘层的材料为SiOx。
  8. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在基板上沉积缓冲层；
    步骤2、在缓冲层上沉积一层导热绝缘薄膜，并对该导热绝缘薄膜进行图案化处理，得到导热绝缘层；
    步骤3、在缓冲层上沉积非晶硅层，所述非晶硅层完全覆盖所述导热绝缘层；
    步骤4、采用离子植入技术在非晶硅层内植入硼离子，再对非晶硅层进行快速热退火处理，使非晶硅结晶成多晶硅，然后通过蚀刻工艺蚀刻掉结晶过程中从多晶硅表面析出的导电层，得到多晶硅层；
    步骤5、对多晶硅层进行图案化处理，形成多晶硅半导体层；
    步骤6、在所述多晶硅半导体层上涂布光阻，通过对所述光阻进行曝光、显影，得到位于所述多晶硅半导体层上的光阻层，暴露出所述多晶硅半导体层的两端区域；以所述光阻层为遮蔽层，对所述多晶硅半导体层的两端区域通过离子植入技术植入硼离子，形成源/漏极接触区；
    步骤7、剥离所述光阻层，在多晶硅半导体层上依次形成栅极绝缘层、栅极、层间绝缘层、源/漏极，所述源/漏极与多晶硅半导体层两端的源/漏极接触区相接触；
    其中，所述步骤1中，所述缓冲层的材料为SiNx、SiOx、或二者的组合；
    其中，所述步骤2中，通过黄光、蚀刻制程对所述导热绝缘薄膜进行图案化处理；所述导热绝缘层的材料为Al2O3；所述导热绝缘层的厚度为30-50nm；
    其中，所述步骤3中，所述非晶硅层的厚度为200-300nm。
  9. 如权利要求8所述的低温多晶硅TFT基板的制作方法，其中，所述步骤4中，快速热退火处理的温度为650℃-700℃，时间为15-25分钟；蚀刻掉多晶硅表面上析出的导电层的厚度为100-150nm。
  10. 如权利要求8所述的低温多晶硅TFT基板的制作方法，其中，所述步骤5中，通过黄光、蚀刻制程对多晶硅层进行图案化处理；所述导热绝缘层的图形与所述多晶硅半导体层的图形相对应。
  11. 如权利要求8所述的低温多晶硅TFT基板的制作方法，其中，所述步骤7中，所述栅极绝缘层的材料为SiOx。
  12. 一种低温多晶硅TFT基板，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的导热绝缘层、设于所述导热绝缘层上的多晶硅半导体 层、设于所述缓冲层上覆盖所述导热绝缘层与多晶硅半导体层的栅极绝缘层、设于所述栅极绝缘层上的栅极、设于所述栅极绝缘层上覆盖所述栅极的层间绝缘层、及设于所述层间绝缘层上的源/漏极；
    所述多晶硅半导体层的两端区域为植入硼离子的源/漏极接触区；所述栅极绝缘层、及层间绝缘层上对应所述源/漏极接触区上方分别设有过孔；所述源/漏极分别经由所述过孔与所述源/漏极接触区相接触。
  13. 如权利要求12所述的低温多晶硅TFT基板，其中，所述缓冲层的材料为SiNx、SiOx、或二者的组合；所述导热绝缘层的材料为Al2O3；所述栅极绝缘层的材料为SiOx。
  14. 如权利要求12所述的低温多晶硅TFT基板，其中，所述导热绝缘层的厚度为30-50nm；所述导热绝缘层的图形与所述多晶硅半导体层的图形相对应。
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