WO2019071694A1 - 低温多晶硅薄膜及晶体管的制造方法 - Google Patents

低温多晶硅薄膜及晶体管的制造方法 Download PDF

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WO2019071694A1
WO2019071694A1 PCT/CN2017/110124 CN2017110124W WO2019071694A1 WO 2019071694 A1 WO2019071694 A1 WO 2019071694A1 CN 2017110124 W CN2017110124 W CN 2017110124W WO 2019071694 A1 WO2019071694 A1 WO 2019071694A1
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layer
buffer layer
silicon
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manufacturing
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French (fr)
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单剑锋
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惠科股份有限公司
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02524—Group 14 semiconducting materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/0259—Microstructure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

Definitions

  • the present application relates to a method for fabricating a silicon thin film and a transistor, and more particularly to a method for manufacturing a low temperature polysilicon film and a transistor.
  • Planar display devices have been widely used in various fields. Due to their superior characteristics such as slimness, low power consumption and no radiation, liquid crystal display devices have gradually replaced traditional cathode ray tube display devices and applied to many kinds of electronic products. Among them, such as mobile phones, portable multimedia devices, notebook computers, LCD TVs, and LCD screens, and the like.
  • the liquid crystal display device includes components such as a display panel, and the active matrix type liquid crystal display panel is a general display panel including an active matrix substrate, a counter substrate, and a liquid crystal layer interposed between the two substrates.
  • the active matrix substrate has a plurality of row wires, column wires and pixels, and the pixel has a pixel driving component, and the pixel driving component is connected with the row wires and the column wires.
  • a typical pixel drive component is a thin film transistor, and the row and column conductors are typically metal wires.
  • the thin film transistor of the active matrix substrate can be divided into a conventional amorphous silicon thin film transistor and a low temperature polysilicon thin film transistor with better conductivity.
  • Low-temperature polysilicon process often uses excimer laser annealing technology, that is, using excimer laser as heat source, laser illumination sets amorphous silicon film to recrystallize amorphous silicon, and transform into polysilicon structure, because the whole process is 600. It is completed below °C, so general glass substrates are applicable.
  • the use of laser annealing tends to cause protrusions on the surface of the polysilicon layer. The size of the protrusions affects the current characteristics of the transistor, which causes the operational characteristics of the transistors on the panel to be different, resulting in degradation of display quality.
  • the purpose of the present application is to provide a method for manufacturing a low-temperature polysilicon film and a transistor thereof, which can improve the protrusion problem on the surface of the low-temperature polysilicon film.
  • the present application provides a method for fabricating a low temperature polysilicon film, comprising: forming a buffer layer on a substrate, the surface of the buffer layer having a plurality of pores; forming a silicon layer on the buffer layer; The layer is annealed to form a polysilicon layer and a portion of the silicon material of the polysilicon layer is filled into the pores.
  • the step of forming the buffer layer on the substrate comprises: forming a first sub-buffer layer on the substrate; forming a second sub-layer on the first sub-buffer layer a buffer layer, the second sub-buffer layer being finer than the first sub-buffer layer.
  • the first sub-buffer layer is a diffusion barrier layer.
  • the manufacturing method further includes roughening the buffer layer to form the pores on a surface of the buffer layer before forming the silicon layer on the buffer layer.
  • the manufacturing method further includes roughening the surface of the silicon layer to form an uneven surface as a recrystallization growth space; wherein a portion of the silicon material of the polysilicon layer is formed into a recrystallization growth space.
  • the step of roughening the surface of the silicon layer is to etch the surface of the silicon layer.
  • the manufacturing method further includes: providing a mask before annealing the silicon layer to form the polysilicon layer; transferring a pattern from the mask to the silicon layer, the pattern There is room for recrystallization growth.
  • a portion of the pattern transferred over the silicon layer serves as a channel region, and the recrystallized growth space is located at a side of the portion.
  • the annealing is a laser annealing.
  • the method of fabricating further includes forming a fill layer on the silicon layer prior to annealing the silicon layer to form the polysilicon layer.
  • the present application provides a method for fabricating a low temperature polysilicon thin film transistor, comprising: a step of a method for fabricating a low temperature polysilicon film; forming a gate insulating layer on the polysilicon layer; and forming a gate on the gate insulating layer a gate electrode; a source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the polysilicon layer.
  • the low temperature polysilicon film and the transistor manufacturing method of the present application are provided
  • the amorphous silicon recrystallizes into a space for growth, which can relieve the intergranular extrusion during the recrystallization of the amorphous silicon, thereby making the size of the protrusion on the surface of the polysilicon layer significantly smaller.
  • the aspect ratio of the protrusions is less than 0.3 or even less than 0.2. Therefore, the problem of protrusion on the surface of the low-temperature polysilicon film can be improved.
  • FIGS. 1A to 1C are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • 1D is a schematic view of an embodiment of a method of fabricating a low temperature polysilicon thin film transistor of the present application.
  • FIGS. 2A to 2C are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • 3A to 3D are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • 4A to 4E are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • first and second may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two components.
  • FIG. 1A to 1C are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • a method of manufacturing a low temperature polysilicon film first provides a substrate 11, which is, for example, a glass substrate. Then, a buffer layer 12 is formed on the substrate 11. The surface of the buffer layer 12 has a plurality of pores which serve as a space for subsequent recrystallization of the silicon layer.
  • the manufacturing method may further include roughening the buffer layer 12 to form voids on the surface of the buffer layer 12, for example, the pore diameter is less than 20 nm.
  • the roughened surface is an uneven surface.
  • a silicon layer 13 is formed on the buffer layer 12, and at this time, most of the silicon layer 13 is formed on the surface of the buffer layer 12, and the pores of the buffer layer 12 are still free from the material of the silicon layer 13. Fill In.
  • the silicon layer 13 can be deposited on the buffer layer 12 in a conventional manner, and the material of the silicon layer 13 is amorphous silicon.
  • the silicon layer 13 of amorphous silicon is formed, the silicon layer 13 is annealed to form a polysilicon layer 14, and a portion of the silicon material 140 of the polysilicon layer 14 is filled into the pores 120.
  • Annealing is, for example, laser annealing, and the annealing process temperature is below 600 degrees Celsius.
  • the polycrystalline silicon film obtained by such a process can be called low temperature poly-silicon (LTPS).
  • LTPS low temperature poly-silicon
  • the process temperature of the low temperature polysilicon is relatively low, so the substrate material is not limited, for example, the substrate 11 can use a glass substrate.
  • the polysilicon layer 14 is formed by converting an original amorphous silicon layer into a polysilicon layer by an annealing process such as laser crystalization or excimer laser annealing (ELA). During the annealing process, the amorphous silicon in the silicon layer 13 is melted, recrystallized, and rearranged to become polycrystalline silicon, thereby forming the polysilicon layer 14, and a plurality of protrusions are formed on the surface of the polysilicon layer 14, and the protrusions may be formed on the surface. The upper or lower surface of the polysilicon layer 14.
  • an annealing process such as laser crystalization or excimer laser annealing (ELA).
  • ELA excimer laser annealing
  • part of the amorphous silicon When amorphous silicon recrystallizes, part of the amorphous silicon first acts as a recrystallized seed, and then the crystal grows into a larger crystal, and these crystals continuously grow and combine to form larger crystals. However, during the bonding process, since the crystals interact with each other, a part of the crystal is pushed onto the surface of the polysilicon layer 14 to form a protrusion.
  • the buffer layer 12 leaves the voids 120 for the recrystallized protrusions, at least the protrusions 140 on the lower surface of the polysilicon layer 14 can be filled into the pores 120.
  • the apertures 120 also constrain the size and shape of the protrusions 140 to avoid excessive protrusions.
  • protrusions are also generated on the upper surface of the polysilicon layer 14, since the partial protrusions are changed to the lower surface of the polysilicon layer 14, the protrusion of the upper surface is improved.
  • the aspect ratio of the protrusions of the polysilicon layer of the conventional process is about 0.45.
  • the aspect ratio of the protrusions of the polysilicon layer 14 can be lowered to 0.3 or less, and can even be reduced to 0.2 or less.
  • the upper and lower surfaces of the polysilicon layer 14 have protrusions, the aspect ratio of the protrusions is not excessively large and affects the performance of the module.
  • FIG. 1D is a schematic view of an embodiment of a method of fabricating a low temperature polysilicon thin film transistor of the present application.
  • a subsequent process is performed to form a thin film transistor.
  • the manufacturing method of the low temperature polysilicon thin film transistor includes: forming a gate insulating layer 15 on the polysilicon layer 14; and forming a gate 16 on the gate insulating layer 15; forming a source The electrode 18 and a drain electrode 19, the source electrode and the drain electrode are electrically connected to the polysilicon layer.
  • the low temperature polysilicon thin film transistor includes a polysilicon layer 14, a gate insulating layer 15, a gate 16, a dielectric layer 17, a source electrode 18, and a drain electrode 19.
  • the polysilicon layer 14 is first patterned, and the patterned polysilicon layer 14 includes three regions as a source 141, a drain 143, and a channel region 142, respectively, and the channel region 142 is located between the source 141 and the drain 143.
  • a gate insulating layer 15 is formed over the patterned polysilicon layer 14 and the substrate 11.
  • the gate insulating layer 15 is made of, for example, silicon oxide or silicon nitride.
  • a gate 16 is formed over the gate insulating layer 15 and the channel region 142.
  • a dielectric layer 17 is formed on the gate electrode 16 and the gate insulating layer 15, and the dielectric layer 17 and the gate insulating layer 15 are patterned to form a via hole, and the via hole exposes the source electrode 141 and the drain electrode. 143.
  • the source electrode 18 and the drain electrode 19 are formed on the surface of the dielectric layer 17 and the via hole.
  • the source electrode 18 passes through the via hole to contact the source electrode 141
  • the drain electrode 19 passes through the via hole to contact the drain electrode 143. Therefore, the source electrode 18 and The drain electrode 19 is electrically connected to the source 141 and the drain 143 of the polysilicon layer 14, respectively.
  • the low temperature polysilicon thin film transistor is not limited to a liquid crystal display panel or an organic light emitting diode panel.
  • the substrate 11 may be composed of glass, quartz, or the like.
  • the buffer layer 12 may be made of a material such as SiN x , SiO x or SiO x N y .
  • FIG. 2A to 2C are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • a method of manufacturing a low temperature polysilicon film first provides a substrate 21, which is, for example, a glass substrate. Then, a buffer layer 22 is formed on the substrate 21.
  • the buffer layer 22 may have a multi-layer structure. In this embodiment, the two layers are exemplified, but the number of layers is not limited to two layers, and more layers may be provided.
  • the buffer layer 22 includes a first sub-buffer layer 221 and a second sub-buffer layer 222.
  • the step of forming the buffer layer 22 includes: forming a first sub-buffer layer 221 on the substrate 21, and then on the first sub-buffer layer 221 A second sub-buffer layer 222 is formed.
  • These sub-buffer layers may have different fineness, and the uppermost sub-buffer layer of the buffer layer 22 may have lower fineness, thereby forming pores on the upper surface of the uppermost sub-buffer layer to be required for recrystallization of the silicon layer.
  • Space For example, the second sub-buffer layer 222 is lower in fineness than the first sub-buffer layer 221, and therefore, the upper surface of the second sub-buffer layer 222 has a plurality of pores 220, and the pores 220 can serve as a space for re-crystallization of the subsequent silicon layer.
  • the manufacturing method may roughen the second sub-buffer layer 222 to form the voids 220 on the surface of the buffer layer, for example, the pore diameter is less than 20 nm.
  • the roughened surface is an uneven surface.
  • the roughening may include etching.
  • the etching may be dry etching or wet etching.
  • the process parameters of the dry etching include frequency, gas pressure, ion density, etching time, etc.
  • the process parameters of the wet etching include solution concentration, etching time, reaction temperature, and solution. Stir and so on.
  • the roughening process eliminates the need for mask pattern transfer, eliminating the need for photoresist on the buffer layer, and eliminating the need for a mask and exposure.
  • the first sub-buffer layer is a diffusion barrier layer. Due to the diffusion of impurities in the substrate 21 to other layers during the annealing process, the diffusion barrier layer can block at least part of the impurities and prevent excessive impurities from diffusing into the silicon layer.
  • the first sub-buffer layer has a higher degree of fineness than the second sub-buffer layer, thereby having a better diffusion barrier effect.
  • the manufacturing method may roughen the first sub-buffer layer 221 to have a better diffusion barrier effect.
  • the roughened surface is an uneven surface.
  • a silicon layer 23 is formed on the second sub-buffer layer 222 of the buffer layer 22, and at this time, most of the silicon layer 23 is formed on the upper surface of the second sub-buffer layer 222, the buffer layer 12 The pores still have space that is not filled by the material of the silicon layer 23.
  • the silicon layer 23 can be deposited on the second sub-buffer layer 222 in a conventional manner, the material of the silicon layer 23 being amorphous silicon.
  • the silicon layer 23 of amorphous silicon is formed, the silicon layer 23 is annealed to form a polysilicon layer 24, and a portion of the silicon material 240 of the polysilicon layer 24 is filled into the pores of the second sub-buffer layer 222. 220. Since the polysilicon layer 24 is formed in a similar manner and structure to the polysilicon layer 14, it will not be described.
  • FIG. 1D After the polysilicon layer 24 is formed, a subsequent process may be performed as shown in FIG. 1D to form a thin film transistor. Since the manufacturing method of the transistor can refer to the related description of FIG. 1D, it will not be described again.
  • the substrate 21 may be composed of glass, quartz, or the like.
  • the sublayer of the buffer layer 22 may be made of a material such as SiN x , SiO x or SiO x N y .
  • the method for manufacturing the low-temperature polysilicon film may further include: rough
  • the surfaces of the silicon layers 13, 23 are formed to form an uneven surface as a recrystallization growth space.
  • the surface roughness of the roughened surface is between 5 nm and 30 nm.
  • a portion of the silicon material of the polysilicon layers 14, 24 is formed into a recrystallization growth space.
  • the surface of the roughened silicon layers 13, 23 is, for example, the surface of the etched silicon layers 13, 23.
  • the roughening may include etching.
  • the etching may be dry etching or wet etching.
  • the process parameters of the dry etching include frequency, gas pressure, ion density, etching time, etc.
  • the process parameters of the wet etching include solution concentration, etching time, reaction temperature, and solution. Stir and so on.
  • the roughening process eliminates the need for mask pattern transfer, eliminating the need for photoresist on the silicon layer, and eliminating the need for a mask and exposure.
  • the manufacturing method of the low-temperature polysilicon film can further include: providing a mask before transferring the silicon layer to form the polysilicon layer; and transferring from the mask A pattern is applied to the silicon layer, the pattern leaving a recrystallization growth space.
  • the recrystallized growth space is located on the side of the pattern.
  • the pattern on the silicon layer is transferred through the reticle pattern transfer process. For example, an entire layer of photoresist is deposited on the unpatterned silicon layer, and then the photoresist is exposed through the reticle, and the reticle pattern is first transferred to the photoresist. Then, an etching process is used to etch the silicon layer that is not protected by the photoresist, and thus the mask pattern is transferred to the silicon layer.
  • a part of the pattern transferred on the silicon layer serves as a channel region, and a recrystallized growth space is left on the side of the portion.
  • the pattern of the reticle is used to define the source, drain, channel region, and recrystallization growth space on the silicon layer. After the pattern of the reticle is transferred to the silicon layer, if the silicon is viewed from above the substrate The layer, the channel region is planarly located between the source and the drain, and the recrystallized growth space is located on the side of the channel region of the silicon layer, and even the recrystallized growth space can be simultaneously located on the side of the source and drain of the silicon layer. .
  • the side surfaces may be roughened by etching to form more uneven surfaces as recrystallization.
  • the long space for example, the surface roughness of the roughened surface is between 5 nm and 30 nm.
  • the method for fabricating the low temperature polysilicon film may further include: forming a compensation layer on the silicon layers 13, 23 before annealing the silicon layers 13, 23 to form the polysilicon layers 14, 24. Since the impurities of the substrates 11, 21 are diffused during annealing, the trapping layer can be provided to capture these impurities and prevent impurities from accumulating in the polysilicon layers 14, 24.
  • the material of the trap layer is, for example, a material such as SiN x , SiO x or SiO x N y .
  • the trapping layer can be achieved by adjusting the process parameters, for example, the low density SiO x film layer can be adjusted by adjusting the ratio of the reactant SiH 4 to N 2 O, or the reactants TEOS and O 2 or O 3 .
  • the ratio is formed.
  • the intergranular extrusion during the recrystallization of the amorphous silicon can be relieved, and the protrusion size on the surface of the polysilicon layer can be made.
  • the aspect ratio of the protrusions is less than 0.3 or even less than 0.2.
  • the aspect ratio of the surface protrusions of the polysilicon layer is less than 0.3, the component characteristics of the components can be made uniform.
  • the color uniformity of the display panel can be improved.
  • FIG. 3A to 3D are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • the manufacturing method provides a substrate 31 which is, for example, a glass substrate.
  • a buffer layer 32 is formed on the substrate 31.
  • the manufacturing method includes roughening the surface of the silicon layer 33 to form an uneven surface as a recrystallization growth space, for example, the surface roughness of the roughened surface is between 5 nm and 30 nm.
  • the surface of the roughened silicon layer 33 is, for example, the surface of the etched silicon layer 33.
  • the silicon layer 33 can be deposited on the buffer layer 32 in a conventional manner, and the material of the silicon layer 33 is amorphous silicon.
  • the fabrication method anneals the silicon layer 33 to form a polysilicon layer 34, and forms part of the silicon material of the polysilicon layer 34 into a recrystallization growth space.
  • annealing such as laser annealing, annealing and amorphous silicon recrystallization
  • the aspect ratio of the protrusion of the polysilicon layer of the conventional process is about 0.45. Compared with the conventional process, the aspect ratio of the protrusion of the polysilicon layer 34 can be reduced to 0.3 or less, and can even be reduced to 0.2 or less, and the protrusion is reduced. The effect of the object on the performance of the component.
  • FIG. 1D After the polysilicon layer 34 is formed, a subsequent process may be performed as shown in FIG. 1D to form a thin film transistor. Since the manufacturing method of the transistor can refer to the related description of FIG. 1D, it will not be described again.
  • the buffer layer 32 can also adopt the embodiment of FIGS. 1A and 2A described above.
  • the buffer layer 32 may adopt the foregoing embodiment of FIG. 1A.
  • the surface of the buffer layer 32 has a plurality of pores, and the pores may serve as a space for recrystallization of the subsequent silicon layer, and a part of the silicon material of the annealed polysilicon layer is filled into the pores.
  • the manufacturing method may further include roughening the buffer layer 32 to form voids on the surface of the buffer layer 32. Since the related embodiments can refer to the related description of FIG. 1A described above, it will not be described again.
  • the buffer layer 32 can also employ the embodiment of Figure 2A previously described.
  • the step of forming the buffer layer 32 includes: forming a first sub-buffer layer on the substrate 31; forming a second sub-buffer layer on the first sub-buffer layer, the second sub-buffer layer being lower in detail than the first Subbuffer layer.
  • the first sub-buffer layer can be a diffusion barrier layer. Since the related embodiments can refer to the related description of FIG. 2A described above, it will not be described again.
  • the method for fabricating the low temperature polysilicon film can further include: providing a mask before annealing the silicon layer to form the polysilicon layer; and transferring a pattern from the mask to In the silicon layer, the pattern leaves a recrystallization growth space.
  • the recrystallized growth space is located on the side of the pattern.
  • the method for fabricating the low temperature polysilicon film may further include: forming a compensation layer on the silicon layer 33 before annealing the silicon layer 33 to form the polysilicon layer 34, due to impurities of the substrate 31 during annealing. It will diffuse and the trapping layer can be used to capture these impurities and prevent impurities from accumulating in the polysilicon layer 34.
  • the intergranular extrusion during the recrystallization of the amorphous silicon can be relieved, and the protrusion size on the surface of the polysilicon layer can be made.
  • the aspect ratio of the protrusions is less than 0.3. Even less than 0.2.
  • FIG. 4A to 4E are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.
  • the manufacturing method provides a substrate 41 which is, for example, a glass substrate.
  • a buffer layer 42 is formed on the substrate 41.
  • FIG. 4B is a side view of a low temperature polysilicon film
  • FIG. 4C is a top view of FIG. 4B.
  • the fabrication method includes forming a silicon layer 43 on the buffer layer 42, which may be deposited on the buffer layer 42 in a conventional manner, the material of the silicon layer 43 being amorphous silicon.
  • the manufacturing method includes providing a photomask; transferring a pattern from the photomask to the silicon layer 43, the pattern leaving a recrystallization growth space, and the recrystallized growth space is located on the side of the pattern.
  • the buffer layer 42 When the silicon layer 43 is viewed from above the substrate 41, the buffer layer 42 is seen because the recrystallized growth space is located on the side of the pattern on the silicon layer 43. The recesses above the buffer layer 42 and on the side of the pattern on the silicon layer 43 form a recrystallized growth space.
  • the pattern of the reticle is used to define the position of the source, the drain, the channel region, and the recrystallized growth space on the silicon layer 43, and the pattern of the reticle is transferred to the silicon layer 43 if the substrate 41 is removed from the substrate 41.
  • the silicon layer 43 is viewed from above, the channel region is planarly located between the source and the drain, and the recrystallized growth space is located on the side of the channel region of the silicon layer 43, and even the recrystallized growth space can be simultaneously located at the source of the silicon layer 43.
  • the side of the drain is viewed from above, the channel region is planarly located between the source and the drain, and the recrystallized growth space is located on the side of the channel region of the silicon layer 43, and even the recrystallized growth space can be simultaneously located at the source of the silicon layer 43.
  • the side of the drain is viewed from above, the channel region is planarly located between the source and the drain, and the recrystallized growth space is located on the side of the channel
  • the surface of the silicon layer 43 may be roughened to form an uneven surface as a recrystallization growth space.
  • the surface of the roughened silicon layer 43 is, for example, the surface of the etched silicon layer 43, for example, the surface roughness of the roughened surface is between 5 nm and 30 nm. Thereby, both the upper surface and the side surface of the silicon layer 43 have a recrystallization growth space.
  • FIG. 4D is a side view of a low temperature polysilicon film
  • FIG. 4D is a top view of FIG. 4C.
  • the fabrication method anneals the silicon layer 43 to form a polysilicon layer 44 and forms a portion of the silicon material of the polysilicon layer 44 into a recrystallized growth space.
  • the intergranular extrusion during recrystallization can be relieved, and the size of the protrusion on the surface of the polysilicon layer 44 can be significantly reduced.
  • annealing such as laser annealing, annealing and amorphous silicon recrystallization
  • the silicon layer 43 itself has a recrystallization growth space for the recrystallized protrusions, as shown in FIG. 4E, at least the protrusions on the upper surface of the polysilicon layer 44 can be filled into the recrystallization growth space.
  • Conventional system The aspect ratio of the protrusions of the polysilicon layer of the process is about 0.45. Compared with the conventional process, the aspect ratio of the protrusions of the polysilicon layer 44 can be lowered to 0.3 or less, and can even be reduced to 0.2 or less, and the protrusion pair can be reduced. The impact of component performance.
  • FIG. 1D After the polysilicon layer 44 is formed, a subsequent process may be performed as shown in FIG. 1D to form a thin film transistor. Since the manufacturing method of the transistor can refer to the related description of FIG. 1D, it will not be described again.
  • buffer layer 42 can also adopt the embodiment of FIGS. 1A and 2A described above.
  • the buffer layer 42 may adopt the foregoing embodiment of FIG. 1A.
  • the surface of the buffer layer 42 has a plurality of pores, and the pores may serve as a space for recrystallization of the subsequent silicon layer, and a part of the silicon material of the annealed polysilicon layer is filled into the pores.
  • the manufacturing method may further include roughening the buffer layer 42 to form voids on the surface of the buffer layer 42, for example, the pore diameter is less than 20 nm. Since the related embodiments can refer to the related description of FIG. 1A described above, it will not be described again.
  • the buffer layer 42 can also employ the embodiment of Figure 2A described above.
  • the step of forming the buffer layer 42 includes: forming a first sub-buffer layer on the substrate 41; forming a second sub-buffer layer on the first sub-buffer layer, the second sub-buffer layer being lower in detail than the first Subbuffer layer.
  • the first sub-buffer layer can be a diffusion barrier layer. Since the related embodiments can refer to the related description of FIG. 2A described above, it will not be described again.
  • the intergranular extrusion during the recrystallization of the amorphous silicon can be relieved, and the protrusion size on the surface of the polysilicon layer can be made.
  • the aspect ratio of the protrusions is less than 0.3 or even less than 0.2.
  • the aspect ratio of the surface protrusions of the polysilicon layer is less than 0.3, the component characteristics of the components can be made uniform.
  • the color uniformity of the display panel can be improved.

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Abstract

一种低温多晶硅薄膜的制造方法，包括：在一衬底上形成一缓冲层，所述缓冲层的表面具有多个孔隙；在所述缓冲层上形成一硅层；对所述硅层进行退火以形成一多晶硅层，并使所述多晶硅层的部分硅材料填入至所述孔隙。

Description

低温多晶硅薄膜及晶体管的制造方法 技术领域
本申请关于一种硅薄膜及晶体管的制造方法，特别关于一种低温多晶硅薄膜及晶体管的制造方法。
背景技术
平面显示装置已经广泛的被运用在各种领域，液晶显示装置因具有体型轻薄、低功率消耗及无辐射等优越特性，已经渐渐地取代传统阴极射线管显示装置，而应用至许多种类的电子产品中，例如行动电话、可携式多媒体装置、笔记型计算机、液晶电视及液晶屏幕等等。
液晶显示装置包括显示面板等组件，有源矩阵型液晶显示面板是目前一般的显示面板，其包括有源矩阵衬底、对向衬底、以及夹设在这二衬底间的液晶层。有源矩阵衬底上具有多个行导线、列导线以及像素，像素中有像素驱动组件，像素驱动组件和行导线及列导线连接。一般的像素驱动组件是薄膜晶体管，行导线及列导线通常是金属导线。
有源矩阵衬底的薄膜晶体管可分为传统的非晶硅薄膜晶体管以及导电能力较佳的低温多晶硅薄膜晶体管。低温多晶硅制程常采用准分子雷射退火技术，亦即利用准分子雷射作为热源，雷射光照设非晶硅薄膜使非晶硅再结晶，转变成为多晶硅结构，因整个处理过程都是在600℃以下完成，所以一般玻璃衬底皆可适用。但利用雷射退火容易造成多晶硅层表面有突起物，突起物的尺寸影响晶体管的电流特性，这会造成面板上晶体管的操作特性不一，因而导致显示质量下降。
发明内容
有鉴于先前技术的不足，发明人经研发后得本申请。本申请的目的为提供一种低温多晶硅薄膜及其晶体管的制造方法，可改善低温多晶硅薄膜表面的突起问题。
本申请提出一种低温多晶硅薄膜的制造方法，包括：在一衬底上形成一缓冲层，所述缓冲层的表面具有多个孔隙；在所述缓冲层上形成一硅层；对所述硅层进行退火以形成一多晶硅层，并使所述多晶硅层的部分硅材料填入至所述孔隙。
在一实施例中，其中在所述衬底上形成所述缓冲层的步骤包括：在所述衬底上形成一第一子缓冲层；在所述第一子缓冲层上形成一第二子缓冲层，所述第二子缓冲层的细致度低于所述第一子缓冲层。
在一实施例中，其中所述第一子缓冲层是一扩散障壁层。
在一实施例中，制造方法更包括：在所述缓冲层上形成所述硅层前，粗糙化所述缓冲层，以在所述缓冲层的表面上形成所述孔隙。
在一实施例中，制造方法更包括：粗糙化所述硅层的表面，以形成不平整表面作为再结晶成长空间；其中所述多晶硅层的部分硅材料形成至再结晶成长空间。
在一实施例中，其中粗糙化所述硅层的表面的步骤是蚀刻所述硅层的表面。
在一实施例中，制造方法更包括：在对所述硅层进行退火以形成所述多晶硅层前，提供一光罩；从所述光罩移转一图案至所述硅层，所述图案留有再结晶成长空间。
在一实施例中，其中在所述硅层上转移的所述图案的一部分作为沟道区，所述再结晶成长空间位在所述部分的侧边。
在一实施例中，其中所述退火是雷射退火。
在一实施例中，制造方法更包括：在对所述硅层进行退火以形成所述多晶硅层前，在所述硅层上形成一补捉层。
本申请提出一种低温多晶硅薄膜晶体管的制造方法，包括：如前述低温多晶硅薄膜的制造方法的步骤；在所述多晶硅层上形成一闸极绝缘层；以及在所述闸极绝缘层上形成一闸极；形成一源电极及一漏电极，所述源电极及所述漏电极电性连接所述多晶硅层。
综上所述，本申请的低温多晶硅薄膜及晶体管的制造方法，由于提供有 非晶硅再结晶成长空间，可舒缓非晶硅再结晶过程中晶体间的挤压，进而使多晶硅层表面的突起物尺寸明显变小。在较佳的情况下，突起物的高宽比都小于0.3，甚至小于0.2。因此，可改善低温多晶硅薄膜表面的突起问题。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1A至图1C为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。
图1D为本申请的低温多晶硅薄膜晶体管的制造方法的一实施例的示意图。
图2A至图2C为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。
图3A至图3D为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。
图4A至图4E为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描 述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
以下将参照相关图式，说明依本申请较佳实施例的内嵌式触控显示装置，其中相同的组件将以相同的参照符号加以说明。
图1A至图1C为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。如图1A所示，低温多晶硅薄膜的制造方法首先提供一衬底11，衬底11例如是玻璃衬底。然后，在衬底11上形成缓冲层12。缓冲层12的表面具有多个孔隙，孔隙可作为后续硅层再结晶的空间。
另外，在缓冲层12上形成硅层前，制造方法可更包括：粗糙化缓冲层12，以在缓冲层12的表面上形成孔隙，孔径例如小于20nm。粗糙化后的表面是不平整表面。
如图1B所示，在缓冲层12上形成一硅层13，此时大部分的硅层13是形成在缓冲层12的表面上，缓冲层12的孔隙仍有空间未被硅层13的材料填 入。硅层13可使用常规的方式沉积在缓冲层12，硅层13的材料是非晶硅。
如图1C所示，形成非晶硅的硅层13后，对硅层13进行退火以形成一多晶硅层14，并使多晶硅层14的部分硅材料140填入至孔隙120。
退火例如是雷射退火，退火制程温度在摄氏600度以下，利用此种制程方式所得多晶硅薄膜可称为低温多晶硅(low temperature poly-silicon，简称为LTPS)。相较于早期的多晶硅薄膜的制程温度高达摄氏1000度，低温多晶硅的制程温度较低，因而衬底材质较不受限制，例如衬底11可使用玻璃衬底。
多晶硅层14的制造是藉由雷射结晶化(laser crystalization)或准分子雷射退火(excimer laser annealing，简称ELA)等退火制程将原本的非晶硅层转变成多晶硅层。在退火过程中，硅层13中的非晶硅会熔融后再结晶并重新排列而成为多晶硅，因而形成多晶硅层14，且在多晶硅层14的表面会形成有数个突起物，突起物可能形成在多晶硅层14的上表面或下表面。
由于非晶硅再结晶时，部分的非晶硅会先作为再结晶的晶种，然后长晶成为较大的晶体，这些晶体不断地成长并相互结合形成更大的晶体。但是在结合过程中，由于晶体彼此应力相互作用，使得部分晶体被推挤到多晶硅层14表面上而形成突起物。
由于缓冲层12留有给再结晶突起物的孔隙120，因此，至少多晶硅层14的下表面的突起物140可填入至孔隙120。孔隙120也拘束突起物140的尺寸及形状，避免突起物过大。虽然在多晶硅层14上表面也会有突起物(图未示)产生，但因为部分的突起以改至多晶硅层14下表面，使得上表面的突起情况改善。习知制程的多晶硅层的突起物的高宽比约为0.45左右，与习知制程相较，多晶硅层14的突起物的高宽比可下降至0.3以下，甚至可降至0.2以下。虽然多晶硅层14的上下表面都有突起物，但突起物的高宽比都不致过大而影响组件性能。
图1D为本申请的低温多晶硅薄膜晶体管的制造方法的一实施例的示意图。如图1D所示，在如图1C衬底11上形成多晶硅层14后，进行后续制程以形成薄膜晶体管。低温多晶硅薄膜晶体管的制造方法包括：在多晶硅层14上形成一闸极绝缘层15；以及在闸极绝缘层15上形成一闸极16；形成一源 电极18及一漏电极19，源电极及所述漏电极电性连接所述多晶硅层。
举例来说，低温多晶硅薄膜晶体管包括多晶硅层14、闸极绝缘层15、闸极16、介电层17、源电极18以及漏电极19。多晶硅层14先经图案化，图案化后的多晶硅层14包括三区域分别作为源极141、漏极143以及沟道区142，沟道区142位于源极141与漏极143间。然后，在图案化后的多晶硅层14以及衬底11上方形成闸绝缘层15，闸极绝缘层15材质例如是氧化硅或是氮化硅。然后，在闸极绝缘层15以及通道区142上方形成闸极16。接着，形成一层介电层17于闸极16以与门极绝缘层15上，并图案化介电层17与闸极绝缘层15以形成通孔，通孔会露出源极141与漏极143。然后，形成源电极18与漏电极19在介电层17表面以及通孔，源电极18穿过通孔接触源极141，漏电极19穿过通孔接触漏极143，因此，源电极18及漏电极19分别电性连接多晶硅层14的源极141与漏极143。
另外，低温多晶硅薄膜晶体管不限用于液晶显示面板或有机发光二极管面板。
另外，衬底11可由玻璃、石英、或类似的材质来构成。缓冲层12可以由SiNx、SiOx或SiOxNy等材质所构成。
图2A至图2C为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。如图2A所示，低温多晶硅薄膜的制造方法首先提供一衬底21，衬底21例如是玻璃衬底。然后，在衬底21上形成缓冲层22。缓冲层22可以是多层结构，在本实施例是以二层为例，但层数不限于二层也可设有更多层。
缓冲层22包括一第一子缓冲层221以及一第二子缓冲层222，形成缓冲层22的步骤包括：在衬底21上形成第一子缓冲层221，然后在第一子缓冲层221上形成第二子缓冲层222。
这些子缓冲层可以有不同的细致度，缓冲层22中最上层的子缓冲层可以有较低的细致度，藉以在最上层的子缓冲层的上表面形成孔隙以作为硅层再结晶所需的空间。例如第二子缓冲层222的细致度低于第一子缓冲层221，因此，第二子缓冲层222的上表面具有多个孔隙220，孔隙220可作为后续硅层再结晶的空间。
另外，在缓冲层上形成硅层前，制造方法可以粗糙化第二子缓冲层222，以在所述缓冲层的表面上形成孔隙220，孔径例如小于20nm。粗糙化后的表面是不平整表面。
粗糙化可包括蚀刻，蚀刻可以是干蚀刻或湿蚀刻，干蚀刻的制程参数包括频率、气压、离子密度、蚀刻时间等等，湿蚀刻的制程参数包括溶液浓度、蚀刻时间、反应温度、溶液的搅拌等等。藉由调整前述蚀刻参数，可以使蚀刻后表面有不同的粗糙度。
粗糙化的过程可以不需进行光罩图案转移，在缓冲层上不需设置光阻，也不需要光罩及曝光。
第一子缓冲层是一扩散障壁层，由于退火过程中，衬底21中的杂质会扩散至其他层，扩散障壁层可挡下至少部分的杂质，避免过多的杂质扩散到硅层。第一子缓冲层相较于第二子缓冲层有较高的细致度，藉以有较佳的扩散障壁效果。
另外，在形成第二子缓冲层222前，制造方法可以粗糙化第一子缓冲层221，以有较佳的扩散障壁效果。粗糙化后的表面是不平整表面。
如图2B所示，在缓冲层22的第二子缓冲层222上形成一硅层23，此时大部分的硅层23是形成在第二子缓冲层222的上表面上，缓冲层12的孔隙仍有空间未被硅层23的材料填入。硅层23可使用常规的方式沉积在第二子缓冲层222上，硅层23的材料是非晶硅。
如图2C所示，形成非晶硅的硅层23后，对硅层23进行退火以形成一多晶硅层24，并使多晶硅层24的部分硅材料240填入至第二子缓冲层222的孔隙220。由于多晶硅层24的形成方式及结构与前述多晶硅层14类似，故此不再坠述。
形成多晶硅层24后，也可如图1D再进行后续制程以形成薄膜晶体管。由于晶体管的制造方法可参考图1D的相关说明，故此不再坠述。
另外，衬底21可由玻璃、石英、或类似的材质来构成。缓冲层22的子层可以由SiNx、SiOx或SiOxNy等材质所构成。
另外，在图1A及图2A中，低温多晶硅薄膜的制造方法可更包括：粗糙 化硅层13、23的表面，以形成不平整表面作为再结晶成长空间，举例来说，粗糙化后的表面的表面粗糙度介于5nm与30nm间。多晶硅层14、24的部分硅材料形成至再结晶成长空间。粗糙化硅层13、23的表面例如是蚀刻硅层13、23的表面。藉此，由于提供有更多的再结晶成长空间，可舒缓再结晶过程中晶体间的挤压，进而使多晶硅层14、24表面的突起物尺寸明显变小。
粗糙化可包括蚀刻，蚀刻可以是干蚀刻或湿蚀刻，干蚀刻的制程参数包括频率、气压、离子密度、蚀刻时间等等，湿蚀刻的制程参数包括溶液浓度、蚀刻时间、反应温度、溶液的搅拌等等。藉由调整前述蚀刻参数，可以使蚀刻后表面有不同的粗糙度。
粗糙化的过程可以不需进行光罩图案转移，在硅层上不需设置光阻，也不需要光罩及曝光。
另外，在图1B及图2B中，低温多晶硅薄膜的制造方法可制造方法更包括：在对所述硅层进行退火以形成所述多晶硅层前，提供一光罩；从所述光罩移转一图案至所述硅层，所述图案留有再结晶成长空间。所述再结晶成长空间位在所述图案的侧边。藉此，由于提供有更多的再结晶成长空间，可舒缓再结晶过程中晶体间的挤压，进而使多晶硅层14、24表面的突起物尺寸明显变小。
硅层上的图案经光罩图案转移制程，举例来说，未图案化的硅层上先沉积一整层光阻，然后光阻经光罩曝光，光罩图案会先转移到光阻上。然后，利用蚀刻制程来蚀刻未被光阻保护的硅层，因而光罩图案便转移到硅层。
另外，在所述硅层上转移的所述图案的一部分作为沟道区，再结晶成长空间是留在所述部分的侧边。举例来说，光罩的图案用来定义硅层上的源极、漏极、沟道区以及再结晶成长空间的位置，光罩的图案移转到硅层后，若从衬底上方俯视硅层，沟道区平面地位于源极与漏极间，再结晶成长空间位于硅层的沟道区的侧边，甚至再结晶成长空间还可同时位于硅层的源极、漏极的侧边。
另外，为了留有更多的再结晶成长空间，在光罩图案转移制程中，也可藉由蚀刻对侧边表面进行粗糙化处理，以形成更多不平整表面作为再结晶成 长空间，举例来说，粗糙化后的表面的表面粗糙度介于5nm与30nm间。
另外，在图1B及图2B中，低温多晶硅薄膜的制造方法可更包括：在对硅层13、23进行退火以形成多晶硅层14、24前，在硅层13、23上形成一补捉层，由于退火时衬底11、21的杂质会扩散，设置补捉层可用来捕捉这些杂质，避免杂质累积在多晶硅层14、24。补捉层的材料例如是SiNx、SiOx或SiOxNy等材质。举例来说，补捉层可藉由调整制程参数来达成，例如低密度的SiOx膜层可藉由调整反应物SiH4与N2O的比例，或是反应物TEOS与O2或O3的比例而形成。通常SiH4所占的比例愈大时，SiOx膜层的多孔性质愈加增；如果气所占的比例愈小，SiOx膜层的密度愈小。
综上所述，低温多晶硅薄膜及晶体管的制造方法中，由于提供有非晶硅再结晶成长空间，可舒缓非晶硅再结晶过程中晶体间的挤压，进而使多晶硅层表面的突起物尺寸明显变小。在较佳的情况下，突起物的高宽比都小于0.3，甚至小于0.2。
此外，由于多晶硅层表面突起物的高宽比都小于0.3，所以可以使组件的组件特性较为一致。采用这样的低温多晶硅薄膜晶体管作为显示面板的开关或驱动器时，可以使显示面板色彩均匀度较佳。
图3A至图3D为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。如图3A所示，制造方法提供一衬底31，衬底31例如是玻璃衬底。然后，在衬底31上形成缓冲层32。
如图3B所示，制造方法包括粗糙化硅层33的表面，以形成不平整表面作为再结晶成长空间，举例来说，粗糙化后的表面的表面粗糙度介于5nm与30nm间。粗糙化硅层33的表面例如是蚀刻硅层33的表面。硅层33可使用常规的方式沉积在缓冲层32，硅层33的材料是非晶硅。
如图3C所示，制造方法对硅层33进行退火以形成一多晶硅层34，并使多晶硅层34的部分硅材料形成至再结晶成长空间。
退火例如是雷射退火，退火及非晶硅再结晶的相关说明可参考图1C的相关内容，故此不再坠述。
由于硅层33本身留有给再结晶突起物的再结晶成长空间，因此，至少多 晶硅层34的上表面的突起物可填入至再结晶成长空间。习知制程的多晶硅层的突起物的高宽比约为0.45左右，与习知制程相较，多晶硅层34的突起物的高宽比可下降至0.3以下，甚至可降至0.2以下，减轻突起物对组件性能的影响。
形成多晶硅层34后，也可如图1D再进行后续制程以形成薄膜晶体管。由于晶体管的制造方法可参考图1D的相关说明，故此不再坠述。
另外，缓冲层32也可采用前述图1A及图2A的实施方式。
举例来说，缓冲层32可采用前述图1A的实施方式，缓冲层32的表面具有多个孔隙，孔隙可作为后续硅层再结晶的空间，经退火的多晶硅层的部分硅材料填入至孔隙。例如在缓冲层32上形成硅层33前，制造方法可更包括：粗糙化缓冲层32，以在缓冲层32的表面上形成孔隙。由于相关实施方式可参考前述图1A的相关说明，故此不再坠述。
缓冲层32也可采用前述图2A的实施方式。形成缓冲层32的步骤包括：在衬底31上形成一第一子缓冲层；在第一子缓冲层上形成一第二子缓冲层，第二子缓冲层的细致度低于所述第一子缓冲层。第一子缓冲层可以是一扩散障壁层。由于相关实施方式可参考前述图2A的相关说明，故此不再坠述。
另外，在图3B中，低温多晶硅薄膜的制造方法可制造方法更包括：在对所述硅层进行退火以形成所述多晶硅层前，提供一光罩；从所述光罩移转一图案至所述硅层，所述图案留有再结晶成长空间。所述再结晶成长空间位在所述图案的侧边。藉此，由于提供有更多的再结晶成长空间，可舒缓再结晶过程中晶体间的挤压，进而使多晶硅层34表面的突起物尺寸明显变小。
另外，在图3B中，低温多晶硅薄膜的制造方法可更包括：在对硅层33进行退火以形成多晶硅层34前，在硅层33上形成一补捉层，由于退火时衬底31的杂质会扩散，设置补捉层可用来捕捉这些杂质，避免杂质累积在多晶硅层34。
综上所述，低温多晶硅薄膜及晶体管的制造方法中，由于提供有非晶硅再结晶成长空间，可舒缓非晶硅再结晶过程中晶体间的挤压，进而使多晶硅层表面的突起物尺寸明显变小。在较佳的情况下，突起物的高宽比都小于0.3， 甚至小于0.2。
图4A至图4E为本申请的低温多晶硅薄膜的制造方法的一实施例的示意图。如图4A所示，制造方法提供一衬底41，衬底41例如是玻璃衬底。然后，在衬底41上形成缓冲层42。
图4B是低温多晶硅薄膜的侧视示意图，图4C是图4B的俯视示意图。如图4B所示，制造方法包括在缓冲层42上形成一硅层43，硅层43可使用常规的方式沉积在缓冲层42，硅层43的材料是非晶硅。如图4C所示，制造方法包括提供一光罩；从所述光罩移转一图案至硅层43，图案留有再结晶成长空间，再结晶成长空间位在图案的侧边。若从衬底41上方俯视硅层43，因再结晶成长空间位在硅层43上图案的侧边，会看到缓冲层42。缓冲层42上方和硅层43上图案侧边的凹入形成再结晶成长空间。
举例来说，光罩的图案用来定义硅层43上的源极、漏极、沟道区以及再结晶成长空间的位置，光罩的图案移转到硅层43后，若从衬底41上方俯视硅层43，沟道区平面地位于源极与漏极间，再结晶成长空间位于硅层43的沟道区的侧边，甚至再结晶成长空间还可同时位于硅层43的源极、漏极的侧边。
另外，硅层43的表面可粗糙化，以形成不平整表面作为再结晶成长空间。粗糙化硅层43的表面例如是蚀刻硅层43的表面，举例来说，粗糙化后的表面的表面粗糙度介于5nm与30nm间。藉此，硅层43的上表面和侧表面都有留有再结晶成长空间。
图4D是低温多晶硅薄膜的侧视示意图，图4D是图4C的俯视示意图。如图4D所示，制造方法对硅层43进行退火以形成一多晶硅层44，并使多晶硅层44的部分硅材料形成至再结晶成长空间。藉此，由于提供有更多的再结晶成长空间，可舒缓再结晶过程中晶体间的挤压，进而使多晶硅层44表面的突起物尺寸明显变小。
退火例如是雷射退火，退火及非晶硅再结晶的相关说明可参考图1C或图2C的相关内容，故此不再坠述。
由于硅层43本身留有给再结晶突起物的再结晶成长空间，因此，如图4E所示，至少多晶硅层44的上表面的突起物可填入至再结晶成长空间。习知制 程的多晶硅层的突起物的高宽比约为0.45左右，与习知制程相较，多晶硅层44的突起物的高宽比可下降至0.3以下，甚至可降至0.2以下，减轻突起物对组件性能的影响。
形成多晶硅层44后，也可如图1D再进行后续制程以形成薄膜晶体管。由于晶体管的制造方法可参考图1D的相关说明，故此不再坠述。
另外，缓冲层42也可采用前述图1A及图2A的实施方式。
举例来说，缓冲层42可采用前述图1A的实施方式，缓冲层42的表面具有多个孔隙，孔隙可作为后续硅层再结晶的空间，经退火的多晶硅层的部分硅材料填入至孔隙。例如在缓冲层42上形成硅层43前，制造方法可更包括：粗糙化缓冲层42，以在缓冲层42的表面上形成孔隙，孔径例如小于20nm。由于相关实施方式可参考前述图1A的相关说明，故此不再坠述。
缓冲层42也可采用前述图2A的实施方式。形成缓冲层42的步骤包括：在衬底41上形成一第一子缓冲层；在第一子缓冲层上形成一第二子缓冲层，第二子缓冲层的细致度低于所述第一子缓冲层。第一子缓冲层可以是一扩散障壁层。由于相关实施方式可参考前述图2A的相关说明，故此不再坠述。
综上所述，低温多晶硅薄膜及晶体管的制造方法中，由于提供有非晶硅再结晶成长空间，可舒缓非晶硅再结晶过程中晶体间的挤压，进而使多晶硅层表面的突起物尺寸明显变小。在较佳的情况下，突起物的高宽比都小于0.3，甚至小于0.2。
此外，由于多晶硅层表面突起物的高宽比都小于0.3，所以可以使组件的组件特性较为一致。采用这样的低温多晶硅薄膜晶体管作为显示面板的开关或驱动器时，可以使显示面板色彩均匀度较佳。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种低温多晶硅薄膜的制造方法，包括：
    在一衬底上形成一缓冲层，所述缓冲层的表面具有多个孔隙；
    在所述缓冲层上形成一硅层；以及
    对所述硅层进行退火以形成一多晶硅层，并使所述多晶硅层的部分硅材料填入至所述孔隙。
  2. 如权利要求1所述的制造方法，其中在所述衬底上形成所述缓冲层的步骤包括：
    在所述衬底上形成一第一子缓冲层；
    在所述第一子缓冲层上形成一第二子缓冲层，所述第二子缓冲层的细致度低于所述第一子缓冲层。
  3. 如权利要求2所述的制造方法，其中所述第一子缓冲层是一扩散障壁层。
  4. 如权利要求1所述的制造方法，更包括：
    在所述缓冲层上形成所述硅层前，粗糙化所述缓冲层，以在所述缓冲层的表面上形成所述孔隙。
  5. 如权利要求1所述的制造方法，更包括：
    粗糙化所述硅层的表面，以形成不平整表面作为再结晶成长空间；
    其中所述多晶硅层的部分硅材料形成至再结晶成长空间。
  6. 如权利要求5所述的制造方法，其中粗糙化所述硅层的表面的步骤是蚀刻所述硅层的表面。
  7. 如权利要求1所述的制造方法，更包括：
    在对所述硅层进行退火以形成所述多晶硅层前，提供一光罩；
    从所述光罩移转一图案至所述硅层，所述图案留有再结晶成长空间。
  8. 如权利要求7所述的制造方法，其中在所述硅层上转移的所述图案的一部分作为沟道区，所述再结晶成长空间位在所述部分的侧边。
  9. 如权利要求1所述的制造方法，其中所述退火是雷射退火。
  10. 一种低温多晶硅薄膜的制造方法，包括：
    在一衬底上形成一第一子缓冲层，所述第一子缓冲层是一扩散障壁层；
    在所述第一子缓冲层上形成一第二子缓冲层，所述第二子缓冲层的细致 度低于所述第一子缓冲层；
    粗糙化所述第二子缓冲层，以在所述第二子缓冲层的表面上形成多个孔隙；
    在所述第二子缓冲层上形成一硅层；
    蚀刻所述硅层的表面以粗糙化所述硅层的表面，以形成不平整表面作为再结晶成长空间；以及
    对所述硅层进行雷射退火以形成一多晶硅层，并使所述多晶硅层的部分硅材料填入至所述孔隙及所述再结晶成长空间。
  11. 如权利要求10所述的制造方法，更包括
    在对所述硅层进行雷射退火以形成所述多晶硅层前，提供一光罩；以及
    从所述光罩移转一图案至所述硅层，所述图案留有另一再结晶成长空间，其中在所述硅层上转移的所述图案的一部分作为沟道区，所述另一再结晶成长空间位在所述部分的侧边；
    其中对所述硅层进行雷射退火以形成所述多晶硅层的步骤，使所述多晶硅层的部分硅材料填入至所述孔隙、所述再结晶成长空间及所述另一再结晶成长空间。
  12. 一种低温多晶硅薄膜晶体管的制造方法，包括：
    在一衬底上形成一缓冲层，所述缓冲层的表面具有多个孔隙；
    在所述缓冲层上形成一硅层；
    对所述硅层进行退火以形成一多晶硅层，并使所述多晶硅层的部分硅材料填入至所述孔隙；
    在所述多晶硅层上形成一闸极绝缘层；以及
    在所述闸极绝缘层上形成一闸极；
    形成一源电极及一漏电极，所述源电极及所述漏电极电性连接所述多晶硅层。
  13. 如权利要求12所述的制造方法，其中在所述衬底上形成所述缓冲层的步骤包括：
    在所述衬底上形成一第一子缓冲层；
    在所述第一子缓冲层上形成一第二子缓冲层，所述第二子缓冲层的细致度低于所述第一子缓冲层。
  14. 如权利要求13所述的制造方法，其中所述第一子缓冲层是一扩散障壁层。
  15. 如权利要求12所述的制造方法，更包括：
    在所述缓冲层上形成所述硅层前，粗糙化所述缓冲层，以在所述缓冲层的表面上形成所述孔隙。
  16. 如权利要求12所述的制造方法，更包括：
    粗糙化所述硅层的表面，以形成不平整表面作为再结晶成长空间；
    其中所述多晶硅层的部分硅材料形成至再结晶成长空间。
  17. 如权利要求16所述的制造方法，其中粗糙化所述硅层的表面的步骤是蚀刻所述硅层的表面。
  18. 如权利要求12所述的制造方法，更包括：
    在对所述硅层进行退火以形成所述多晶硅层前，提供一光罩；
    从所述光罩移转一图案至所述硅层，所述图案留有再结晶成长空间。
  19. 如权利要求18所述的制造方法，其中在所述硅层上转移的所述图案的一部分作为沟道区，所述再结晶成长空间位在所述部分的侧边。
  20. 如权利要求12所述的制造方法，其中所述退火是雷射退火。
PCT/CN2017/110124 2017-10-12 2017-11-09 低温多晶硅薄膜及晶体管的制造方法 WO2019071694A1 (zh)

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CN107946173B (zh) 2017-10-12 2019-12-27 惠科股份有限公司 低温多晶硅薄膜及晶体管的制造方法
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KR20220060069A (ko) * 2020-11-03 2022-05-11 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법

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