WO2014139249A1 - 移位寄存器、显示装置、栅极驱动电路及驱动方法 - Google Patents

移位寄存器、显示装置、栅极驱动电路及驱动方法 Download PDF

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Publication number
WO2014139249A1
WO2014139249A1 PCT/CN2013/078443 CN2013078443W WO2014139249A1 WO 2014139249 A1 WO2014139249 A1 WO 2014139249A1 CN 2013078443 W CN2013078443 W CN 2013078443W WO 2014139249 A1 WO2014139249 A1 WO 2014139249A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
shift register
gate
pull
Prior art date
Application number
PCT/CN2013/078443
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English (en)
French (fr)
Inventor
吴博
祁小敬
周全国
聂磊森
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP13854214.7A priority Critical patent/EP2975604B1/en
Priority to JP2015561904A priority patent/JP6328153B2/ja
Priority to US14/360,879 priority patent/US9240781B2/en
Priority to KR1020147017047A priority patent/KR101580422B1/ko
Publication of WO2014139249A1 publication Critical patent/WO2014139249A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/04—Shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a shift register, a display device, a gate driving circuit and a driving method. Background technique
  • the basic principle of realizing one frame of image display is to sequentially output the signals required for each row of pixels from top to bottom by data driving, and the gate driving sequentially goes from top to bottom for each pixel row. Enter a square wave of a certain width to strobe.
  • Today's manufacturing method is to bond the gate drive IC and the data drive IC to the glass panel by a COG (chip on glas s) process.
  • COG chip on glas s
  • the gate driving circuit is fabricated on the glass panel by the array substrate process without increasing the process and cost of the existing process, and the basic gate driving circuit shift register unit circuit
  • the schematic diagram is shown in Figure 1, but the circuit has a long duty cycle, the voltage threshold has a drift problem, and the control signal cannot control the circuit 4.
  • the technical problem to be solved by the present invention is: How to provide a shift register, a display device, a gate driving circuit and a driving method to reduce the working period of the circuit, improve the voltage threshold drift problem, and better realize the control signal to the circuit control.
  • a shift register includes a multi-stage shift register circuit, and an Nth-stage shift register circuit of the multi-stage shift register circuit includes :
  • a reset circuit that resets the Nth stage shift register circuit after outputting a high level at the output end; a holding circuit that maintains an output potential of the Nth stage shift register circuit after the reset of the Nth stage shift register circuit;
  • control end and the input end of the precharge circuit are connected to the output end of the shift register circuit of the upper stage, and the output end is connected to the input end of the reset circuit;
  • the input end of the pull-up circuit is connected to the first control signal terminal
  • the control end of the reset circuit is connected to the output end of the shift register circuit of the next stage, and the output end is grounded;
  • the holding circuit is connected to an output end of the pre-charging circuit, an input end of the reset circuit, a control end of the pull-up circuit, and an output end of the pull-up circuit, and the first control end and the first a control signal terminal is connected, and the second control end is connected to the second control signal terminal;
  • the holding circuit is provided with an eighth transistor, a gate of the eighth transistor is connected to the first control signal terminal, and a source and a drain are connected to each other.
  • the holding circuit includes a first holding circuit and a second holding circuit
  • the eighth transistor is disposed in the first holding circuit.
  • the first holding circuit includes a fifth transistor and an eighth transistor, a gate of the eighth transistor is a first control end of the holding circuit, and a source and a drain of the eighth transistor are a source of the fifth transistor is connected, a gate of the fifth transistor is connected to a control terminal of the pull-up circuit, and a drain of the fifth transistor is grounded;
  • the second holding circuit includes a fourth transistor, a sixth transistor, and a seventh transistor, a gate of the fourth transistor being a second control terminal of the holding circuit, a source of the fourth transistor, and a sixth transistor
  • the source and the output of the pull-up circuit are connected, the drain of the fourth transistor is grounded, the gate of the sixth transistor is connected to the gate of the seventh transistor, and the drain of the sixth transistor Grounding, a source of the seventh transistor is connected to an output end of the precharge circuit, an input end of the reset circuit, a control end of the pull-up circuit, and a drain of the seventh transistor is grounded;
  • the first holding circuit and the second holding circuit are connected by a pull-down node, the pull-down node is connected to a source and a drain of the eighth transistor, a source of the fifth transistor, a gate of the sixth transistor, and a gate
  • the gate of the seventh transistor is described.
  • the first holding circuit includes a fifth transistor and an eighth transistor, a control terminal of the eighth transistor is a first control terminal of the holding circuit, a source and a drain of the eighth transistor are connected to a source of the fifth transistor, and a gate of the fifth transistor is a control terminal of the pull-up circuit is connected, a drain of the fifth transistor is grounded;
  • the second hold circuit includes a fourth transistor, a sixth transistor, and a seventh transistor, and a gate of the fourth transistor is the holding circuit a second control terminal, a source of the fourth transistor is connected to a source of the seventh transistor and an output of the pull-up circuit, a drain of the fourth transistor is grounded, and a gate of the sixth transistor Connected to a gate of the seventh transistor, a source of the sixth transistor is connected to an output end of the precharge circuit, an input end of the reset circuit, and a control end of the pull-up circuit, a drain of the sixth transistor is connected to a source of the seventh transistor, and a drain of the seventh transistor is grounded;
  • the first holding circuit and the second holding circuit are connected by a pull-down node, the pull-down node is connected to a source and a drain of the eighth transistor, a source of the fifth transistor, a gate of the sixth transistor, and a gate
  • the gate of the seventh transistor is described.
  • the pre-charging circuit comprises a first transistor, the gate of the first transistor is a control terminal, the source is an input terminal, and the drain is an output terminal.
  • the reset circuit includes a second transistor, the gate of the second transistor is a control terminal, the source is an input terminal, and the drain is an output terminal.
  • the pull-up circuit includes a third transistor and a capacitor, the gate of the third transistor is a control terminal, the source is an input terminal, and the drain is an output terminal, and the gate and the drain of the third transistor are respectively The two ends of the capacitor are connected.
  • a gate driving circuit comprising the shift register.
  • a display device comprising the gate drive circuit.
  • a gate driving method comprising the steps of:
  • the S1 precharge circuit charges the pull-up circuit
  • the S2 pull-up circuit pulls up the potential of the shift register circuit, and the shift register circuit outputs a high level
  • the S3 reset circuit resets the shift register circuit;
  • the S4 hold circuit maintains the output potential of the shift register circuit after the shift register circuit is reset;
  • the equivalent capacitance of the eighth transistor in the holding circuit changes with the turning on or off of the eighth transistor, and the equivalent capacitance when the eighth transistor is turned on is greater than the equivalent capacitance when the eighth transistor is turned off.
  • the shift register, the display device, the gate driving circuit and the driving method of the embodiment of the invention not only realize shift register, but also reduce the working period of the circuit, improve the voltage threshold drift problem, and short-circuit the transistor through the source and drain
  • the control signal is controlled to the pull-down node, so that the pull-down node rises rapidly when the first control signal is at a high level, and the decrease amplitude decreases when the first control signal is at a low level, which can better realize the control signal to the circuit. control.
  • 1 is a schematic circuit diagram of a prior art G0A circuit shift register unit
  • FIG. 2 is a schematic diagram of a shift register circuit in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of a shift register unit according to Embodiment 1 of the present invention.
  • FIG. 4 is a timing waveform diagram of a shift register unit circuit according to an embodiment of the present invention.
  • FIG. 5 is a timing waveform diagram of a shift register circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic circuit diagram of a shift register unit of Embodiment 2 of the present invention.
  • Fig. 7 is a flow chart showing the gate driving method of the embodiment of the present invention. detailed description
  • a shift register of an embodiment of the present invention includes a multi-stage shift register circuit.
  • SRO-SRn is each stage of the n-stage shift register circuit
  • GLO-GLn is the output of the n-stage shift register circuit
  • STV is the start signal
  • each stage shift register is above.
  • the output of the following stage is used as the STV start signal.
  • the output of the following stage acts as the reset signal RST, and operates under the dual clocks CK and CKB to realize the top-down gate drive scan output.
  • the Nth stage shift register circuit of the multi-stage shift register circuit includes: a precharge circuit 1 for precharging the pull-up circuit;
  • the pull-up circuit 2 is configured to enable the output terminal OUTPUT to output a high level after the pre-charging is completed; the reset circuit 3 resets the Nth-stage shift register circuit after the output terminal OUTPUT outputs a high level;
  • N is a natural number greater than one.
  • the control terminal and the input terminal of the precharge circuit 1 are connected to the output terminal N-1 _0UT of the shift register circuit of the previous stage, and the output terminal is connected to the input terminal of the reset circuit 3;
  • the input end of the pull-up circuit 2 is connected to the first control signal terminal CK;
  • the control terminal of the reset circuit 3 is connected to the output terminal N+1 _0UT of the next-stage shift register circuit, and the output terminal is grounded;
  • the holding circuit is connected to the output end of the pre-charging circuit 1, the input end of the reset circuit 3, the control end of the pull-up circuit 2, and the output end of the pull-up circuit 2, and the first control terminal and the first control signal terminal CK Connected, the second control terminal is connected to the second control signal terminal CKB; the holding circuit is provided with an eighth transistor M8, and the gate of the eighth transistor M8 is connected to the first control signal terminal, the source and the drain Connected to each other.
  • the holding circuit includes a first holding circuit 4A and a second holding circuit 4B, and the eighth transistor M8 is disposed in the first holding circuit 4A.
  • the first holding circuit 4A includes a fifth transistor M5 and an eighth transistor M8.
  • the control terminal of the eighth transistor M8 is the first control terminal of the holding circuit, the source and the drain of the eighth transistor M8 and the source of the fifth transistor M5. Connected, the gate of the fifth transistor M5 is connected to the control terminal of the pull-up circuit 2, and the drain of the fifth transistor M5 is grounded;
  • the second holding circuit 4B includes a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the fourth transistor M4 is the second control terminal of the holding circuit, the source of the fourth transistor M4 and the sixth transistor M6.
  • the source is connected to the output of the pull-up circuit 2, the drain of the fourth transistor M4 is grounded, the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7, and the drain of the sixth transistor M6 is grounded, the seventh
  • the source of the transistor M7 is connected to the output terminal of the precharge circuit 1, the input terminal of the reset circuit 3, and the control terminal of the pull-up circuit 2, and the seventh crystal
  • the drain of the body tube M7 is grounded;
  • the first hold circuit 4A and the second hold circuit 4B are connected by a pull-down node PD, the pull-down node PD is connected to the source and drain of the eighth transistor M8, the source of the fifth transistor M5, the gate of the sixth transistor M6, and the seventh The gate of transistor M7.
  • PU is a pull-up node
  • PD is a pull-down node
  • a signal input by the first control signal terminal CK and the second control signal terminal CKB is a dual clock signal of a differential input.
  • the precharge circuit 1 includes a first transistor M1, the gate of the first transistor M1 is a control terminal, the source is an input terminal, and the drain is an output terminal.
  • the reset circuit 3 includes a second transistor M2 whose gate is a control terminal, the source is an input terminal, and the drain is an output terminal.
  • the pull-up circuit 2 includes a third transistor M3 and a capacitor C1.
  • the gate of the third transistor M3 is a control terminal, the source is an input terminal, and the drain is an output terminal.
  • the gate and the drain of the third transistor M3 are respectively connected to the two ends of the capacitor C1. connection.
  • the above-mentioned transistors are thin film transistors.
  • the shift register of Embodiment 1 of the present invention in the first clock signal, the first control signal terminal CK is outputted to a low level, and the second control signal terminal CKB is outputted to a high level.
  • the output of the previous stage shift register circuit is N-1 _0UT is high level, and the output of the next stage shift register circuit is N+1 -0UT is low level.
  • Transistors M2, M6, M7, M8 are turned off, and transistors Ml, M4 are turned on.
  • the upper shift register circuit output N-1 _0UT precharges the gate of transistor M3 through transistor M1, causing the PU point voltage of the pull-up node to rise.
  • the second control signal terminal CK is at a low level, and the pull-up node PU pulls down the pull-down node PD, so that the PD voltage of the pull-down node is low, and the transistors M6 and M7 are all turned off, so that the gate pull-up node PU of the transistor M3 is kept. In the pre-charg ing state, the output OUTPUT voltage remains low.
  • the first control signal terminal CK is outputted to a high level
  • the second control signal terminal CKB is outputted to a low level
  • the upper stage shift register circuit outputs N-1 _0UT is low
  • the next stage shift register output N+1 _0UT is low.
  • the transistors M1, M2, M4 are turned off. Pull-up node PU through capacitor
  • the source and drain of the transistor M8 are short-circuited, which is equivalent to the capacitance, so that the signal of the pull-down node PD point potential is coupled to the first control signal terminal CK.
  • the pull-up node PU is at a high level
  • the transistor M5 is turned on
  • the transistors M8 and M5 are The aspect ratio causes the pull-down node PD potential to be low
  • the equivalent capacitance of transistor M8 at this stage is the equivalent capacitance when the transistor is turned on.
  • the pull-up node PU maintains a high level
  • the output terminal OUTPUT maintains an output high level, and shifts the N-1 -OUT signal of the shift register circuit of the previous stage.
  • the output of the previous stage shift register circuit is N-1 - 0UT is low level, the first control signal terminal CK is low level, and the second control signal terminal CKB is high level, the next stage
  • the shift register circuit outputs N+1 _0UT to a high level.
  • Transistor M1 is turned off and transistors M2 and M4 are turned on. Pull-up node PU and output OUTPUT are set low.
  • the output of the previous stage shift register circuit is N-1 - 0UT is low level, and the output of the next stage shift register circuit is N+1 _0UT is low level, and the first control signal terminal CK is high.
  • Level, the second control signal terminal CKB is at a low level.
  • the transistors Ml, M2, and M4 are turned off, the pull-up node PU is low, and the transistors M3 and M5 are turned off.
  • the source and drain of the transistor M8 are short-circuited, which is equivalent to the capacitance.
  • the first control signal terminal CK is at a high level
  • the pull-down node PD is coupled to the high level of the first control signal terminal CK through the transistor M8, so that the transistors M6 and M7 are turned on.
  • the pull node PU and the output OUTPUT are pulled low.
  • the equivalent capacitance of the transistor M8 is the equivalent capacitance when the transistor is turned on, and the capacitance is larger than the equivalent capacitance when the transistor is turned off.
  • the output of the previous stage shift register circuit is N-1 - 0UT is low level
  • the output of the next stage shift register circuit is N+1 _0UT is low level
  • the first control signal terminal CK is low.
  • Level the second control signal terminal CKB is at a high level.
  • the transistors M1 and M2 are turned off, the pull-up node PU is low, and the transistors M3 and M5 are turned off.
  • Transistor M4 is turned on and the output OUTPUT is pulled low.
  • the source and drain of the transistor M8 are short-circuited, equivalent to the capacitor, the first control signal terminal CK is at a low level, and the pull-down node PD is coupled to the low level of the first control signal terminal CK through the transistor M8.
  • the equivalent capacitance of the transistor M8 at this stage The size is the equivalent capacitance when the transistor is turned off, and the capacitance is smaller than the equivalent capacitance when the transistor is turned on.
  • the timing waveform diagram of the shift register circuit of the embodiment of the present invention is shown in FIG. 5, in which STV is the start signal, and GLO-GLn is the output end of the n-stage shift register circuit.
  • the shift register of the embodiment of the invention reduces the working period of the circuit and improves the voltage threshold drift problem.
  • the control signal is controlled to the pull-down node by the short-circuiting of the source and drain, so that the pull-down node is high in the first control signal. When the level is fast, the falling amplitude is reduced when the first control signal is low, and the control signal can be better controlled by the circuit.
  • a shift register of an embodiment of the present invention is as shown in FIG. 6, and has the same features as Embodiment 1, except that the first holding circuit 4A includes a fifth transistor M5 and an eighth transistor M8, and an eighth transistor M8.
  • the control terminal is the first control terminal of the holding circuit, the source and the drain of the eighth transistor M8 are connected to the source of the fifth transistor M5, and the gate of the fifth transistor M5 is connected to the control terminal of the pull-up circuit.
  • the drain of the fifth transistor M5 is grounded;
  • the second holding circuit 4B includes a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the fourth transistor M4 is the second control terminal of the holding circuit, and the source of the fourth transistor M4 and the seventh transistor M7.
  • the source is connected to the output of the pull-up circuit 2, the drain of the fourth transistor M4 is grounded, the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7, and the source of the sixth transistor M6 is connected to the precharge circuit.
  • the output terminal of the first terminal, the input terminal of the reset circuit 3, and the control terminal of the pull-up circuit 2 are connected, the drain of the sixth transistor M6 is connected to the source of the seventh transistor M7, and the drain of the seventh transistor M7 is grounded;
  • the first holding circuit 4A and the second holding circuit 4B are connected by a pull-down node PD, and the pull-down node PD is connected to the source and the drain of the eighth transistor, the source of the fifth transistor, the gate of the sixth transistor, and the gate of the seventh transistor. pole.
  • the effect of the capacitive coupling is achieved by the short-circuiting of the source and the drain.
  • the solution of the embodiment of the present invention can be more than four types.
  • the two-way scanning of the GOA can be realized by the design of the pre-charging circuit P r e-cha rgi ng and the reset circuit Reset module.
  • the pull-up node PU and the output terminal OUTPUT to be pulled down to the output of the previous stage or the next stage shift register, or the four clock circuits using the technique of the present invention, as long as the source-drain short circuit of the present invention is used
  • the technical solution of the effect of the transistor to achieve capacitive coupling is within the scope of the present invention.
  • a gate driving circuit of an embodiment of the invention comprising the shift register.
  • a display device according to an embodiment of the present invention, the display device including the gate drive Dynamic circuit.
  • FIG. 7 shows a flow chart of a gate driving method of an exemplary embodiment of the present invention. As shown in Figure 7, the operation of the method is as follows:
  • step S1 the precharge circuit charges the pull-up circuit
  • step S2 the pull-up circuit pulls up the potential of the shift register circuit, and the shift register circuit outputs a high level
  • step S3 the reset circuit resets the shift register circuit
  • step S4 the hold circuit holds the output potential of the shift register circuit after the shift register circuit is reset.
  • step S4 the equivalent capacitance of the eighth transistor in the holding circuit changes with the turning on or off of the eighth transistor, and the equivalent capacitance when the eighth transistor is turned on is greater than the equivalent capacitance when the eighth transistor is turned off.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种移位寄存器、显示装置、栅极驱动电路及驱动方法，移位寄存器包括多级移位寄存电路（SR0-SRn），多级移位寄存电路（SR0-SRn）的第N级移位寄存电路包括：预充电电路（1）、上拉电路（2）、复位电路（3）和保持电路，保持电路设置有第八晶体管（M8），第八晶体管（M8）的栅极与第一控制信号端子（CK）连接，源极和漏极相互连接。其不仅实现了移位寄存，还减小了电路的工作周期，改善了电压与漂移问题，通过源漏短接的晶体管，实现控制信号对下拉节点的控制，使下拉结点在第一控制信号为高电平时快速升高，在第一控制信号为低电平时下降幅度减小，能够更好实现对电路的控制。

Description

移位寄存器、 显示装置、 栅极驱动电路及驱动方法 技术领域
本发明涉及液晶显示领域，特别涉及一种移位寄存器、显示装置、 栅极驱动电路及驱动方法。 背景技术
在薄膜晶体管液晶显示器 TFT-LCD中， 实现一帧画面显示的基 本原理是通过数据驱动将每一行像素所需的信号依次从上往下输出， 栅极驱动依次从上到下对每一像素行输入一定宽度的方波进行选通。 现今的制造方法是将栅极驱动 IC和数据驱动 IC通过 COG ( chip on glas s )工艺黏结在玻璃面板上。 小尺寸薄膜晶体管液晶显示器在分 辨率较高时， 栅极和数据驱动输出较多， 驱动 IC的长度将增大， 这 将不利于模组驱动 IC的贴合工艺。 如今， 通过栅极驱动电路的设计， 在不增加现有制程上任何工艺和成本的情况下将栅极驱动 IC通过阵 列基板工艺制作在玻璃面板上，基本的栅极驱动电路移位寄存器单元 电路原理图如图 1所示， 但该电路工作周期较长， 电压阈值存在漂移 问题， 控制信号无法对电路 4艮好的控制。 发明内容
本发明要解决的技术问题是： 如何提供一种移位寄存器、显示装 置、栅极驱动电路及驱动方法能够减小电路的工作周期， 改善电压阈 值漂移问题， 更好的实现控制信号对电路的控制。
为解决上述技术问题， 按照本发明的一个方面， 提供一种移位寄 存器， 所述移位寄存器包括多级移位寄存电路， 所述多级移位寄存电 路的第 N级移位寄存电路包括：
预充电电路， 用于对上拉电路进行预充电；
上拉电路， 用于在预充电完成后使输出端输出高电平；
复位电路，在输出端输出高电平后对所述第 N级移位寄存电路进 行复位； 保持电路，在所述第 N级移位寄存电路复位后保持第 N级移位寄 存电路的输出电位；
所述预充电电路的控制端和输入端与上一级移位寄存电路的输 出端连接， 输出端与所述复位电路的输入端连接；
所述上拉电路的输入端与第一控制信号端子连接；
所述复位电路的控制端与下一级移位寄存电路的输出端连接，输 出端接地；
所述保持电路与所述预充电电路的输出端、所述复位电路的输入 端、 所述上拉电路的控制端、 所述上拉电路的输出端相连， 第一控制 端与所述第一控制信号端子连接，第二控制端与所述第二控制信号端 子连接；
所述保持电路设置有第八晶体管，所述第八晶体管的栅极与所述 第一控制信号端子连接， 源极和漏极相互连接。
可选择地， 所述保持电路包括第一保持电路和第二保持电路， 所 述第八晶体管设置在所述第一保持电路中。
可选择地， 所述第一保持电路包括第五晶体管和第八晶体管， 所 述第八晶体管的栅极为所述保持电路的第一控制端，所述第八晶体管 的源极和漏极与所述第五晶体管的源极连接，所述第五晶体管的栅极 与所述上拉电路的控制端连接， 所述第五晶体管的漏极接地；
所述第二保持电路包括第四晶体管、 第六晶体管和第七晶体管， 所述第四晶体管的栅极为所述保持电路的第二控制端，第四晶体管的 源极与所述第六晶体管的源极及所述上拉电路的输出端连接，所述第 四晶体管的漏极接地，所述第六晶体管的栅极与所述第七晶体管的栅 极连接， 所述第六晶体管的漏极接地， 所述第七晶体管的源极与所述 预充电电路的输出端、 所述复位电路的输入端、 所述上拉电路的控制 端连接， 所述第七晶体管的漏极接地；
所述第一保持电路和第二保持电路通过下拉节点连接，所述下拉 节点连接第八晶体管的源极和漏极、 所述第五晶体管的源极、 所述第 六晶体管的栅极、 所述第七晶体管的栅极。
可选择地， 所述第一保持电路包括第五晶体管和第八晶体管， 所 述第八晶体管的控制端为所述保持电路的第一控制端，所述第八晶体 管的源极和漏极与所述第五晶体管的源极连接，所述第五晶体管的栅 极与所述上拉电路的控制端连接， 所述第五晶体管的漏极接地； 所述第二保持电路包括第四晶体管、 第六晶体管和第七晶体管， 所述第四晶体管的栅极为所述保持电路的第二控制端，第四晶体管的 源极与所述第七晶体管的源极及所述上拉电路的输出端连接，所述第 四晶体管的漏极接地，所述第六晶体管的栅极与所述第七晶体管的栅 极连接， 所述第六晶体管的源极与所述预充电电路的输出端、 所述复 位电路的输入端、 所述上拉电路的控制端连接， 所述第六晶体管的漏 极与第七晶体管的源极连接， 所述第七晶体管的漏极接地；
所述第一保持电路和第二保持电路通过下拉节点连接，所述下拉 节点连接第八晶体管的源极和漏极、 所述第五晶体管的源极、 所述第 六晶体管的栅极、 所述第七晶体管的栅极。
可选择地， 所述预充电电路包括第一晶体管， 所述第一晶体管的 栅极为控制端， 源极为输入端， 漏极为输出端。
可选择地， 所述复位电路包括第二晶体管， 所述第二晶体管的栅 极为控制端， 源极为输入端， 漏极为输出端。
可选择地， 所述上拉电路包括第三晶体管和电容， 所述第三晶体 管的栅极为控制端， 源极为输入端， 漏极为输出端， 所述第三晶体管 的栅极和漏极分别与所述电容的两端连接。
按照本发明的另一方面， 还提供一种栅极驱动电路， 所述栅极驱 动电路包括所述的移位寄存器。
按照本发明的另一方面， 还提供一种显示装置， 所述显示装置包 括所述的栅极驱动电路。
按照本发明的另一方面， 还提供一种栅极驱动方法， 该方法包括 步骤：
S1 预充电电路对上拉电路进行充电；
S2 上拉电路对移位寄存电路电位进行上拉， 移位寄存电路输出 高电平；
S3 复位电路对移位寄存电路进行复位； S4 保持电路在移位寄存电路复位后保持移位寄存电路的输出电 位；
所述步骤 S4中保持电路中的第八晶体管的等效电容随第八晶体 管的开启或关断改变，第八晶体管开启时的等效电容大于第八晶体管 关断时的等效电容。
本发明实施例的移位寄存器、显示装置、栅极驱动电路及驱动方 法， 不仅实现了移位寄存， 还减小了电路的工作周期， 改善了电压阈 值漂移问题， 通过源漏短接的晶体管， 实现控制信号对下拉节点的控 制， 使下拉结点在第一控制信号为高电平时快速升高， 在第一控制信 号为低电平时下降幅度减小， 能够更好实现控制信号对电路的控制。 附图说明
图 1是现有技术 G0A电路移位寄存器单元电路原理图；
图 2是本发明实施例移位寄存器电路原理图；
图 3是本发明实施例 1移位寄存器单元电路原理图；
图 4是本发明实施例移位寄存器单元电路时序波形图；
图 5是本发明实施例移位寄存器电路时序波形图；
图 6是本发明实施例 2移位寄存器单元电路原理图；
图 7是本发明实施例栅极驱动方法步骤图。 具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细 描述。 以下实施例用于说明本发明的原理， 但不用来限制本发明的范 围。
实施例 1 本发明实施例的一种移位寄存器包括多级移位寄存电路。 如图 2 所示， 图中 SRO-SRn为 n级移位寄存电路的每一级， GLO-GLn为 n级 移位寄存电路的输出端， STV为起始信号， 每级移位寄存器以上级的 输出作为 STV起始信号， 以下级的输出作为复位信号 RST, 在双时钟 CK和 CKB下工作， 实现自上而下的栅驱动扫描输出。 如图 3所示， 所述多级移位寄存电路的第 N级移位寄存电路包括： 预充电电路 1 , 用于对上拉电路进行预充电；
上拉电路 2 , 用于在预充电完成后使输出端 OUTPUT输出高电平； 复位电路 3 , 在输出端 OUTPUT输出高电平后对所述第 N级移位 寄存电路进行复位；
保持电路，在所述第 N级移位寄存电路复位后保持第 N级移位寄 存电路的输出电位；
其中 N为大于 1的自然数。
预充电电路 1的控制端和输入端与上一级移位寄存电路的输出端 N-1 _0UT连接， 输出端与所述复位电路 3的输入端连接；
上拉电路 2的输入端与第一控制信号端子 CK连接；
复位电路 3的控制端与下一级移位寄存电路的输出端 N+1 _0UT连 接， 输出端接地；
所述保持电路与预充电电路 1的输出端、 复位电路 3的输入端、 上 拉电路 2的控制端、 上拉电路 2的输出端相连， 第一控制端与所述第一 控制信号端子 CK连接，第二控制端与所述第二控制信号端子 CKB连接； 所述保持电路设置有第八晶体管 M8 ,第八晶体管 M8的栅极与所述 第一控制信号端子连接， 源极和漏极相互连接。
所述保持电路包括第一保持电路 4A和第二保持电路 4B,第八晶体 管 M8设置在第一保持电路 4A中。
第一保持电路 4A包括第五晶体管 M5和第八晶体管 M8 ,第八晶体管 M8的控制端为保持电路的第一控制端，第八晶体管 M8的源极和漏极与 第五晶体管 M5的源极连接， 第五晶体管 M5的栅极与上拉电路 2的控制 端连接， 第五晶体管 M5的漏极接地；
第二保持电路 4B包括第四晶体管 M4、第六晶体管 M6和第七晶体管 M7 , 第四晶体管 M4的栅极为所述保持电路的第二控制端， 第四晶体管 M4的源极与第六晶体管 M6的源极及上拉电路 2的输出端连接， 第四晶 体管 M4的漏极接地， 第六晶体管 M6的栅极与第七晶体管 M7的栅极连 接， 第六晶体管 M6的漏极接地， 第七晶体管 M7的源极与预充电电路 1 的输出端、 述复位电路 3的输入端、 上拉电路 2的控制端连接， 第七晶 体管 M7的漏极接地；
第一保持电路 4A和第二保持电路 4B通过下拉节点 PD连接，下拉节 点 PD连接第八晶体管 M8的源极和漏极、 第五晶体管 M5的源极、 第六晶 体管 M6的栅极、 第七晶体管 M7的栅极。
图中 PU为上拉节点， PD为下拉节点， 第一控制信号端子 CK与第二 控制信号端子 CKB输入的信号为差分输入的双时钟信号。
在该示例性实施例中， 预充电电路 1包括第一晶体管 Ml , 第一晶 体管 Ml的栅极为控制端， 源极为输入端， 漏极为输出端。
复位电路 3包括第二晶体管 M2 , 第二晶体管 M2的栅极为控制端， 源极为输入端， 漏极为输出端。
上拉电路 2包括第三晶体管 M3和电容器 C1 , 第三晶体管 M3的栅极 为控制端， 源极为输入端， 漏极为输出端， 第三晶体管 M3的栅极和漏 极分别与电容器 C1的两端连接。
可选择地， 上面提到的晶体管（第一晶体管、 第二晶体管、 第三 晶体管、 第四晶体管、 第五晶体管、 第六晶体管、 第七晶体管、 第八 晶体管） 为薄膜晶体管。
具体地， 本发明实施例 1的移位寄存器， 如图 4所示， 在第一时 钟信号内， 第一控制信号端子 CK输出为低电平， 第二控制信号端子 CKB输出为高电平， 上一级移位寄存电路输出 N-1 _0UT为高电平， 下 一级移位寄存电路输出 N+1 -0UT为低电平。 晶体管 M2、 M6、 M7、 M8 关断， 晶体管 Ml、 M4开启。 上一级移位寄存电路输出 N-1 _0UT通过 晶体管 Ml对晶体管 M3的栅极进行预充电， 使得上拉节点 PU点电压 上升。 第二控制信号端子 CK为低电平， 同时上拉节点 PU对下拉节点 PD进行下拉， 使下拉节点 PD电压为低， 晶体管 M6、 M7均关断， 使 晶体管 M3的栅极上拉节点 PU保持预充电（ Pre-charg ing )状态， 输 出端 OUTPUT电压保持低电平。
在第二时钟信号内， 电路预充电（Pre-charg ing )后， 第一控制 信号端子 CK输出为高电平， 第二控制信号端子 CKB输出为低电平， 上 一级移位寄存电路输出 N-1 _0UT为低电平， 下一级移位寄存电路输出 N+1 _0UT为低电平。 晶体管 Ml、 M2、 M4关断。 上拉节点 PU通过电容器 CI的升压 （boos t )作用上升， 晶体管 M3开启， 输出端 OUTPUT输出高 电压信号。 晶体管 M8的源漏短接， 等效于电容， 使下拉节点 PD点电位 耦合第一控制信号端子 CK的信号变化， 此时上拉节点 PU为高电平， 晶 体管 M5开启， 晶体管 M8、 M5的宽长比使下拉节点 PD电位为低， 晶体管 M7、 M8关断。 此阶段晶体管 M8的等效电容大小为晶体管开启时的等效 电容。 上拉节点 PU保持高电平， 输出端 OUTPUT保持输出高电平， 对上 一级移位寄存电路输出 N-1 -OUT信号进行移位。
在第三时钟信号内， 上一级移位寄存电路输出 N-1 -0UT 为低电 平， 第一控制信号端子 CK为低电平， 第二控制信号端子 CKB为高电 平， 下一级移位寄存电路输出 N+1 _0UT为高电平。 晶体管 Ml关断， 晶体管 M2、 M4开启。 上拉节点 PU和输出端 OUTPUT置位到低电平。
在第四时钟信号内， 上一级移位寄存电路输出 N-1 -0UT 为低电 平， 下一级移位寄存电路输出 N+1 _0UT为低电平， 第一控制信号端子 CK为高电平， 第二控制信号端子 CKB为低电平。 晶体管 Ml、 M2、 M4 关断， 上拉节点 PU为低电平， 晶体管 M3、 M5关断。 晶体管 M8的源 漏短接， 等效于电容， 第一控制信号端子 CK为高电平， 下拉节点 PD 通过晶体管 M8耦合第一控制信号端子 CK的高电平， 使晶体管 M6、 M7开启， 上拉节点 PU和输出端 OUTPUT下拉至低电平。 此阶段晶体 管 M8的等效电容大小为晶体管开启时的等效电容， 电容较晶体管关 断时的等效电容大。
在第五时钟信号内， 上一级移位寄存电路输出 N-1 -0UT 为低电 平， 下一级移位寄存电路输出 N+1 _0UT为低电平， 第一控制信号端子 CK为低电平， 第二控制信号端子 CKB为高电平。 晶体管 M1、 M2关断， 上拉节点 PU为低电平， 晶体管 M3、 M5关断。 晶体管 M4开启， 输出 端 OUTPUT下拉至低电平。 晶体管 M8的源漏短接， 等效于电容， 第一 控制信号端子 CK为低电平， 下拉节点 PD通过晶体管 M8耦合第一控 制信号端子 CK的低电平，此阶段晶体管 M8的等效电容大小为晶体管 关断时的等效电容， 电容较晶体管开启时的等效电容小。
本发明实施例的移位寄存器电路时序波形图如图 5 所示， 图中 STV为起始信号， GLO-GLn为 n级移位寄存电路的输出端。 本发明实施例的移位寄存器减小了电路的工作周期，改善了电压 阈值漂移问题， 通过源漏短接的晶体管， 实现控制信号对下拉节点的 控制， 使下拉节点在第一控制信号为高电平时快速升高， 在第一控制 信号为低电平时下降幅度减小， 能够更好实现控制信号对电路的控 制。
实施例 2
本发明实施例的一种移位寄存器如图 6所示， 其特征与实施例 1 基本相同， 不同之处在于， 第一保持电路 4A包括第五晶体管 M5和第八 晶体管 M8 , 第八晶体管 M8的控制端为所述保持电路的第一控制端， 第 八晶体管 M8的源极和漏极与第五晶体管 M5的源极连接，第五晶体管 M5 的栅极与上拉电路的控制端连接， 第五晶体管 M5的漏极接地；
第二保持电路 4B包括第四晶体管 M4、第六晶体管 M6和第七晶体管 M7 , 第四晶体管 M4的栅极为所述保持电路的第二控制端， 第四晶体管 M4的源极与第七晶体管 M7的源极及上拉电路 2的输出端连接， 第四晶 体管 M4的漏极接地， 第六晶体管 M6的栅极与第七晶体管 M7的栅极连 接， 第六晶体管 M6的源极与预充电电路 1的输出端、 复位电路 3的输入 端、 上拉电路 2的控制端连接， 第六晶体管 M6的漏极与第七晶体管 M7 的源极连接， 第七晶体管 M7的漏极接地；
第一保持电路 4A和第二保持电路 4B通过下拉节点 PD连接，下拉节 点 PD连接第八晶体管的源极和漏极、 第五晶体管的源极、 第六晶体管 的栅极、 第七晶体管的栅极。
通过源漏短接的晶体管实现电容耦合的效果，本发明实施例的方 案可以有 4艮多种，例如可以通过预充电电路 P r e-cha r g i ng和复位电路 Reset模块的设计实现 GOA双向扫描、通过设计使上拉节点 PU和输出端 OUTPUT下拉至前一级或后一级移位寄存器的输出、或者是采用本发明 技术的四个时钟电路，只要使用了本发明的通过源漏短接的晶体管实 现电容耦合的效果的技术方案， 都在本发明的保护范围内。
本发明实施例的一种栅极驱动电路，所述栅极驱动电路包括所述 的移位寄存器。
本发明实施例的一种显示装置，所述显示装置包括所述的栅极驱 动电路。
图 7示出本发明示例性实施例的一种栅极驱动方法的流程图。 如 图 7所示， 该方法的操作过程如下：
在步骤 S1中， 预充电电路对上拉电路进行充电；
在步骤 S2中， 上拉电路对移位寄存电路电位进行上拉， 移位寄存 电路输出高电平；
在步骤 S3中， 复位电路对移位寄存电路进行复位；
在步骤 S4中，保持电路在移位寄存电路复位后保持移位寄存电路 的输出电位。
在步骤 S4中，保持电路中的第八晶体管的等效电容随第八晶体管 的开启或关断改变，第八晶体管开启时的等效电容大于第八晶体管关 断时的等效电容。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关 技术领域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明 的范畴， 本发明的专利保护范围应由权利要求限定。

Claims

权 利 要 求 书
1、 一种移位寄存器， 包括： 多级移位寄存电路， 所述多级移位 寄存电路的第 N级移位寄存电路包括：
预充电电路， 用于对上拉电路进行预充电；
上拉电路， 用于在预充电完成后使输出端输出高电平； 复位电路，在输出端输出高电平后对所述第 N级移位寄存电路进 行复位；
保持电路，在所述第 N级移位寄存电路复位后保持第 N级移位寄 存电路的输出电位；
所述预充电电路的控制端和输入端与上一级移位寄存电路的输 出端连接， 输出端与所述复位电路的输入端连接；
所述上拉电路的输入端与第一控制信号端子连接；
所述复位电路的控制端与下一级移位寄存电路的输出端连接，输 出端接地；
所述保持电路与所述预充电电路的输出端、所述复位电路的输入 端、 所述上拉电路的控制端、 所述上拉电路的输出端相连， 第一控制 端与所述第一控制信号端子连接，第二控制端与所述第二控制信号端 子连接；
所述保持电路设置有第八晶体管，所述第八晶体管的栅极与所述 第一控制信号端子连接， 源极和漏极相互连接。
2、 如权利要求 1所述的移位寄存器， 其中， 所述保持电路包括第 一保持电路和第二保持电路，所述第八晶体管设置在所述第一保持电 路中。
3、 如权利要求 2所述的移位寄存器， 其中， 所述第一保持电路包 括第五晶体管和第八晶体管，所述第八晶体管的栅极为所述保持电路 的第一控制端，所述第八晶体管的源极和漏极与所述第五晶体管的源 极连接， 所述第五晶体管的栅极与所述上拉电路的控制端连接， 所述 第五晶体管的漏极接地； 所述第二保持电路包括第四晶体管、 第六晶体管和第七晶体管， 所述第四晶体管的栅极为所述保持电路的第二控制端，第四晶体管的 栅极源极与所述第六晶体管的源极及所述上拉电路的输出端连接，所 述第四晶体管的漏极接地，所述第六晶体管的栅极与所述第七晶体管 的栅极连接， 所述第六晶体管的漏极接地， 所述第七晶体管的源极与 所述预充电电路的输出端、 所述复位电路的输入端、 所述上拉电路的 控制端连接， 所述第七晶体管的漏极接地；
所述第一保持电路和第二保持电路通过下拉节点连接，所述下拉 节点连接第八晶体管的源极和漏极、 所述第五晶体管的源极、 所述第 六晶体管的栅极、 所述第七晶体管的栅极。
4、 如权利要求 2所述的移位寄存器， 其中， 所述第一保持电路包 括第五晶体管和第八晶体管，所述第八晶体管的控制端为所述保持电 路的第一控制端，所述第八晶体管的源极和漏极与所述第五晶体管的 源极连接， 所述第五晶体管的栅极与所述上拉电路的控制端连接， 所 述第五晶体管的漏极接地；
所述第二保持电路包括第四晶体管、 第六晶体管和第七晶体管， 所述第四晶体管的栅极为所述保持电路的第二控制端，第四晶体管的 源极与所述第七晶体管的源极及所述上拉电路的输出端连接，所述第 四晶体管的漏极接地，所述第六晶体管的栅极与所述第七晶体管的栅 极连接， 所述第六晶体管的源极与所述预充电电路的输出端、 所述复 位电路的输入端、 所述上拉电路的控制端连接， 所述第六晶体管的漏 极与第七晶体管的源极连接， 所述第七晶体管的漏极接地；
所述第一保持电路和第二保持电路通过下拉节点连接，所述下拉 节点连接第八晶体管的源极和漏极、 所述第五晶体管的源极、 所述第 六晶体管的栅极、 所述第七晶体管的栅极。
5、 如权利要求 1所述的移位寄存器， 其中， 所述预充电电路包括 第一晶体管， 所述第一晶体管的栅极为控制端， 源极为输入端， 漏极 为输出端。
6、 如权利要求 1所述的移位寄存器， 其中， 所述复位电路包括第 二晶体管， 所述第二晶体管的栅极为控制端， 源极为输入端， 漏极为 输出端。
7、 如权利要求 1所述的移位寄存器， 其中， 所述上拉电路包括第 三晶体管和电容器，所述第三晶体管的栅极为控制端，源极为输入端， 漏极为输出端，所述第三晶体管的栅极和漏极分别与所述电容器的两 端连接。
8、 一种栅极驱动电路， 包括权利要求 1-7中任意一项所述的移位 寄存器。
9、 一种显示装置， 包括权利要求 8所述的栅极驱动电路。
10、 一种栅极驱动方法， 包括下列步骤：
预充电电路对上拉电路进行充电 （S1 );
上拉电路对移位寄存电路电位进行上拉，移位寄存电路输出高电 平 （S2 );
复位电路对移位寄存电路进行复位 S 3；
保持电路在移位寄存电路复位后保持移位寄存电路的输出电位 ( S4 );
在所述步骤 S4中保持电路中的第八晶体管的等效电容随第八晶 体管的开启或关断改变，第八晶体管开启时的等效电容大于第八晶体 管关断时的等效电容。
PCT/CN2013/078443 2013-03-14 2013-06-28 移位寄存器、显示装置、栅极驱动电路及驱动方法 WO2014139249A1 (zh)

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