WO2019056803A1 - 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2019056803A1
WO2019056803A1 PCT/CN2018/090217 CN2018090217W WO2019056803A1 WO 2019056803 A1 WO2019056803 A1 WO 2019056803A1 CN 2018090217 W CN2018090217 W CN 2018090217W WO 2019056803 A1 WO2019056803 A1 WO 2019056803A1
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Prior art keywords
pull
node
shift register
circuit
output
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PCT/CN2018/090217
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English (en)
French (fr)
Inventor
韩明夫
商广良
韩承佑
姚星
郑皓亮
袁丽君
王志冲
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/307,060 priority Critical patent/US20210225312A1/en
Priority to JP2018564266A priority patent/JP7208018B2/ja
Priority to EP18807544.4A priority patent/EP3686894A4/en
Publication of WO2019056803A1 publication Critical patent/WO2019056803A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • a pixel array such as a liquid crystal display typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by an attached integrated driving circuit.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • GOA Gate driver On Array
  • a GOA composed of a plurality of cascaded shift register units may be used to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and corresponding to the pixel arrays by the data lines.
  • the pixel units of the row provide data signals to form the gray voltages required to display the gray levels of the image, thereby displaying each frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a pull-up node reset circuit, an output circuit, and a coupling circuit.
  • the input circuit is configured to charge a pull-up node in response to an input signal;
  • the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal;
  • the output circuit is configured to The first clock signal is output to the first output terminal under the control of the level of the pull-up node;
  • the coupling circuit is configured to perform coupling control on the potential of the pull-up node in response to the second clock signal.
  • the shift register unit provided by an embodiment of the present disclosure further includes a pull-down node control circuit, a pull-up node noise reduction circuit, and an output noise reduction circuit.
  • the pull-down node control circuit is configured to control a level of a pull-down node;
  • the pull-up node noise reduction circuit is configured to perform noise reduction on the pull-up node under control of a level of the pull-down node
  • the output noise reduction circuit is configured to perform noise reduction on the first output under control of a level of the pull-down node.
  • the coupling circuit includes a first transistor and a storage capacitor. a gate of the first transistor and a first pole of a storage capacitor are configured to be coupled to the pull-up node, and a first pole of the first transistor is configured to be coupled to a second clock signal terminal to receive the first a second clock signal, the second pole of the first transistor being configured to be coupled to the second pole of the storage capacitor.
  • a shift register unit provided by an embodiment of the present disclosure further includes a second output.
  • the coupling circuit is further configured to output the second clock signal to the second output, the second output being configured to be coupled to the second pole of the first transistor.
  • a shift register unit provided by an embodiment of the present disclosure further includes a coupling reset circuit.
  • the coupled reset circuit is configured to reset the second output under control of a level of the pull-down node.
  • the coupled reset circuit includes: a second transistor having a gate configured to be connected to the pull-down node, the first pole being configured to be the same The two outputs are connected, and the second pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the input circuit includes: a third transistor having a gate connected to the first electrode and configured to be connected to the input terminal to receive the input signal, A second pole is configured to connect with the pull up node to charge the pull up node.
  • the pull-up node reset circuit includes: a fourth transistor having a gate configured to be connected to the reset terminal to receive the reset signal, the first pole being And being coupled to the pull-up node to reset the pull-up node, the second pole being configured to be coupled to the first voltage terminal to receive the first voltage.
  • the output circuit includes: a fifth transistor having a gate configured to be connected to the pull-up node, the first pole being configured to be the first clock
  • the signal terminal is coupled to receive the first clock signal
  • the second pole is configured to be coupled to the first output terminal.
  • the pull-down node control circuit includes: a sixth transistor having a gate connected to the first pole and configured to be connected to the second voltage terminal to receive the first a second voltage, the second pole being configured to be coupled to the pull-down node; and a seventh transistor having a gate configured to be coupled to the pull-up node, the first pole being configured to be coupled to the pull-down node, and second The pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the pull-up node noise reduction circuit includes: an eighth transistor whose gate is configured to be connected to the pull-down node, and the first pole is configured to The pull-up node is connected to perform noise reduction on the pull-up node, and the second pole is configured to be connected to the first voltage terminal to receive the first voltage.
  • the output noise reduction circuit includes: a ninth transistor having a gate configured to be connected to the pull-down node, the first pole being configured to be The first output is coupled, and the second pole is configured to be coupled to the first voltage terminal to receive the first voltage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units according to embodiments of the present disclosure.
  • the input terminals of the remaining stages of the shift register unit are connected to the first output end of the shift register unit of the previous stage; except for the last stage shift register unit, the remaining stages are shifted.
  • the reset terminal of the register unit is coupled to the first output of the shift register unit of the next stage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units according to embodiments of the present disclosure.
  • the input terminals of the remaining stages of shift register units are connected to the second output end of the shift register unit of the previous stage; except for the last stage shift register unit, the remaining stages are shifted.
  • the reset terminal of the register unit is connected to the second output terminal of the shift register unit of the next stage.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit according to any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: in a first stage, the input circuit charges the pull-up node in response to the input signal, and the output circuit outputs the a low level of the first clock signal to the first output terminal; in a second phase, a potential of the pull-up node is increased by a high level coupling of the first clock signal and the second clock signal, The output circuit outputs a high level of the first clock signal to the first output terminal; in a third stage, a potential of the pull-up node is reduced by a low level coupling of the first clock signal, An output terminal is discharged through the output circuit; in a fourth stage, a potential of the pull-up node is further coupled low by a low level of the second clock signal; in a fifth stage, the pull-up node reset circuit is in the Resetting the pull-up node under control of the reset signal; wherein, in the third phase and the fourth phase, a falling edge of the first clock signal is earlier than the
  • a rising edge timing of the first clock signal and a rising edge timing of the second clock signal are consistent.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: in a first stage, the input circuit charges the pull-up node in response to the input signal, and the output circuit outputs the a low level of the first clock signal to the first output end, the coupling circuit outputs a low level of the second clock signal to the second output end; and a second stage, a potential of the pull-up node Is pulled high by the high level coupling of the first clock signal and the second clock signal, the output circuit outputs a high level of the first clock signal to the first output end, the coupling circuit outputs a high level of the second clock signal to the second output end; in a third stage, a potential of the pull-up node is pulled low by a low level coupling of the first clock signal, the first output end Dissolving to a low level by the output circuit, the coupling circuit outputs a high level of the second clock signal to the second output end; in a fourth stage, a potential of the pull-up node is
  • 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a timing chart of signals corresponding to the operation of the shift register unit shown in FIG. 1;
  • FIG. 3 is a schematic block diagram of a shift register unit according to an example of an embodiment of the present disclosure
  • FIG. 4 is a schematic block diagram of a shift register unit according to another example of an embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram showing an implementation example of the shift register unit shown in FIG. 4;
  • FIG. 6 is a circuit diagram showing an implementation example of the shift register unit shown in FIG. 3;
  • Figure 7 is a timing diagram of signals corresponding to the operation of the shift register unit shown in Figure 5;
  • FIG. 8 is a schematic diagram of emulating the potential of the pull-up node PU in the shift register unit shown in FIGS. 1 and 5.
  • FIGS. 9 is a schematic diagram of simulating an output signal of a first output terminal OUT1 in the shift register unit shown in FIGS. 1 and 5.
  • FIG. 10 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display panel in order to realize low cost and narrow bezel, GOA (Gate driver On Array) technology can be adopted, that is, the gate driving circuit is integrated on the display panel through the thin film transistor process, thereby achieving narrow bezel and reducing assembly cost, etc.
  • GOA Gate driver On Array
  • the display panel may be a liquid crystal display (LCD) panel or an organic light emitting diode (OLED) display panel.
  • FIG. 1 shows a circuit structure of a shift register unit which can be cascaded to form a gate drive circuit.
  • the shift register unit includes nine transistors (T1 to T9) and a storage capacitor (C1).
  • the first transistor T1 has a gate connected to the pull-up node PU, a first pole connected to the first clock signal terminal CLK, and a second pole connected to the second output terminal OUT2.
  • the second transistor T2 has a gate connected to the pull-down node PD, a first pole connected to the second output terminal OUT2, and a second pole connected to the first voltage terminal VGL.
  • the third transistor T3 has a gate connected to the first electrode and configured to be connected to the input terminal INPUT, and the second pole is connected to the pull-up node PU.
  • the fourth transistor T4 has a gate connected to the reset terminal RST, a first pole connected to the pull-up node PU, and a second pole connected to the first voltage terminal VGL.
  • the fifth transistor T5 has a gate connected to the pull-up node PU, a first pole connected to the first clock signal terminal CLK, and a second pole connected to the first output terminal OUT1.
  • the sixth transistor T6 has a gate connected to the first electrode and is configured to be connected to the second voltage terminal VGH (for example, to maintain an input DC high level signal), and the second electrode is connected to the pull-down node PD.
  • the seventh transistor T7 has a gate connected to the pull-up node PU, a first pole connected to the pull-down node PD, and a second pole connected to the first voltage terminal VGL.
  • the eighth transistor T8 has a gate connected to the pull-down node PD, a first pole connected to the pull-up node PU, and a second pole connected to the first voltage terminal VGL (eg, holding an input DC low level signal).
  • the ninth transistor T9 has a gate connected to the pull-down node PD, a first pole connected to the first output terminal OUT1, and a second pole connected to the first voltage terminal VGL.
  • the storage capacitor C1 has a first pole connected to the pull-up node PU and a second pole connected to the first output terminal OUT1.
  • the above transistors are all N-type transistors.
  • the following description is also made by taking an N-type transistor as an example, but embodiments of the present disclosure are not limited to such a case, for example, at least part of these transistors may be replaced with a P-type transistor.
  • the shift register unit performs the following operations.
  • the first clock signal terminal CLK inputs a low level signal
  • the input terminal INPUT inputs a high level signal. Since the input terminal INPUT inputs a high level signal, the third transistor T3 is turned on, so that the high level of the input terminal INPUT input charges the storage capacitor C1, and the potential of the pull-up node PU is pulled up to the first high level.
  • the second voltage terminal VGH may be set to maintain an input DC high level signal
  • the sixth transistor T6 remains turned on, and the high level input by the second voltage terminal VGH charges the pull-down node PD.
  • the seventh transistor T7 is turned on, thereby electrically connecting the pull-down node PD and the first voltage terminal VGL.
  • the first voltage terminal VGL may be set to hold an input DC low level signal.
  • the sixth transistor T6 and the seventh transistor T7 can be configured (for example, the size ratio of the two, the threshold voltage, etc.).
  • the eighth transistor T8 does not cause the eighth transistor T8 to turn on.
  • the potential level of the signal timing diagram shown in FIG. 2 is only illustrative and does not represent a true potential value.
  • the pull-up node PU is at the first high level, the first transistor T1 and the fifth transistor T5 are turned on, and at this time, the first clock signal terminal CLK is input with a low level, so at this stage, the first output terminal OUT1 and the second terminal The output terminal OUT2 outputs the low level signal.
  • the first clock signal terminal CLK inputs a high level signal
  • the input terminal INPUT inputs a low level signal. Since the input terminal INPUT inputs a low level signal, the third transistor T3 is turned off, and the pull-up node PU maintains the first high level of the previous stage, so that the first transistor T1 and the fifth transistor T5 remain turned on, due to the fact that at this stage
  • the first clock signal terminal CLK is input to a high level, so the first output terminal OUT1 and the second output terminal OUT2 output the high level signal.
  • the high level can pass through the parasitic capacitance of the first transistor T1 (including between the gate and the first pole) Parasitic capacitance, and parasitic capacitance between the gate and the second stage), parasitic capacitance of the fifth transistor T5 (including parasitic capacitance between the gate and the first electrode, and parasitic capacitance between the gate and the second stage)
  • the storage capacitor C1 couples the potential of the pull-up node PU to rise.
  • the voltage amplitude of the PU coupling of the pull-up node can be calculated by Equation 1:
  • ⁇ V_PU ⁇ V_CLK ⁇ (C_T1+C_T5+C_C1)/C_PU;
  • ⁇ V_PU is the voltage amplitude of the pull-up node PU coupling
  • ⁇ V_CLK is the voltage amplitude change of the first clock signal terminal
  • C_T1 is the parasitic capacitance value of the first transistor T1
  • C_T5 is the parasitic capacitance value of the fifth transistor T5
  • C_C1 For the capacitance value of the storage capacitor C1, C_PU is the sum of all the capacitances connected to the pull-up node PU.
  • the potential of the pull-up node PU is coupled to rise to a second high level, so that the conduction of the fifth transistor T5 is more sufficient. Since the potential of the pull-up node PU is at a high level, the seventh transistor T7 continues to be turned on, so that the potential of the pull-down node PD continues to remain at a low level. Since the potential of the pull-down node PD is at a low level, the second transistor T2, the eighth transistor T8, and the ninth transistor T9 remain in an off state, thereby not affecting the potential of the pull-up node PU and the shift register unit normally outputting the shift signal.
  • the signal input from the first clock signal terminal CLK changes from a high level to a low level, and the input terminal INPUT continues to input a low level.
  • the potential of the pull-up node PU is coupled to the first high level (as shown in the figure).
  • the dotted line ellipse is indicated in 2), and the voltage amplitude of the coupling reduction can still be calculated by Equation 1.
  • the fifth transistor T5 remains on, and the first output terminal OUT1 is discharged to the first clock signal terminal CLK at a low level through the fifth transistor T5; A transistor T1 remains open, and the second output terminal OUT2 discharges to the first clock signal terminal CLK at a low level through the first transistor T1. By discharging, the potentials of the first output terminal OUT1 and the second output terminal OUT2 are lowered to a low level.
  • the fourth transistor T4 is turned on, the pull-up node PU is electrically connected to the first voltage terminal VGL, and the potential of the pull-up node PU is pulled down to a low level, thereby The first transistor T1 and the fifth transistor T5 are turned off.
  • the seventh transistor T7 is turned off, the discharge path of the pull-down node PD is turned off, and the potential of the pull-down node PD is charged to a high level, thereby making the eighth transistor T8 and the second transistor T2
  • the ninth transistor T9 is turned on, respectively pulling the potential of the pull-up node PU, the second output terminal OUT2 and the first output terminal OUT1 to the low level input by the first voltage terminal VGL, further eliminating the shift register unit in the non-
  • the output stage has its output (including the first output terminal OUT1 and the second output terminal OUT2) and noise that may be generated at the pull-up node PU.
  • the shift register cells shown in FIG. 1 may be cascaded to form a gate drive circuit for driving each of the shift register cells, for example, corresponding to one gate line, for driving the display panel.
  • the first output terminal OUT1 may be connected to the corresponding gate line to provide a progressive scan signal
  • the second output terminal OUT2 may be connected to the reset terminal RST of the shift register unit of the previous stage and the input terminal INPUT of the shift register unit of the next stage.
  • a reset signal and an input signal are provided separately. This connection method can improve the load capacity of the shift register unit.
  • the time available for charging is greatly reduced, for example, a display with an ⁇ -Si (amorphous silicon) TFT (thin film transistor) as a pixel switching element and a resolution of 8K.
  • ⁇ -Si amorphous silicon
  • TFT thin film transistor
  • the turn-on time of a row of pixel units is only 3.7 ⁇ s, for example, and the actual effective charging time is less. Therefore, the increase of the charging time of 0.1 ⁇ s can significantly improve the charging rate.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a pull-up node reset circuit, an output circuit, and a coupling circuit.
  • the input circuit is configured to charge the pull-up node in response to the input signal;
  • the pull-up node reset circuit is configured to reset the pull-up node in response to the reset signal;
  • the output circuit is configured to be at a level of the pull-up node
  • the first clock signal is output to the first output terminal;
  • the coupling circuit is configured to perform coupling control on the potential of the pull-up node in response to the second clock signal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit, a display device, and a driving method corresponding to the shift register unit described above.
  • the shift register unit, the gate driving circuit, the display device and the driving method provided by the embodiments of the present disclosure can control the potential of the pull-up node by the coupling circuit to maintain a high potential when discharging at the first output end. Therefore, the falling edge time of the output signal of the first output terminal can be reduced, and the charging time of the pixel unit in the display panel can be increased, so that the driving capability can be improved.
  • One example of an embodiment of the present disclosure provides a shift register unit 100 that includes an input circuit 110, a pull-up node reset circuit 120, an output circuit 130, and a coupling circuit 140, as shown in FIG.
  • the input circuit 110 is configured to charge the pull up node PU in response to an input signal.
  • the input circuit 110 can be configured to electrically connect the pull-up node PU and the input terminal INPUT so that the high-level signal input to the input terminal INPUT can charge the pull-up node PU.
  • the pull up node reset circuit 120 is configured to reset the pull up node PU in response to the reset signal.
  • the pull-up node reset circuit 120 can be configured to be connected to the reset terminal RST, so that the pull-up node PU can be electrically connected to the low-level signal or the low-voltage terminal under the control of the reset signal input by the reset terminal RST.
  • the low voltage terminal is, for example, the first voltage terminal VGL, so that the pull-up node PU can be pulled down and reset. It should be noted that the first voltage terminal VGL can be configured, for example, to maintain an input DC low-level signal.
  • the output circuit 130 is configured to output the first clock signal to the first output terminal OUT1 under the control of the level of the pull-up node PU.
  • the output circuit 130 can be configured to electrically connect the first clock signal terminal CLK and the first output terminal OUT1 under the control of the level of the pull-up node PU, so that the first clock signal terminal CLK can be input.
  • a clock signal is output to the first output terminal OUT1.
  • the first output terminal OUT1 can also be discharged through the output circuit 130.
  • the coupling circuit 140 is configured to couple control the potential of the pull-up node PU in response to the second clock signal.
  • the coupling circuit 140 can be connected to the second clock signal terminal CLKA, so that when the second clock signal input by the second clock signal terminal CLKA is at a high level, the coupling circuit 140 couples the potential of the pull-up node PU to be controlled.
  • the potential rises; when the second clock signal input by the second clock signal terminal CLKA is at a low level, the coupling circuit 140 couples the potential of the pull-up node PU to lower its potential.
  • a plurality of cascaded shift register units 100 may be employed to form a gate drive circuit.
  • the potential of the pull-up node PU can be controlled by the output circuit 130 and the coupling circuit 140, and with the cooperation of the first clock signal and the second clock signal, so that the potential of the pull-up node PU is controlled.
  • the first output terminal OUT1 is discharged, it is kept at a higher potential, so that the falling edge time of the output signal of the first output terminal OUT1 can be reduced, and the charging time of the pixel unit in the display panel can be increased, so that the driving capability can be improved.
  • the shift register unit 100 may further include a pull-down node control circuit 150, a pull-up node noise reduction circuit 160, and an output noise reduction circuit 170.
  • the pull-down node control circuit 150 is configured to control the level of the pull-down node PD to control the pull-up node noise reduction circuit 160 and the output noise reduction circuit 170.
  • the pull-up node noise reduction circuit 160 is configured to perform noise reduction on the pull-up node PU under the control of the level of the pull-down node PD.
  • the pull-up node noise reduction circuit 160 may be configured to be connected to the first voltage terminal VGL to electrically connect the pull-up node PU and the first voltage terminal VGL under the control of the level of the pull-down node PD, thereby The pull-up node PU performs pull-down noise reduction.
  • the output noise reduction circuit 170 is configured to perform noise reduction on the first output terminal OUT1 under the control of the level of the pull-down node PU.
  • the output noise reduction circuit 170 can be configured to electrically connect the first output terminal OUT1 and the first voltage terminal VGL under the control of the level of the pull-down node PD, thereby performing pull-down noise reduction on the first output terminal OUT1.
  • the shift register unit 100 may further include a second output terminal OUT2 and a coupled reset circuit 180.
  • the coupling circuit 140 is also configured to output a second clock signal to the second output terminal OUT2.
  • the second output terminal OUT2 may be connected to the reset terminal RST of the shift register unit of the previous stage and the shift register of the next stage.
  • the input terminal of the unit is connected to INPUT to provide a reset signal and an input signal, respectively. The use of two outputs increases the load capacity of the shift register unit.
  • the coupled reset circuit 180 is configured to reset the second output terminal OUT2 under the control of the level of the pull-down node PU.
  • the coupling reset circuit 180 may be configured to be connected to the first voltage terminal VGL to electrically connect the second output terminal OUT2 and the first voltage terminal VGL under the control of the level of the pull-down node PU, thereby implementing the The pull-down reset of the two output terminals OUT2.
  • the shift register unit 100 shown in FIG. 4 can be implemented as the circuit structure shown in FIG. 5 in one example.
  • the shift register unit 100 includes first to ninth transistors T1-T9 and a storage capacitor C1.
  • the coupling circuit 140 can be implemented to include the first transistor T1 and the storage capacitor C1.
  • the gate of the first transistor T1 is configured to be connected to the pull-up node PU, the first pole is configured to be coupled to the second clock signal terminal CLKA to receive the second clock signal, and the second pole is configured to be coupled to the second output terminal OUT2
  • the first pole of the storage capacitor C1 is configured to be connected to the pull-up node PU, and the second pole is configured to be coupled to the second output terminal OUT2.
  • the coupled reset circuit 180 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be coupled to a pull-down node PU, the first pole is configured to be coupled to the second output terminal OUT2, and the second pole is configured to be coupled to the first voltage terminal VGL to receive the first voltage.
  • first voltage terminal VGL in the embodiment of the present disclosure maintains, for example, an input DC low level signal, and the DC low level is referred to as a first voltage; and the second voltage terminal VGH maintains an input DC high level, for example.
  • the signal which is referred to as the second voltage.
  • the input circuit 110 can be implemented as a third transistor T3.
  • a gate of the third transistor T3 is coupled to the first pole and is configured to be coupled to the input terminal INPUT to receive an input signal, and the second pole is configured to be coupled to the pull-up node PU to charge the pull-up node PU.
  • the pull-up node reset circuit 120 can be implemented as a fourth transistor T4.
  • a gate of the fourth transistor T4 is configured to be coupled to the reset terminal RST to receive a reset signal
  • the first pole is configured to be coupled to the pull-up node PU to reset the pull-up node PU
  • the second pole is configured to be first
  • the voltage terminal VGL is connected to receive the first voltage.
  • the output circuit 130 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the pull-up node PU, the first pole is configured to be coupled to the first clock signal terminal CLK to receive the first clock signal, and the second pole is configured to be coupled to the first output terminal OUT1 connection.
  • the pull-down node control circuit 150 can be implemented to include a sixth transistor T6 and a seventh transistor T7.
  • the gate of the sixth transistor T6 is connected to the first electrode, and is configured to be connected to the second voltage terminal VGH to receive the second voltage, the second electrode is configured to be connected to the pull-down node PD; the gate of the seventh transistor T7 is The first pole is configured to be connected to the pull-down node PD, and the second pole is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the pull-up node noise reduction circuit 160 can be implemented as an eighth transistor T8.
  • the gate of the eighth transistor T8 is configured to be connected to the pull-down node PU
  • the first pole is configured to be connected to the pull-up node PU to perform noise reduction on the pull-up node PU
  • the second pole is configured to be coupled to the first voltage terminal VGL Connect to receive the first voltage.
  • the output reset circuit 170 can be implemented as a ninth transistor T9.
  • the gate of the ninth transistor T9 is configured to be coupled to the pull-down node PD, the first pole is configured to be coupled to the first output terminal OUT1, and the second pole is configured to be coupled to the first voltage terminal VGL to receive the first voltage.
  • the gates of the second transistor T2 and the ninth transistor T9 may not be connected to the pull-down node PD, but may be electrically connected to the reset terminal RST, so that Under the control of the reset signal input by the reset terminal RST, the effect of reset noise reduction is realized.
  • the embodiments of the present disclosure do not limit this.
  • the shift register unit 100 shown in FIG. 3 it can be realized as the circuit configuration shown in FIG.
  • the connection relationship of the respective transistors and the storage capacitor C1 shown in FIG. 6 can be referred to the corresponding description in the shift register unit 100 shown in FIG. 5, and details are not described herein again.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt a P-type transistor.
  • the first pole may be a source
  • the second pole may be a drain, and only needs to be selected.
  • the polarities of the poles of the transistor of a given type may be correspondingly connected according to the polarities of the respective poles of the respective transistors in the embodiment of the present disclosure.
  • the transistors in the shift register unit 100 all adopt N-type transistors, the first voltage terminal VGL maintains the first voltage of the input DC low level, and the second voltage terminal VGH maintains the input DC high level.
  • the second voltage, the first clock signal terminal CLK inputs the first clock signal, and the second clock signal terminal CLKA inputs the second clock signal.
  • the shift register unit 100 performs the following operations.
  • the first clock signal terminal CLK inputs a low level signal
  • the second clock signal terminal CLKA inputs a low level signal
  • the input terminal INPUT inputs a high level signal. Since the input terminal INTPUT inputs a high level signal, the third transistor T3 is turned on, so that the high level of the input terminal INPUT input charges the storage capacitor C1, and the potential of the pull-up node PU is pulled up to the first high level.
  • the sixth transistor T6 Since the second voltage terminal VGH maintains the input DC high level signal, the sixth transistor T6 remains turned on, and the high level input by the second voltage terminal VGH charges the pull-down node PD. Further, since the potential of the pull-up node PU is at the first high level, the seventh transistor T7 is turned on, thereby electrically connecting the pull-down node PD and the first voltage terminal VGL. In the design of the transistor, the sixth transistor T6 and the seventh transistor T7 can be configured (for example, the size ratio of the two, the threshold voltage, etc.). When both T6 and T7 are turned on, the potential of the pull-down node PD is pulled down. At a lower level, the low level does not turn on the eighth transistor T8 and the ninth transistor T9. It should be noted that the potential level of the signal timing diagram shown in FIG. 7 is only illustrative and does not represent a true potential value.
  • the pull-up node PU Since the pull-up node PU is at the first high level, the first transistor T1 and the fifth transistor T5 are turned on, and at this time, the first clock signal terminal CLK and the second clock signal terminal CLKA input a low level signal, so at this stage, The first output terminal OUT1 and the second output terminal OUT2 each output a low level signal.
  • the first clock signal terminal CLK inputs a high level signal
  • the second clock signal terminal CLKA inputs a high level signal
  • the input terminal INPUT input signal continues to remain at a high level for a period of time and then falls to a low level.
  • the pull-up node PU is at a high level
  • the first transistor T1 and the fifth transistor T5 are kept turned on. Since the first clock signal terminal CLK and the second clock signal terminal CLKA both input a high level at this stage, the first The output terminal OUT1 and the second output terminal OUT2 output a high level signal.
  • the high level can pass through the parasitic capacitance of the fifth transistor T5 (including the parasitic capacitance between the gate and the first electrode, and the gate and the The parasitic capacitance between the two levels is coupled to increase the potential of the pull-up node PU.
  • the voltage level of the high level input to the pull-up node PU of the first clock signal terminal CLK can be calculated by Equation 2:
  • ⁇ V_PU1 ⁇ V_CLK ⁇ C_T5/C_PU;
  • ⁇ V_PU1 is the voltage amplitude of the pull-up node PU coupled due to the change of the potential of the first clock signal terminal CLK
  • ⁇ V_CLK is the voltage amplitude change amount of the first clock signal end
  • C_T5 is the parasitic capacitance value of the fifth transistor T5.
  • C_PU is the sum of all the capacitances connected to the pull-up node PU.
  • the high level can pass through the parasitic capacitance of the first transistor T1 (including the parasitic capacitance between the gate and the first electrode, and the gate and the The parasitic capacitance between the two levels) and the storage capacitor C1 are coupled to increase the potential of the pull-up node PU.
  • the voltage level of the high level input to the pull-up node PU of the second clock signal terminal CLKA can be calculated by Equation 3:
  • ⁇ V_PU2 ⁇ V_CLKA ⁇ (C_T1+C_C1)/C_PU;
  • ⁇ V_PU2 is the voltage amplitude of the pull-up node PU coupled due to the change of the potential of the second clock signal terminal CLKA
  • ⁇ V_CLKA is the voltage amplitude change amount of the second clock signal end
  • C_T1 is the parasitic capacitance value of the first transistor T1
  • C_C1 is the capacitance value of the storage capacitor C1
  • C_PU is the sum of all the capacitances connected to the pull-up node PU.
  • the high level input to the pull-up node PU through the first clock signal terminal CLK and the second clock signal terminal CLKA causes the potential to be coupled to the second high voltage. level.
  • the potential of the pull-up node PU is coupled to rise to a second high level, so that the conduction of the fifth transistor T5 is more sufficient. Since the potential of the pull-up node PU is at a high level, the seventh transistor T7 continues to be turned on, so that the potential of the pull-down node PD continues to remain at a low level. Since the potential of the pull-down node PD is at a low level, the second transistor T2, the eighth transistor T8, and the ninth transistor T9 remain in an off state, thereby not affecting the potential of the pull-up node PU and the shift register unit normally outputting the shift signal.
  • the signal input from the first clock signal terminal CLK changes from a high level to a low level, and the second clock signal terminal CLKA continues to maintain an input high level signal.
  • the high-level signal input by the first clock signal terminal CLK is similar to the coupling of the pull-up node PU, because the signal input from the first clock signal terminal CLK changes from the high level at this stage.
  • Low level the potential of the pull-up node PU is coupled to reduce a small amplitude to a high level (as indicated by the dashed oval in FIG. 7, the high level is greater than the first high level and less than the second high level),
  • the voltage amplitude of the reduced coupling can be calculated using Equation 2.
  • the fifth transistor T5 Since the potential of the pull-up node PU is still at a high level, the fifth transistor T5 remains on, and the first output terminal OUT1 discharges to the first clock signal terminal CLK at a low level through the fifth transistor T5, and discharges, the first output The potential of terminal OUT1 drops to a low level. At the same time, the first transistor T1 remains on, and the second output terminal OUT2 outputs a high level signal input by the second clock signal terminal CLKA.
  • the signal input from the second clock signal terminal CLKA changes from a high level to a low level.
  • the high-level signal input from the second clock signal terminal CLKA is similar to the rise of the pull-up node PU, because the signal input from the second clock signal terminal CLKA changes from the high level at this stage.
  • Low level the potential of the pull-up node PU is coupled to the first high level, and the voltage amplitude of the coupling reduction can be calculated by Equation 3.
  • the first transistor T1 Since the potential of the pull-up node PU is still at a high level, the first transistor T1 remains on, and the second output terminal OUT2 discharges to the second clock signal terminal CLKA at a low level through the first transistor T1, and discharges, the second output The potential of terminal OUT2 drops to a low level.
  • Equation 2 and Equation 3 it can be seen from Equation 2 and Equation 3 that in the case where the parameters of the first transistor T1 and the fifth transistor T5 are determined, the proportional relationship between ⁇ V_PU1 and ⁇ V_PU2 can be adjusted by adjusting the capacitance value C_C1 of the storage capacitor C1, thereby controlling Pull the potential of the node PU in the third phase C.
  • the fourth transistor T4 is turned on, the pull-up node PU is electrically connected to the first voltage terminal VGL, and the potential of the pull-up node PU is pulled down to a low level, thereby The first transistor T1 and the fifth transistor T5 are turned off.
  • the seventh transistor T7 is turned off, the discharge path of the pull-down node PD is turned off, and the potential of the pull-down node PD is charged to a high level, thereby making the eighth transistor T8 and the second transistor T2
  • the ninth transistor T9 is turned on, respectively pulling the potential of the pull-up node PU, the second output terminal OUT2 and the first output terminal OUT1 to the low level input by the first voltage terminal VGL, further eliminating the shift register unit in the non-
  • the output stage has its output (including the first output terminal OUT1 and the second output terminal OUT2) and noise that may be generated at the pull-up node PU.
  • the shift register unit 100 shown in FIG. 5 is in operation, for example, as shown in FIG. 7, in the third stage C and the fourth stage D, the first The falling edge of the signal (first clock signal) input from the clock signal terminal CLK is earlier than the falling edge timing of the signal (second clock signal) input from the second clock signal terminal CLKA.
  • the potential of the pull-up node PU is first decreased by a small amplitude (as indicated by a broken line ellipse in FIG. 7), so that the first output is made.
  • the terminal OUT1 is discharged, the potential of the pull-up node PU can be maintained at a higher potential (compared to the dotted ellipse in FIG. 2).
  • the rising edge timing of the signal (first clock signal) input by the first clock signal terminal CLK and the signal input by the second clock signal terminal CLKA is consistent at all times, and embodiments of the present disclosure include, but are not limited to, such a situation.
  • the rising edge of the signal input by the first clock signal terminal CLK may be earlier or later than the rising of the signal (second clock signal) input by the second clock signal terminal CLKA.
  • the potentials of the shift register unit shown in FIG. 1 and the pull-up node PU in the shift register unit shown in FIG. 5 are simulated, and the simulation results are shown in FIG.
  • the dotted line in FIG. 8 corresponds to the potential of the pull-up node PU in FIG. 1
  • the solid line corresponds to the potential of the pull-up node PU in FIG. 5
  • the abscissa is time
  • the ordinate is voltage.
  • the high potential can increase the discharge speed of the first output terminal OUT1, thereby lowering the first output terminal OUT1.
  • the falling edge time of the output signal since the potential of the pull-up node PU can be maintained at a higher potential, the high potential can increase the discharge speed of the first output terminal OUT1, thereby lowering the first output terminal OUT1. The falling edge time of the output signal.
  • the falling edge time of the output signal of the first output terminal OUT1 described in the embodiment of the present disclosure refers to: the output signal is used from the 90% of the high level amplitude to 10% of the high level amplitude. time.
  • the output signals of the shift register unit shown in FIG. 1 and the first output terminal OUT1 in the shift register unit shown in FIG. 5 are simulated, and the simulation results are shown in FIG.
  • the dotted line in FIG. 9 corresponds to the output signal of the first output terminal OUT1 in FIG. 1
  • the solid line corresponds to the output signal of the first output terminal OUT1 in FIG. 5,
  • the abscissa is time
  • the ordinate is voltage.
  • the falling edge time of the solid curve is 1.1 ⁇ s
  • the falling edge time of the dashed curve is 1.8 ⁇ s. From the simulation results, it can be concluded that the first output can be made by using the shift register unit as shown in FIG.
  • the falling edge time of the output signal of the terminal OUT1 is lowered, so that the charging time can be increased and the driving capability can be improved.
  • the gate driving circuit 10 includes a plurality of cascaded shift register units 100, for example, the shift register unit 100 can be The shift register unit provided in the above embodiment, for example, the shift register unit 100 has only the first output terminal OUT1.
  • the gate driving circuit 10 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scan driving function.
  • the input terminals INPUT of the remaining stages of shift register units are connected to the first output terminal OUT1 of the shift register unit of the previous stage.
  • the reset terminal RST of the remaining stages of the shift register unit is connected to the first output terminal OUT1 of the shift register unit of the next stage.
  • the input INPUT of the first stage shift register unit can be configured to receive the trigger signal STV
  • the reset terminal RST of the last stage shift register unit can be configured to receive the reset signal RESET.
  • the gate driving circuit 10 can be disposed on one side of the display panel.
  • the display panel includes N rows of gate lines (N is an integer greater than zero), and the first output terminal OUT1 of each stage of the shift register unit 100 in the gate driving circuit 10 may be configured to sequentially and the N rows of gates Line connections for outputting progressive scan signals.
  • the gate driving circuit 10 may be disposed on both sides of the display panel to implement the bilateral driving.
  • the embodiment of the present disclosure does not limit the manner in which the gate driving circuit 10 is disposed, for example, the display panel.
  • One side is provided with a gate driving circuit 10 for driving odd-numbered gate lines
  • the other side of the display panel is provided with a gate driving circuit 10 for driving even-numbered gate lines.
  • the clock signal terminals (the first clock signal terminal CLK and the second clock signal terminal CLKA) in each shift register unit 100 can be passed through the four system clock signals CLK1, CLK2, CLKA1, and CLKA2. Provide a clock signal.
  • the gate drive circuit 10 may further include a timing controller 200.
  • the timing controller 200 is configured, for example, to provide clock signals (CLK1, CLK2, CLKA1, CLKA2) to the shift register units 100 of the stages, and the timing controller 200 can also be configured to provide the trigger signal STV and the reset signal RESET.
  • the falling edge time of the signal outputted by the first output terminal OUT1 can be reduced, and the charging time of the pixel unit in the display panel can be increased, thereby improving the driving capability of the gate driving circuit.
  • At least one embodiment of the present disclosure further provides a gate driving circuit 10, as shown in FIG. 11, which is different from the gate driving circuit shown in FIG. 10, and the gate driving circuit 10 of FIG.
  • the shift register unit 100 has a second output terminal OUT2 in addition to the first output terminal OUT1.
  • the input terminal INPUT of the remaining stages of the shift register unit is connected to the second output terminal OUT2 of the shift register unit of the previous stage.
  • the reset terminal RST of the remaining stages of the shift register unit is connected to the second output terminal OUT2 of the shift register unit of the next stage.
  • the input INPUT of the first stage shift register unit can be configured to receive the trigger signal STV
  • the reset terminal RST of the last stage shift register unit can be configured to receive the reset signal RESET.
  • the first output terminal OUT1 of each stage shift register unit 100 outputs a progressive scan signal, and the output signal of the second output terminal OUT2 can be used.
  • the reset signal of the shift register unit of the first stage and the input signal of the shift register unit of the next stage are performed. In this way, the load capacity of the gate drive circuit 10 can be improved.
  • At least one embodiment of the present disclosure also provides a display device 1, as shown in FIG. 12, which includes any of the gate drive circuits 10 provided in the above embodiments.
  • the display device in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc., having any display function.
  • the display device 1 may further include other conventional components such as a display panel, and embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive any of the shift register units 100 provided in the embodiments of the present disclosure and a gate driving circuit employing the shift register unit.
  • the driving method includes the following operations.
  • the input circuit 110 charges the pull-up node PU in response to the input signal, and the output circuit 130 outputs the low level of the first clock signal to the first output terminal OUT1.
  • the potential of the pull-up node PU is boosted by the high level coupling of the first clock signal and the second clock signal, and the output circuit 130 outputs the high level of the first clock signal to the first output terminal OUT1.
  • the potential of the pull-up node PU is reduced by the low level coupling of the first clock signal, and the first output terminal OUT1 is discharged through the output circuit 130.
  • the potential of the pull-up node PU is further coupled low by the low level of the second clock signal.
  • the pull-up node reset circuit 120 resets the pull-up node PU under the control of the reset signal.
  • the falling edge of the first clock signal is earlier than the falling edge of the second clock signal.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive the shift register unit 100 having the second output terminal OUT2 provided in the embodiment of the present disclosure.
  • the driving method includes the following operations.
  • the input circuit 110 charges the pull-up node PU in response to the input signal, the output circuit 130 outputs a low level of the first clock signal to the first output terminal OUT1, and the coupling circuit 140 outputs the low voltage of the second clock signal. Flat to the second output terminal OUT2.
  • the potential of the pull-up node PU is pulled high by the high-level coupling of the first clock signal and the second clock signal, and the output circuit 130 outputs the high level of the first clock signal to the first output terminal OUT1, the coupling circuit 140 outputs a high level of the second clock signal to the second output terminal OUT2.
  • the potential of the pull-up node PU is pulled low by the low level coupling of the first clock signal, the first output terminal OUT1 is discharged to the low level through the output circuit 130, and the coupling circuit 140 outputs the high voltage of the second clock signal. Flat to the second output terminal OUT2.
  • the potential of the pull-up node PU is further coupled low by the low level of the second clock signal, and the second output terminal OUT2 is discharged to the low level through the coupling circuit 140.
  • the pull-up node reset circuit 120 resets the pull-up node PU under the control of the reset signal.
  • the falling edge of the first clock signal is earlier than the falling edge of the second clock signal.
  • the rising edge timing of the first clock signal is consistent with the rising edge timing of the second clock signal; or, in the second phase, the rising edge timing of the first clock signal It is earlier or later than the rising edge of the second clock signal.
  • the driving method of the shift register unit provided in the embodiment of the present disclosure can reduce the falling edge time of the output signal of the first output terminal OUT1 and increase the charging time of the pixel unit in the display panel, thereby improving the driving capability.
  • the high level and the low level of each port input are relative.
  • a high level indicates a higher voltage range (for example, a high level can be 5V, 10V, or other suitable voltage), and multiple high levels of multiple ports can be the same or different, for example, the high level can be Turn on the N-type transistor and turn off the P-type transistor.
  • a low level indicates a lower voltage range (eg, a low level can be 0V, -5V, -10V, or other suitable voltage), and multiple low levels of multiple ports can be the same or different.
  • the low level can turn on the P-type transistor and turn off the N-type transistor.
  • the minimum value of the high level is larger than the maximum value of the low level.

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Abstract

一种移位寄存器单元(100)、栅极驱动电路(10)、显示装置(1)以及驱动方法。移位寄存器单元(100)包括输入电路(110)、上拉节点复位电路(120)、输出电路(130)和耦合电路(140)。输入电路(110)被配置为响应于输入信号对上拉节点(PU)进行充电；上拉节点复位电路(120)被配置为响应于复位信号对上拉节点(PU)进行复位；输出电路(130)被配置为在上拉节点(PU)的电平的控制下，将第一时钟信号输出至第一输出端(OUT1)；耦合电路(140)被配置为响应于第二时钟信号，对上拉节点(PU)的电位进行耦合控制。移位寄存器单元可以减小第一输出端(OUT1)输出信号的下降沿时间，提高驱动能力。

Description

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
本申请要求于2017年9月21日递交的中国专利申请第201710858352.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置以及驱动方法。
背景技术
在显示技术领域，例如液晶显示器的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、上拉节点复位电路、输出电路和耦合电路。所述输入电路被配置为响应于输入信号对上拉节点进行充电；所述上拉节点复位电路被配置为响应于复位信号对所述上拉节点进行复位；所述输出电路被配置为在所述上拉节点的电平的控制下，将第一时钟信号输出至第一输出端；所述耦合电路被配置为响应于第二时钟信号，对所述上拉节点的电位进行耦合控制。
例如，本公开一实施例提供的移位寄存器单元还包括下拉节点控制电路、上拉节点降噪电路和输出降噪电路。所述下拉节点控制电路被配置为 对下拉节点的电平进行控制；所述上拉节点降噪电路被配置为在所述下拉节点的电平的控制下，对所述上拉节点进行降噪；所述输出降噪电路被配置为在所述下拉节点的电平的控制下，对所述第一输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述耦合电路包括第一晶体管和存储电容。所述第一晶体管的栅极和存储电容的第一极被配置为和所述上拉节点连接，所述第一晶体管的第一极被配置为和第二时钟信号端连接以接收所述第二时钟信号，所述第一晶体管的第二极被配置为和所述存储电容的第二极连接。
例如，本公开一实施例提供的移位寄存器单元还包括第二输出端。所述耦合电路还被配置为输出所述第二时钟信号至所述第二输出端，所述第二输出端被配置为和所述第一晶体管的第二极连接。
例如，本公开一实施例提供的移位寄存器单元还包括耦合复位电路。所述耦合复位电路被配置为在所述下拉节点的电平的控制下，对所述第二输出端进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述耦合复位电路包括：第二晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述第二输出端连接，第二极被配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括：第三晶体管，其栅极和第一极连接，且被配置为和输入端连接以接收所述输入信号，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
例如，在本公开一实施例提供的移位寄存器单元中，所述上拉节点复位电路包括：第四晶体管，其栅极被配置为和复位端连接以接收所述复位信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括：第五晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和第一时钟信号端连接以接收所述第一时钟信号，第二极被配置为和所述第一输出端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉节点控 制电路包括：第六晶体管，其栅极和第一极连接，且被配置为和第二电压端连接以接收第二电压，第二极被配置为和所述下拉节点连接；以及第七晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和所述下拉节点连接，第二极被配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述上拉节点降噪电路包括：第八晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述上拉节点连接以对所述上拉节点进行降噪，第二极被配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出降噪电路包括：第九晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述第一输出端连接，第二极被配置为和第一电压端连接以接收第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开实施例所述的移位寄存器单元。除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第一输出端连接；除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的第一输出端连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开实施例所述的移位寄存器单元。除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第二输出端连接；除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的第二输出端连接。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例所述的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：第一阶段，所述输入电路响应于所述输入信号对所述上拉节点进行充电，所述输出电路输出所述第一时钟信号的低电平至所述第一输出端；第二阶段，所述上拉节点的电位被所述第一时钟信号和所述第二时钟信号的高电平耦合升高，所述输出电路输出所述第一时钟信号的高电平至所述第一输出端；第三阶段，所述上拉节点的电位被所述第一时钟信号的低电平耦合降低，所述第一输出端通过所述输出电路放电；第四阶段，所述上拉节点 的电位被所述第二时钟信号的低电平进一步耦合拉低；第五阶段，所述上拉节点复位电路在所述复位信号的控制下对所述上拉节点进行复位；其中，在所述第三阶段和所述第四阶段中，所述第一时钟信号的下降沿时刻早于所述第二时钟信号的下降沿时刻。
例如，在本公开一实施例提供的驱动方法中，在所述第二阶段中，所述第一时钟信号的上升沿时刻与所述第二时钟信号的上升沿时刻保持一致。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：第一阶段，所述输入电路响应于所述输入信号对所述上拉节点进行充电，所述输出电路输出所述第一时钟信号的低电平至所述第一输出端，所述耦合电路输出所述第二时钟信号的低电平至所述第二输出端；第二阶段，所述上拉节点的电位被所述第一时钟信号和所述第二时钟信号的高电平耦合拉高，所述输出电路输出所述第一时钟信号的高电平至所述第一输出端，所述耦合电路输出所述第二时钟信号的高电平至所述第二输出端；第三阶段，所述上拉节点的电位被所述第一时钟信号的低电平耦合拉低，所述第一输出端通过所述输出电路放电至低电平，所述耦合电路输出所述第二时钟信号的高电平至所述第二输出端；第四阶段，所述上拉节点的电位被所述第二时钟信号的低电平进一步耦合拉低，所述第二输出端通过所述耦合电路放电至低电平；第五阶段，所述上拉节点复位电路在所述复位信号的控制下对所述上拉节点进行复位；在所述第三阶段和所述第四阶段中，所述第一时钟信号的下降沿时刻早于所述第二时钟信号的下降沿时刻。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种移位寄存器单元的电路示意图；
图2为对应于图1中所示的移位寄存器单元工作时的信号时序图；
图3为本公开一实施例的一个示例提供的一种移位寄存器单元的示意框图；
图4为本公开一实施例的另一个示例提供的一种移位寄存器单元的示 意框图；
图5为图4中所示的移位寄存器单元的一种实现示例的电路示意图；
图6为图3中所示的移位寄存器单元的一种实现示例的电路示意图；
图7为对应于图5中所示的移位寄存器单元工作时的信号时序图；
图8为对图1和图5中所示的移位寄存器单元中的上拉节点PU的电位进行仿真的示意图；
图9为对图1和图5中所示的移位寄存器单元中的第一输出端OUT1的输出信号进行仿真的示意图；
图10为本公开一实施例提供的一种栅极驱动电路的示意图；
图11为本公开一实施例提供的另一种栅极驱动电路的示意图；以及
图12为本公开一实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate driver On Array)技术，即将栅极驱动电路通过薄膜晶体管工艺集成在显示面板上，从而可以实现窄边框和降低装配成本等优势。该显示面板可以为液晶 显示(LCD)面板或有机发光二极管(OLED)显示面板。
图1示出了一种移位寄存器单元的电路结构，该移位寄存器单元可以被级联以形成栅极驱动电路。如图1所示，该移位寄存器单元包括九个晶体管(T1至T9)和存储电容(C1)。
第一晶体管T1，其栅极和上拉节点PU连接，第一极和第一时钟信号端CLK连接，第二极和第二输出端OUT2连接。
第二晶体管T2，其栅极和下拉节点PD连接，第一极和第二输出端OUT2连接，第二极和第一电压端VGL连接。
第三晶体管T3，其栅极和第一极连接且被配置为和输入端INPUT连接，第二极和上拉节点PU连接。
第四晶体管T4，其栅极和复位端RST连接，第一极和上拉节点PU连接，第二极和第一电压端VGL连接。
第五晶体管T5，其栅极和上拉节点PU连接，第一极和第一时钟信号端CLK连接，第二极和第一输出端OUT1连接。
第六晶体管T6，其栅极和第一极连接且被配置为和第二电压端VGH(例如保持输入直流高电平信号)连接，第二极和下拉节点PD连接。
第七晶体管T7，其栅极和上拉节点PU连接，第一极和下拉节点PD连接，第二极和第一电压端VGL连接。
第八晶体管T8，其栅极和下拉节点PD连接，第一极和上拉节点PU连接，第二极和第一电压端VGL(例如保持输入直流低电平信号)连接。
第九晶体管T9，其栅极和下拉节点PD连接，第一极和第一输出端OUT1连接，第二极和第一电压端VGL连接。
存储电容C1，其第一极和上拉节点PU连接，第二极和第一输出端OUT1连接。
例如上述晶体管均为N型晶体管。下面也以N型晶体管为例进行说明，但是本公开的实施例不限于这种情形，例如这些晶体管中至少部分可以替换为P型晶体管。
下面结合图2所示的信号时序图来说明图1所示的移位寄存器单元的工作原理，在图2所示的第一阶段A、第二阶段B、第三阶段C以及第四阶段D共四个阶段中，该移位寄存器单元进行如下操作。
在第一阶段A，第一时钟信号端CLK输入低电平信号，输入端INPUT 输入高电平信号。由于输入端INPUT输入高电平信号，第三晶体管T3导通，使得输入端INPUT输入的高电平对存储电容C1进行充电，上拉节点PU的电位被上拉至第一高电平。
例如第二电压端VGH可以设置为保持输入直流高电平信号，第六晶体管T6保持导通，第二电压端VGH输入的高电平对下拉节点PD进行充电。又由于上拉节点PU的电位为第一高电平，第七晶体管T7导通，从而使得下拉节点PD和第一电压端VGL电连接。这里，例如第一电压端VGL可以设置为保持输入直流低电平信号。在晶体管的设计上，可以将第六晶体管T6和第七晶体管T7被配置为(例如对二者的尺寸比、阈值电压等配置)在T6和T7均导通时，下拉节点PD的电位被下拉到一个较低的电平，该低电平不会使第八晶体管T8开启。需要说明的是，图2中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
由于上拉节点PU处于第一高电平，第一晶体管T1和第五晶体管T5导通，此时第一时钟信号端CLK输入低电平，所以在此阶段，第一输出端OUT1和第二输出端OUT2均输出该低电平信号。
在第二阶段B，第一时钟信号端CLK输入高电平信号，输入端INPUT输入低电平信号。由于输入端INPUT输入低电平信号，第三晶体管T3截止，上拉节点PU保持上一阶段的第一高电平，从而使得第一晶体管T1和第五晶体管T5保持导通，由于在此阶段第一时钟信号端CLK输入高电平，所以第一输出端OUT1和第二输出端OUT2输出该高电平信号。
同时，由于第一时钟信号端CLK、第一输出端OUT1以及第二输出端OUT2为高电平，该高电平可以通过第一晶体管T1的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)、第五晶体管T5的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)和存储电容C1对上拉节点PU的电位进行耦合升高。上拉节点PU耦合的电压幅值可以由公式1计算得到：
ΔV_PU＝ΔV_CLK×(C_T1+C_T5+C_C1)/C_PU；    (1)
其中，ΔV_PU为上拉节点PU耦合的电压幅值，ΔV_CLK为第一时钟信号端的电压幅值变化量，C_T1为第一晶体管T1的寄生电容值，C_T5为第五晶体管T5的寄生电容值，C_C1为存储电容C1的电容值，C_PU为和上拉节点PU连接的所有电容总和。
上拉节点PU的电位被耦合升高，达到第二高电平，使得第五晶体管T5的导通更充分。由于上拉节点PU的电位为高电平，第七晶体管T7继续导通，使得下拉节点PD的电位继续保持在低电平。由于下拉节点PD的电位为低电平，第二晶体管T2、第八晶体管T8和第九晶体管T9保持截止状态，从而不会影响上拉节点PU的电位以及移位寄存器单元正常输出移位信号。
在第三阶段C，第一时钟信号端CLK输入的信号由高电平变为低电平，输入端INPUT继续输入低电平。这里与第二阶段对上拉节点PU的耦合升高类似，由于第一时钟信号端CLK输入的信号变为低电平，上拉节点PU的电位被耦合降低至第一高电平(如图2中虚线椭圆标示)，耦合降低的电压幅值依然可以采用公式1计算获得。
同时，由于上拉节点PU的电位依然为高电平，第五晶体管T5保持开启，第一输出端OUT1通过第五晶体管T5向处于低电平的第一时钟信号端CLK放电；同样的，第一晶体管T1保持开启，第二输出端OUT2通过第一晶体管T1向处于低电平的第一时钟信号端CLK放电。通过放电，第一输出端OUT1和第二输出端OUT2的电位下降为低电平。
在第四阶段D，由于复位端RST输入高电平信号，第四晶体管T4导通，上拉节点PU与第一电压端VGL电连接，上拉节点PU的电位被下拉到低电平，从而第一晶体管T1和第五晶体管T5截止。
由于上拉节点PU的电位处于低电平，第七晶体管T7截止，下拉节点PD的放电路径被截止，下拉节点PD的电位被充电至高电平，由此使得第八晶体管T8、第二晶体管T2和第九晶体管T9导通，分别将上拉节点PU、第二输出端OUT2以及第一输出端OUT1的电位下拉到第一电压端VGL输入的低电平，进一步消除了移位寄存器单元在非输出阶段其输出端(包括第一输出端OUT1和第二输出端OUT2)和上拉节点PU处可能产生的噪声。
例如，图1中所示的移位寄存器单元可以被级联以形成栅极驱动电路，该栅极驱动电路用于驱动显示面板时，每一级移位寄存器单元例如对应一条栅线。第一输出端OUT1可以和对应栅线连接以提供逐行扫描信号，第二输出端OUT2可以和上一级移位寄存器单元的复位端RST以及下一级移位寄存器单元的输入端INPUT连接，分别提供复位信号和输入信号。采用这种连接方式可以提高移位寄存器单元的负载能力。
上述移位寄存器单元在工作时，第一输出端OUT1在通过第五晶体管T5 放电时，由于上拉节点PU的电位下降，会影响第五晶体管T5的导通程度，进而影响第一输出端OUT1的放电速度。第一输出端OUT1放电速度越慢，其下降沿时间就越长。
在高分辨率LCD(Liquid Crystal Display)产品中，可以用于充电的时间大幅度缩减，例如对于采用α-Si(非晶硅)TFT(薄膜晶体管)作为像素开关元件且分辨率为8K的显示产品，一行像素单元的开启时间例如只有3.7μs，实际有效的充电时间则更少，因此充电时间0.1μs量级的增加都可以对充电率有明显的提升。
本公开至少一实施例提供一种移位寄存器单元，其包括输入电路、上拉节点复位电路、输出电路和耦合电路。该输入电路被配置为响应于输入信号对上拉节点进行充电；该上拉节点复位电路被配置为响应于复位信号对上拉节点进行复位；该输出电路被配置为在上拉节点的电平的控制下，将第一时钟信号输出至第一输出端；该耦合电路被配置为响应于第二时钟信号，对上拉节点的电位进行耦合控制。
本公开至少一实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置以及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置以及驱动方法，可以通过耦合电路控制上拉节点的电位，使其在第一输出端放电时保持在一个较高的电位，从而可以减小第一输出端输出信号的下降沿时间，增大显示面板中的像素单元的充电时间，从而可以提高驱动能力。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开实施例的一个示例提供一种移位寄存器单元100，如图3所示，该移位寄存器单元100包括输入电路110、上拉节点复位电路120、输出电路130和耦合电路140。
该输入电路110被配置为响应于输入信号对上拉节点PU进行充电。例如，该输入电路110可以被配置为使上拉节点PU和输入端INPUT电连接，从而可以使输入端INPUT输入的高电平信号对上拉节点PU进行充电。
该上拉节点复位电路120被配置为响应于复位信号对上拉节点PU进行复位。例如，该上拉节点复位电路120可以被配置为和复位端RST连接，从而可以在复位端RST输入的复位信号的控制下，使得上拉节点PU和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL，从而可以对上 拉节点PU进行下拉复位。需要说明的是，第一电压端VGL例如可以被配置为保持输入直流低电平信号，以下本公开的各实施例与此相同，不再赘述。
输出电路130被配置为在上拉节点PU的电平的控制下，将第一时钟信号输出至第一输出端OUT1。例如，该输出电路130可以被配置为在上拉节点PU的电平的控制下，使第一时钟信号端CLK和第一输出端OUT1电连接，从而可以将第一时钟信号端CLK输入的第一时钟信号输出至第一输出端OUT1。同时，第一输出端OUT1还可以通过输出电路130进行放电。
该耦合电路140被配置为响应于第二时钟信号，对上拉节点PU的电位进行耦合控制。例如，该耦合电路140可以和第二时钟信号端CLKA连接，从而在第二时钟信号端CLKA输入的第二时钟信号为高电平时，耦合电路140对上拉节点PU的电位进行耦合控制使其电位升高；在第二时钟信号端CLKA输入的第二时钟信号为低电平时，耦合电路140对上拉节点PU的电位进行耦合控制使其电位降低。
例如，可以采用多个级联的上述移位寄存器单元100构成一栅极驱动电路。当使用该栅极驱动电路驱动显示面板时，可以通过输出电路130和耦合电路140，以及在第一时钟信号和第二时钟信号的相互配合下，对上拉节点PU的电位进行控制，使其在第一输出端OUT1放电时保持在一个较高的电位，从而可以减小第一输出端OUT1输出信号的下降沿时间，增大显示面板中的像素单元的充电时间，从而可以提高驱动能力。
例如，如图4所示，在本实施例的另一个示例中，该移位寄存器单元100还可以包括下拉节点控制电路150、上拉节点降噪电路160和输出降噪电路170。
该下拉节点控制电路150被配置为对下拉节点PD的电平进行控制，进而对上拉节点降噪电路160和输出降噪电路170进行控制。
该上拉节点降噪电路160被配置为在下拉节点PD的电平的控制下，对上拉节点PU进行降噪。例如，该上拉节点降噪电路160可以被配置为和第一电压端VGL连接，以在下拉节点PD的电平的控制下，使上拉节点PU和第一电压端VGL电连接，从而对上拉节点PU进行下拉降噪。
该输出降噪电路170被配置为在下拉节点PU的电平的控制下，对第一输出端OUT1进行降噪。例如，该输出降噪电路170可以被配置为在下拉节点PD的电平的控制下，使第一输出端OUT1和第一电压端VGL电连接，从 而对第一输出端OUT1进行下拉降噪。
例如，如图4所示，在本实施例的另一个示例中，该移位寄存器单元100还可以包括第二输出端OUT2和耦合复位电路180。
耦合电路140还被配置为输出第二时钟信号至第二输出端OUT2。例如，当图4中所示的移位寄存器单元100被级联以形成栅极驱动电路时，第二输出端OUT2可以和上一级移位寄存器单元的复位端RST以及下一级移位寄存器单元的输入端INPUT连接，分别提供复位信号和输入信号。采用两个输出端可以提高移位寄存器单元的负载能力。
该耦合复位电路180被配置为在下拉节点PU的电平的控制下，对第二输出端OUT2进行复位。例如，该耦合复位电路180可以被配置为和第一电压端VGL连接，以在下拉节点PU的电平的控制下，将第二输出端OUT2和第一电压端VGL电连接，从而实现对第二输出端OUT2的下拉复位。
例如，图4中所示的移位寄存器单元100在一个示例中可以实现为图5所示的电路结构。如图5所示，该移位寄存器单元100包括：第一至第九晶体管T1-T9以及存储电容C1。
如图5所示，在该示例中，更详细地，耦合电路140可以实现为包括第一晶体管T1和存储电容C1。第一晶体管T1的栅极被配置为和上拉节点PU连接，第一极被配置为和第二时钟信号端CLKA连接以接收第二时钟信号，第二极被配置为和第二输出端OUT2连接；存储电容C1的第一极被配置为和上拉节点PU连接，第二极被配置为和第二输出端OUT2连接。
耦合复位电路180可以实现为第二晶体管T2。第二晶体管T2的栅极被配置为和下拉节点PU连接，第一极被配置为和第二输出端OUT2连接，第二极被配置为和第一电压端VGL连接以接收第一电压。
需要说明的是，本公开的实施例中的第一电压端VGL例如保持输入直流低电平信号，将该直流低电平称为第一电压；第二电压端VGH例如保持输入直流高电平信号，将该直流高电平称为第二电压。以下各实施例与此相同，不再赘述。
输入电路110可以实现为第三晶体管T3。第三晶体管T3的栅极和第一极连接，且被配置为和输入端INPUT连接以接收输入信号，第二极被配置为和上拉节点PU连接以对上拉节点PU进行充电。
上拉节点复位电路120可以实现为第四晶体管T4。第四晶体管T4的栅 极被配置为和复位端RST连接以接收复位信号，第一极被配置为和上拉节点PU连接以对上拉节点PU进行复位，第二极被配置为和第一电压端VGL连接以接收第一电压。
输出电路130可以实现为第五晶体管T5。第五晶体管T5的栅极被配置为和上拉节点PU连接，第一极被配置为和第一时钟信号端CLK连接以接收第一时钟信号，第二极被配置为和第一输出端OUT1连接。
下拉节点控制电路150可以实现为包括第六晶体管T6和第七晶体管T7。第六晶体管T6的栅极和第一极连接，且被配置为和第二电压端VGH连接以接收第二电压，第二极被配置为和下拉节点PD连接；第七晶体管T7的栅极被配置为和上拉节点PU连接，第一极被配置为和下拉节点PD连接，第二极被配置为和第一电压端VGL连接以接收第一电压。
上拉节点降噪电路160可以实现为第八晶体管T8。第八晶体管T8的栅极被配置为和下拉节点PU连接，第一极被配置为和上拉节点PU连接以对上拉节点PU进行降噪，第二极被配置为和第一电压端VGL连接以接收第一电压。
输出复位电路170可以实现为第九晶体管T9。第九晶体管T9的栅极被配置为和下拉节点PD连接，第一极被配置为和第一输出端OUT1连接，第二极被配置为和第一电压端VGL连接以接收第一电压。
需要说明的是，对于图5中所示的移位寄存器单元100，第二晶体管T2和第九晶体管T9的栅极也可以不和下拉节点PD连接，而和复位端RST电连接，从而可以在复位端RST输入的复位信号的控制下，实现复位降噪的效果。本公开的实施例对此不作限定。
例如，对应于图3中所示的移位寄存器单元100，可以实现为图6所示的电路结构。图6中所示的各个晶体管以及存储电容C1的连接关系可以参考图5中所示的移位寄存器单元100中的相应描述，这里不再赘述。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，第一极可以是漏极，第二极可以是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，第一极可以是源极，第二极可以是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。
例如，如图5所示，该移位寄存器单元100中的晶体管均采用N型晶体管，第一电压端VGL保持输入直流低电平的第一电压，第二电压端VGH保持输入直流高电平的第二电压，第一时钟信号端CLK输入第一时钟信号，第二时钟信号端CLKA输入第二时钟信号。
下面结合图7所示的信号时序图，对图5所示的移位寄存器单元100的工作原理进行说明，在图7所示的第一阶段A、第二阶段B、第三阶段C、第四阶段D以及第五阶段E共五个阶段中，该移位寄存器单元100进行如下操作。
在第一阶段A，第一时钟信号端CLK输入低电平信号，第二时钟信号端CLKA输入低电平信号，输入端INPUT输入高电平信号。由于输入端INTPUT输入高电平信号，第三晶体管T3导通，使得输入端INPUT输入的高电平对存储电容C1进行充电，上拉节点PU的电位被上拉至第一高电平。
由于第二电压端VGH保持输入直流高电平信号，第六晶体管T6保持导通，第二电压端VGH输入的高电平对下拉节点PD进行充电。又由于上拉节点PU的电位为第一高电平，第七晶体管T7导通，从而使得下拉节点PD和第一电压端VGL电连接。在晶体管的设计上，可以将第六晶体管T6和第七晶体管T7被配置为(例如对二者的尺寸比、阈值电压等配置)在T6和T7均导通时，下拉节点PD的电位被下拉到一个较低的电平，该低电平不会使第八晶体管T8和第九晶体管T9开启。需要说明的是，图7中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
由于上拉节点PU处于第一高电平，第一晶体管T1和第五晶体管T5导通，此时第一时钟信号端CLK和第二时钟信号端CLKA输入低电平信号，所以在此阶段，第一输出端OUT1和第二输出端OUT2均输出低电平信号。
在第二阶段B，第一时钟信号端CLK输入高电平信号，第二时钟信号端CLKA输入高电平信号，输入端INPUT输入的信号继续保持一段时间的高电 平后下降为低电平。由于上拉节点PU为高电平，使得第一晶体管T1和第五晶体管T5保持导通，由于在此阶段第一时钟信号端CLK和第二时钟信号端CLKA均输入高电平，所以第一输出端OUT1和第二输出端OUT2输出高电平信号。
由于第一时钟信号端CLK、第一输出端OUT1为高电平，该高电平可以通过第五晶体管T5的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)对上拉节点PU的电位进行耦合升高。第一时钟信号端CLK输入的高电平对上拉节点PU耦合的电压幅值可以由公式2计算得到：
ΔV_PU1＝ΔV_CLK×C_T5/C_PU；     (2)
其中，ΔV_PU1为上拉节点PU由于第一时钟信号端CLK的电位的变化而耦合的电压幅值，ΔV_CLK为第一时钟信号端的电压幅值变化量，C_T5为第五晶体管T5的寄生电容值，C_PU为和上拉节点PU连接的所有电容总和。
由于第二时钟信号端CLKA、第二输出端OUT2为高电平，该高电平可以通过第一晶体管T1的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)以及存储电容C1对上拉节点PU的电位进行耦合升高。第二时钟信号端CLKA输入的高电平对上拉节点PU耦合的电压幅值可以由公式3计算得到：
ΔV_PU2＝ΔV_CLKA×(C_T1+C_C1)/C_PU；   (3)
其中，ΔV_PU2为上拉节点PU由于第二时钟信号端CLKA的电位的变化而耦合的电压幅值，ΔV_CLKA为第二时钟信号端的电压幅值变化量，C_T1为第一晶体管T1的寄生电容值，C_C1为存储电容C1的电容值，C_PU为和上拉节点PU连接的所有电容总和。
如上所述，在第二阶段B，通过第一时钟信号端CLK和第二时钟信号端CLKA输入的高电平对上拉节点PU的共同作用，使其电位被耦合升高至第二高电平。
上拉节点PU的电位被耦合升高，达到第二高电平，使得第五晶体管T5的导通更充分。由于上拉节点PU的电位为高电平，第七晶体管T7继续导通，使得下拉节点PD的电位继续保持在低电平。由于下拉节点PD的电位为低电平，第二晶体管T2、第八晶体管T8和第九晶体管T9保持截止状态，从 而不会影响上拉节点PU的电位以及移位寄存器单元正常输出移位信号。
在第三阶段C，第一时钟信号端CLK输入的信号由高电平变为低电平，第二时钟信号端CLKA继续保持输入高电平信号。这里与第二阶段B中，第一时钟信号端CLK输入的高电平信号对上拉节点PU的耦合升高类似，由于在此阶段第一时钟信号端CLK输入的信号从高电平变为低电平，上拉节点PU的电位被耦合降低一个较小幅度至一高电平(如图7中虚线椭圆标示，该高电平大于第一高电平且小于第二高电平)，耦合降低的电压幅值可以采用公式2计算获得。
由于上拉节点PU的电位依然为高电平，第五晶体管T5保持开启，第一输出端OUT1通过第五晶体管T5向处于低电平的第一时钟信号端CLK放电，通过放电，第一输出端OUT1电位下降为低电平。同时，第一晶体管T1保持开启，第二输出端OUT2输出第二时钟信号端CLKA输入的高电平信号。
在第四阶段D，第二时钟信号端CLKA输入的信号由高电平变为低电平。这里与第二阶段B中，第二时钟信号端CLKA输入的高电平信号对上拉节点PU的耦合升高类似，由于在此阶段第二时钟信号端CLKA输入的信号从高电平变为低电平，上拉节点PU的电位被耦合降低至第一高电平，耦合降低的电压幅值可以采用公式3计算获得。
由于上拉节点PU的电位依然为高电平，第一晶体管T1保持开启，第二输出端OUT2通过第一晶体管T1向处于低电平的第二时钟信号端CLKA放电，通过放电，第二输出端OUT2电位下降为低电平。
从公式2和公式3中可以看出，在第一晶体管T1和第五晶体管T5的参数确定的情形下，可以通过调整存储电容C1的电容值C_C1来调整ΔV_PU1和ΔV_PU2的比例关系，进而控制上拉节点PU在第三阶段C中的电位。
在第五阶段E，由于复位端RST输入高电平信号，第四晶体管T4导通，上拉节点PU与第一电压端VGL电连接，上拉节点PU的电位被下拉到低电平，从而使第一晶体管T1和第五晶体管T5截止。
由于上拉节点PU的电位处于低电平，第七晶体管T7截止，下拉节点PD的放电路径被截止，下拉节点PD的电位被充电至高电平，由此使得第八晶体管T8、第二晶体管T2和第九晶体管T9导通，分别将上拉节点PU、第二输出端OUT2以及第一输出端OUT1的电位下拉到第一电压端VGL输入的低电平，进一步消除了移位寄存器单元在非输出阶段其输出端(包括第一 输出端OUT1和第二输出端OUT2)和上拉节点PU处可能产生的噪声。
与图1中所示的移位寄存器单元相比，图5中所示的移位寄存器单元100在工作时，例如如图7所示，在第三阶段C和第四阶段D中，第一时钟信号端CLK输入的信号(第一时钟信号)的下降沿时刻早于第二时钟信号端CLKA输入的信号(第二时钟信号)的下降沿时刻。采用这样的时序设置，可以使该移位寄存器单元100工作在第三阶段C时，使上拉节点PU的电位先下降一个较小的幅度(如图7中虚线椭圆标示)，使得第一输出端OUT1在放电时，上拉节点PU的电位可以保持在一个较高的电位(与图2中虚线椭圆标示相比)。
需要说明的是，如图7所示，在第二阶段B中，第一时钟信号端CLK输入的信号(第一时钟信号)的上升沿时刻和第二时钟信号端CLKA输入的信号(第二时钟信号)的上升沿时刻保持一致，本公开的实施例包括但不限于这种情形。例如，在一个示例中，第一时钟信号端CLK输入的信号(第一时钟信号)的上升沿时刻还可以早于或晚于第二时钟信号端CLKA输入的信号(第二时钟信号)的上升沿时刻。
对图1中所示的移位寄存器单元和图5中所示的移位寄存器单元中的上拉节点PU的电位进行仿真，仿真结果如图8所示。图8中虚线对应图1中上拉节点PU的电位，实线对应图5中上拉节点PU的电位，横坐标为时间，纵坐标为电压。
如图7所示，在第三阶段C中，由于上拉节点PU的电位可以保持在一个较高的电位，该高电位可以提高第一输出端OUT1的放电速度，从而降低第一输出端OUT1输出信号的下降沿时间。
需要说明的是，本公开的实施例中描述的第一输出端OUT1输出信号的下降沿时间是指：输出信号从高电平幅值的90％下降到高电平幅值的10％所用的时间。
对图1中所示的移位寄存器单元和图5中所示的移位寄存器单元中的第一输出端OUT1的输出信号进行仿真，仿真结果如图9所示。图9中虚线对应图1中的第一输出端OUT1的输出信号，实线对应图5中的第一输出端OUT1的输出信号，横坐标为时间，纵坐标为电压。在一次仿真中，实线曲线的下降沿时间为1.1μs，虚线曲线的下降沿时间为1.8μs，从仿真结果可以得出，采用如图5所示的移位寄存器单元，可以使第一输出端OUT1的输 出信号的下降沿时间降低，从而可以增大充电时间，提高驱动能力。
本公开的至少一实施例还提供一种栅极驱动电路10，如图10所示，该栅极驱动电路10包括多个级联的移位寄存器单元100，例如该移位寄存器单元100可以采用上述实施例中提供的移位寄存器单元，例如该移位寄存器单元100只具有第一输出端OUT1。该栅极驱动电路10可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。
例如，如图10所示，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INPUT和上一级移位寄存器单元的第一输出端OUT1连接。除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端RST和下一级移位寄存器单元的第一输出端OUT1连接。例如，第一级移位寄存器单元的输入端INPUT可以被配置为接收触发信号STV，最后一级移位寄存器单元的复位端RST可以被配置为接收复位信号RESET。
例如，当采用该栅极驱动电路10驱动一显示面板时，可以将该栅极驱动电路10设置于显示面板的一侧。例如，该显示面板包括N行栅线(N为大于零的整数)，栅极驱动电路10中的各级移位寄存器单元100的第一输出端OUT1可以被配置为依序和该N行栅线连接，以用于输出逐行扫描信号。需要说明的是，还可以分别在显示面板的两侧设置该栅极驱动电路10，以实现双边驱动，本公开的实施例对栅极驱动电路10的设置方式不作限定，例如还可以在显示面板的一侧设置栅极驱动电路10以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路10以用于驱动偶数行栅线。
例如，如图10所示，可以通过四个***时钟信号CLK1、CLK2、CLKA1以及CLKA2向每个移位寄存器单元100中的时钟信号端(第一时钟信号端CLK和第二时钟信号端CLKA)提供时钟信号。
例如，如图10所示，栅极驱动电路10还可以包括时序控制器200。该时序控制器200例如被配置为向各级移位寄存器单元100提供时钟信号(CLK1，CLK2，CLKA1，CLKA2)，时序控制器200还可以被配置为提供触发信号STV以及复位信号RESET。
采用本实施例提供的栅极驱动电路10，可以降低第一输出端OUT1输出的信号的下降沿时间，增大显示面板中的像素单元的充电时间，从而可以提高该栅极驱动电路的驱动能力。
本公开的至少一实施例还提供一种栅极驱动电路10，如图11所示，与图10中所示的栅极驱动电路所不同的是，图11中的栅极驱动电路10采用的移位寄存器单元100除了第一输出端OUT1外，还具有第二输出端OUT2。
例如，如图11所示，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INPUT和上一级移位寄存器单元的第二输出端OUT2连接。除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端RST和下一级移位寄存器单元的第二输出端OUT2连接。例如，第一级移位寄存器单元的输入端INPUT可以被配置为接收触发信号STV，最后一级移位寄存器单元的复位端RST可以被配置为接收复位信号RESET。
在本实施例提供的栅极驱动电路10中，和上一实施例相同，各级移位寄存器单元100的第一输出端OUT1输出逐行扫描信号，而第二输出端OUT2的输出信号可以用作上一级移位寄存器单元的复位信号和下一级移位寄存器单元的输入信号。采用这种方式，可以提高该栅极驱动电路10的负载能力。
关于本实施例提供的栅极驱动电路的其他部分以及技术效果可以参考上一实施例中相应描述，这里不再赘述。
本公开的至少一实施例还提供一种显示装置1，如图12所示，该显示装置1包括上述实施例中提供的任一栅极驱动电路10。
需要说明的是，本实施例中的显示装置可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中提供的任一移位寄存器单元100以及采用该移位寄存器单元的栅极驱动电路。例如，该驱动方法包括如下操作。
在第一阶段，输入电路110响应于输入信号对上拉节点PU进行充电，输出电路130输出第一时钟信号的低电平至第一输出端OUT1。
在第二阶段，上拉节点PU的电位被第一时钟信号和第二时钟信号的高电平耦合升高，输出电路130输出第一时钟信号的高电平至第一输出端 OUT1。
在第三阶段，上拉节点PU的电位被第一时钟信号的低电平耦合降低，第一输出端OUT1通过输出电路130放电。
在第四阶段，上拉节点PU的电位被第二时钟信号的低电平进一步耦合拉低。
在第五阶段，上拉节点复位电路120在复位信号的控制下对上拉节点PU进行复位。
其中，在第三阶段和第四阶段中，第一时钟信号的下降沿时刻早于第二时钟信号的下降沿时刻。
需要说明的是，关于该驱动方法的详细描述可以参考本公开实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中提供的具有第二输出端OUT2的移位寄存器单元100。例如，该驱动方法包括如下操作。
在第一阶段，输入电路110响应于输入信号对上拉节点PU进行充电，输出电路130输出第一时钟信号的低电平至第一输出端OUT1，耦合电路140输出第二时钟信号的低电平至第二输出端OUT2。
在第二阶段，上拉节点PU的电位被第一时钟信号和第二时钟信号的高电平耦合拉高，输出电路130输出第一时钟信号的高电平至第一输出端OUT1，耦合电路140输出第二时钟信号的高电平至第二输出端OUT2。
在第三阶段，上拉节点PU的电位被第一时钟信号的低电平耦合拉低，第一输出端OUT1通过输出电路130放电至低电平，耦合电路140输出第二时钟信号的高电平至第二输出端OUT2。
在第四阶段，上拉节点PU的电位被第二时钟信号的低电平进一步耦合拉低，第二输出端OUT2通过耦合电路140放电至低电平。
在第五阶段，上拉节点复位电路120在复位信号的控制下对上拉节点PU进行复位。
其中，在第三阶段和第四阶段中，第一时钟信号的下降沿时刻早于第二时钟信号的下降沿时刻。
需要说明的是，关于该驱动方法的详细描述可以参考本公开实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
在上述实施例中，在第二阶段中，第一时钟信号的上升沿时刻与所述第二时钟信号的上升沿时刻保持一致；或者，在第二阶段中，第一时钟信号的上升沿时刻早于或晚于第二时钟信号的上升沿时刻。
本公开的实施例中提供的移位寄存器单元的驱动方法，可以减小第一输出端OUT1输出信号的下降沿时间，增大显示面板中的像素单元的充电时间，从而可以提高驱动能力。
需要说明的是，在本公开的实施例中，各个端口输入的高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个端口的多个高电平可以相同也可以不同，例如该高电平可以开启N型晶体管、关闭P型晶体管。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个端口的多个低电平可以相同也可以不同，例如该低电平可以开启P型晶体管、关闭N型晶体管。例如，高电平的最小值比低电平的最大值大。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种移位寄存器单元，包括：输入电路、上拉节点复位电路、输出电路和耦合电路；其中，
    所述输入电路被配置为响应于输入信号对上拉节点进行充电；
    所述上拉节点复位电路被配置为响应于复位信号对所述上拉节点进行复位；
    所述输出电路被配置为在所述上拉节点的电平的控制下，将第一时钟信号输出至第一输出端；
    所述耦合电路被配置为响应于第二时钟信号，对所述上拉节点的电位进行耦合控制。
  2. 根据权利要求1所述的移位寄存器单元，还包括下拉节点控制电路、上拉节点降噪电路和输出降噪电路，其中，
    所述下拉节点控制电路被配置为对下拉节点的电平进行控制；
    所述上拉节点降噪电路被配置为在所述下拉节点的电平的控制下，对所述上拉节点进行降噪；
    所述输出降噪电路被配置为在所述下拉节点的电平的控制下，对所述第一输出端进行降噪。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述耦合电路包括第一晶体管和存储电容；
    所述第一晶体管的栅极和存储电容的第一极被配置为和所述上拉节点连接，所述第一晶体管的第一极被配置为和第二时钟信号端连接以接收所述第二时钟信号，所述第一晶体管的第二极被配置为和所述存储电容的第二极连接。
  4. 根据权利要求3所述的移位寄存器单元，还包括第二输出端，其中，
    所述耦合电路还被配置为输出所述第二时钟信号至所述第二输出端，
    所述第二输出端被配置为和所述第一晶体管的第二极连接。
  5. 根据权利要求4所述的移位寄存器单元，还包括耦合复位电路，其中，
    所述耦合复位电路被配置为在所述下拉节点的电平的控制下，对所述 第二输出端进行复位。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述耦合复位电路包括：
    第二晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述第二输出端连接，第二极被配置为和第一电压端连接以接收第一电压。
  7. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述输入电路包括：
    第三晶体管，其栅极和第一极连接，且被配置为和输入端连接以接收所述输入信号，第二极被配置为和所述上拉节点连接以对所述上拉节点进行充电。
  8. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述上拉节点复位电路包括：
    第四晶体管，其栅极被配置为和复位端连接以接收所述复位信号，第一极被配置为和所述上拉节点连接以对所述上拉节点进行复位，第二极被配置为和第一电压端连接以接收第一电压。
  9. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述输出电路包括：
    第五晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和第一时钟信号端连接以接收所述第一时钟信号，第二极被配置为和所述第一输出端连接。
  10. 根据权利要求2-5任一所述的移位寄存器单元，其中，所述下拉节点控制电路包括：
    第六晶体管，其栅极和第一极连接，且被配置为和第二电压端连接以接收第二电压，第二极被配置为和所述下拉节点连接；以及
    第七晶体管，其栅极被配置为和所述上拉节点连接，第一极被配置为和所述下拉节点连接，第二极被配置为和第一电压端连接以接收第一电压。
  11. 根据权利要求2-5任一所述的移位寄存器单元，其中，所述上拉节点降噪电路包括：
    第八晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述上拉节点连接以对所述上拉节点进行降噪，第二极被配置为和第一 电压端连接以接收第一电压。
  12. 根据权利要求2-5任一所述的移位寄存器单元，其中，所述输出降噪电路包括：
    第九晶体管，其栅极被配置为和所述下拉节点连接，第一极被配置为和所述第一输出端连接，第二极被配置为和第一电压端连接以接收第一电压。
  13. 一种栅极驱动电路，包括多个级联的如权利要求1-3任一所述的移位寄存器单元，其中，
    除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第一输出端连接；
    除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的第一输出端连接。
  14. 一种栅极驱动电路，包括多个级联的如权利要求4-6任一所述的移位寄存器单元，其中，
    除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第二输出端连接；
    除最后一级移位寄存器单元外，其余各级移位寄存器单元的复位端和下一级移位寄存器单元的第二输出端连接。
  15. 一种显示装置，包括如权利要求13或14所述的栅极驱动电路。
  16. 一种权利要求1-3任一所述的移位寄存器单元的驱动方法，包括：
    第一阶段，所述输入电路响应于所述输入信号对所述上拉节点进行充电，所述输出电路输出所述第一时钟信号的低电平至所述第一输出端；
    第二阶段，所述上拉节点的电位被所述第一时钟信号和所述第二时钟信号的高电平耦合升高，所述输出电路输出所述第一时钟信号的高电平至所述第一输出端；
    第三阶段，所述上拉节点的电位被所述第一时钟信号的低电平耦合降低，所述第一输出端通过所述输出电路放电；
    第四阶段，所述上拉节点的电位被所述第二时钟信号的低电平进一步耦合拉低；
    第五阶段，所述上拉节点复位电路在所述复位信号的控制下对所述上拉节点进行复位；
    其中，在所述第三阶段和所述第四阶段中，所述第一时钟信号的下降沿时刻早于所述第二时钟信号的下降沿时刻。
  17. 根据权利要求16所述的驱动方法，其中，
    在所述第二阶段中，所述第一时钟信号的上升沿时刻与所述第二时钟信号的上升沿时刻保持一致。
  18. 一种权利要求4-6任一所述的移位寄存器单元的驱动方法，包括：
    第一阶段，所述输入电路响应于所述输入信号对所述上拉节点进行充电，所述输出电路输出所述第一时钟信号的低电平至所述第一输出端，所述耦合电路输出所述第二时钟信号的低电平至所述第二输出端；
    第二阶段，所述上拉节点的电位被所述第一时钟信号和所述第二时钟信号的高电平耦合拉高，所述输出电路输出所述第一时钟信号的高电平至所述第一输出端，所述耦合电路输出所述第二时钟信号的高电平至所述第二输出端；
    第三阶段，所述上拉节点的电位被所述第一时钟信号的低电平耦合拉低，所述第一输出端通过所述输出电路放电至低电平，所述耦合电路输出所述第二时钟信号的高电平至所述第二输出端；
    第四阶段，所述上拉节点的电位被所述第二时钟信号的低电平进一步耦合拉低，所述第二输出端通过所述耦合电路放电至低电平；
    第五阶段，所述上拉节点复位电路在所述复位信号的控制下对所述上拉节点进行复位；
    其中，在所述第三阶段和所述第四阶段中，所述第一时钟信号的下降沿时刻早于所述第二时钟信号的下降沿时刻。
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