WO2016070543A1 - 移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2016070543A1
WO2016070543A1 PCT/CN2015/074562 CN2015074562W WO2016070543A1 WO 2016070543 A1 WO2016070543 A1 WO 2016070543A1 CN 2015074562 W CN2015074562 W CN 2015074562W WO 2016070543 A1 WO2016070543 A1 WO 2016070543A1
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Prior art keywords
pull
pole
transistor
module
signal
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PCT/CN2015/074562
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English (en)
French (fr)
Inventor
张元波
韩承佑
林允植
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京东方科技集团股份有限公司
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Priority to EP15762458.6A priority Critical patent/EP3217387A4/en
Priority to US14/777,587 priority patent/US9685134B2/en
Publication of WO2016070543A1 publication Critical patent/WO2016070543A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the gate drive circuit sequentially selects a square wave of a certain width from each pixel in order from the top to the bottom. Then, the signals required for the pixels of the row are sequentially output through the source driving circuit.
  • the gate driving circuit and the source driving circuit are usually connected by a COF (Chip On Film) or a COG (Chip On Glass) process.
  • COF Chip On Film
  • COG Chip On Glass
  • the existing display device can employ a GOA (Gate Drive On Array) circuit.
  • GOA Gate Drive On Array
  • the GOA circuit not only saves cost, but also can realize the symmetrical aesthetic design on both sides of the panel, and can also save the Bonding area of the gate drive circuit and the peripheral wiring space, thereby realizing the display.
  • the design of the narrow bezel of the device improves the productivity and yield of the display device.
  • existing GOA circuits also have certain problems. As shown in FIG. 1, the number of thin film transistors (TFTs) in the conventional GOA circuit is large, so that the occupied space is large.
  • the size of the transistor M is large and takes up a large space.
  • the gate voltage of the transistor M is the output of a shift register unit below the shift register unit, so the gate voltage of the transistor M is the high level of the output voltage, but since the high level is not high enough, The size of the transistor M needs to be relatively large to ensure The output delay is within the normal operating range, which also results in a large footprint of the GOA circuit.
  • the technical problem to be solved by the present invention includes providing a shift register unit, a gate driving circuit and a display device which are simple in structure with respect to the above problems existing in the conventional shift register unit.
  • the technical solution adopted to solve the technical problem of the present invention is a shift register unit, comprising: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module, and a discharge module, wherein
  • the input module is connected to the signal input end and the pull-up control node, and is configured to control a potential of the pull-up control node according to a signal input by the signal input end, where the pull-up control node is a connection between the input module and the pull-up module point;
  • the pull-up module is connected to the pull-up control node, the first clock signal port, and the signal output end, and is configured to control a signal according to a potential of the pull-up control node and a clock signal input by the first clock signal port.
  • the signal output from the output is pulled up to a high level;
  • the pull-down control module is connected to the pull-down control node and the second clock signal port, and is configured to control a level of the pull-down control node according to a level of the second clock signal port, where the pull-down control node is the pull-down control module The connection point with the pull-down module;
  • the pull-down module is connected to the pull-down control node, the pull-up control node, the second clock signal port, and a low-level signal for passing the low-level signal according to a level of the pull-up control node Pulling down the signal of the pull-down control node to a low level;
  • the discharge module includes a discharge capacitor, the first end of the discharge capacitor is connected to the pull-up module and the pull-up control node, and the second end is connected to the output signal reset input for inputting the signal input at the output signal of the reset signal Maintaining the potential of the pull-up control node under the control, and the signal output terminal is discharged through the pull-up module;
  • the reset module is connected to the reset signal input terminal, the pull-up control node, and the low A level signal for pulling down the level of the pull-up control node by a signal input through the reset signal input.
  • the discharge module of the register unit uses a discharge capacitor, the number of transistors is less than that in the prior art, so the structure is simple, the power consumption is small, and the delay problem is alleviated.
  • the input module comprises a first transistor, wherein
  • the first pole of the first transistor is connected to its control electrode and the signal input end, and the second pole is connected to the pull-up control node.
  • the pull-up module includes a second transistor and a storage capacitor
  • the first pole of the second transistor is connected to the first clock signal port, the second pole is connected to the second end of the storage capacitor and the signal output end, and the control pole is connected to the pull-up control node;
  • the first end of the storage capacitor is connected to the pull-up control node and the first end of the discharge capacitor.
  • the pull-down control module includes a third transistor and a fourth transistor, wherein
  • the first pole of the third transistor is connected to the control pole thereof and the second pole of the fourth transistor, the second pole is connected to the control pole and the pull-down module of the fourth transistor, and the control pole is connected to the second clock signal port;
  • the first pole of the fourth transistor is connected to the pull-down control node.
  • the pull-down module includes a fifth transistor and a sixth transistor, wherein
  • the first pole of the fifth transistor is connected to the second pole of the third transistor and the control pole of the fourth transistor, the second pole is connected to the low level signal, and the control pole is connected to the control pole of the sixth transistor;
  • the first pole of the sixth transistor is connected to the pull-down control node, the second pole is connected to the low level signal, and the control pole is connected to the pull-up control node.
  • the discharge module further includes a discharge device coupled to the signal output terminal, the low level signal, and the discharge capacitor for aligning the signal according to a potential of the discharge capacitor The output is discharged.
  • the discharge device may include a seventh transistor, wherein
  • the first pole of the seventh transistor is connected to the second pole of the second transistor, the second end of the storage capacitor and the signal output end, the second pole is connected to the low level signal, and the control pole is connected to the second end of the discharge capacitor.
  • the reset module includes an eighth transistor, wherein
  • the first pole of the eighth transistor is connected to the pull-up control node, the second pole is connected to the low-level signal, and the control pole is connected to the reset signal input end.
  • the register unit further includes a noise reduction module, and the noise reduction module is connected to the reset module, the low level signal, the pull-up control node, and the pull-down control node, and is configured to pass the low level signal according to the potential of the pull-down control node.
  • the potential of the pull-up control node is pulled low to remove the noise of the shift register unit.
  • the noise reduction module includes a ninth transistor and a tenth transistor, wherein
  • the first pole of the ninth transistor is connected to the pull-up control node, the second pole is connected to the low-level signal, and the control pole is connected to the pull-down control node;
  • the first pole of the tenth transistor is connected to the signal output end, the second pole is connected to the low level signal, and the control pole is connected to the pull-down control node.
  • the technical solution adopted to solve the technical problem of the present invention is a gate driving circuit including at least four cascaded shift register units of any of the above, wherein
  • each of the other shift register units is connected to the signal input end of the next two stages of the shift register unit except for the countdown first stage and the penultimate stage shift register unit;
  • each of the shift register units are connected to the output signal reset input terminals of the upper two stage shift register units;
  • the signal output of each of the other shift register units is coupled to the reset signal input of the upper three stage shift register unit;
  • the signal input terminals of the first and second stage shift register units are connected to the frame strobe signal.
  • a technical solution adopted to solve the technical problem of the present invention is a display device including the above-described gate driving circuit.
  • 1 is a schematic diagram of a conventional shift register unit
  • FIG. 2 is a schematic diagram of a shift register unit in accordance with an embodiment of the present invention.
  • FIG. 3 is another schematic diagram of a shift register unit in accordance with an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a shift register unit in accordance with an embodiment of the present invention.
  • FIG. 5 is a timing diagram of operation of a shift register unit in accordance with an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a gate drive circuit in accordance with an embodiment of the present invention.
  • the transistor used in the embodiment of the present invention may be a thin film transistor or a field effect transistor or the like. Since the source and the drain of the transistor used are symmetrical, the source and the drain are indistinguishable. In the embodiment of the present invention, in order to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a gate. Further, the transistor can be classified into an N-type transistor and a P-type transistor. In the embodiment of the present invention, an N-type transistor is taken as an example. When an N-type transistor is used, the source of the first N-type transistor and the drain of the second N-type transistor. It will be readily apparent to those skilled in the art that the invention can be implemented using P-type transistors without the inventive effort, which is also within the scope of the embodiments of the present invention.
  • the embodiment provides a shift register unit, which includes an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module, and a discharge module.
  • the input module is connected to the signal input terminal INPUT and the pull-up control section a point PU for controlling a potential of the pull-up control node PU according to a signal input by the signal input terminal INPUT, wherein the pull-up control node PU is a connection point of the input module and the pull-up module.
  • the pull-up module is connected to the pull-up control node PU, the first clock signal port CLK, and the signal output terminal OUTPUT for inputting a clock according to the potential of the pull-up control node PU and the first clock signal port CLK
  • the control of the signal pulls up the signal output from the signal output OUTPUT to a high level.
  • the pull-down control module is connected to the pull-down control node PD and the second clock signal port CLKR for controlling the level of the pull-down control node PD according to the level of the second clock signal port CLKR, and the pull-down control node PD is the pull-down control The connection point between the module and the drop-down module.
  • the pull-down module is connected to the pull-up control node PU, the pull-down control node PD, and the low-level signal VGL, for pulling down the pull-down control node PD to low power by the low-level signal when the pull-down module is turned on. level.
  • the discharge module includes at least a discharge capacitor, the first end of the discharge capacitor is connected to the pull-up module and the pull-up control node PU, and the second end is connected to the output signal reset input terminal RST_OUT, wherein the output signal reset input terminal RST_OUT input
  • the signal controls the discharge capacitor C2 to maintain the potential of the pull-up control node PU, and the signal output terminal OUTPUT is discharged through the pull-up module.
  • the reset module is connected to the reset signal input terminal RST_PU and the pull-up control node PU for pulling down the level of the pull-up control node PU through the signal input by the reset signal input terminal RST_PU.
  • the discharge capacitor C2 functions as a discharge module. Compared with the discharge module composed of transistors in the prior art, the discharge capacitor C2 occupies a small area, so that it can be well discharged while discharging the shift register unit. The footprint of the shift register unit.
  • the input module includes a first transistor M1, and the first electrode of the first transistor M1 is connected to its control electrode and the signal input terminal INPUT.
  • the second pole connects the pull-up control node PU and the reset module.
  • the pull-up control node PU is a node that controls the pull-up module to be turned on or off.
  • the input module is configured to determine a pull-up control node in the shift register unit according to whether the signal input by the signal input terminal INPUT is high level or low level The state of the PU.
  • the pull-up module includes a second transistor M2 and a storage capacitor C1.
  • the first pole of the second transistor M2 is connected to the first clock signal port CLK, the second pole is connected to the second end of the storage capacitor C1 and the signal output terminal OUTPUT, and the control pole is connected to the pull-up control node PU.
  • the first end of the storage capacitor C1 is connected to the first end of the pull-up control node PU and the discharge capacitor C2 in the discharge module.
  • the pull-down control module includes a third transistor M3 and a fourth transistor M4.
  • the first electrode of the third transistor M3 is connected to its control electrode and the second electrode of the fourth transistor M4, the second electrode is connected to the control electrode and the pull-down module of the fourth transistor M4, and the control electrode is connected to the second clock signal port CLKR.
  • the first pole of the fourth transistor M4 is connected to the pull-down control node PD.
  • the pull-down module includes a fifth transistor M5 and a sixth transistor M6.
  • the first pole of the fifth transistor M5 is connected to the second pole of the third transistor M3 and the gate of the fourth transistor M4, the second pole is connected to the low level signal, and the control pole is connected to the gate of the sixth transistor M6.
  • the first pole of the sixth transistor M6 is connected to the pull-down control node PD, the second pole is connected to the low level signal, and the control pole is connected to the pull-up control node PU.
  • the discharge module may further include a seventh transistor M7 (ie, a discharge device).
  • the first pole of the seventh transistor M7 is connected to the second pole of the second transistor M2, the second end of the storage capacitor C1, and the signal output terminal OUTPUT, the second pole is connected to the low level signal, and the control pole is connected to the discharge capacitor C2. Two ends.
  • the reset module comprises an eighth transistor M8.
  • the first pole of the eighth transistor M8 is connected to the pull-up control node PU, the second pole is connected to the low-level signal VGL, and the control pole is connected to the reset signal input terminal RST_PU.
  • the register unit may also include a noise reduction module, as shown in FIGS. 3 and 4.
  • the noise reduction module is connected to the low level signal VGL, the pull-up control node PU, and the pull-down control node PD for pulling down the potential of the pull-up control node PU through the low level signal VGL according to the potential of the pull-down control node PD.
  • the noise in the output signal of the shift register unit is removed.
  • the noise reduction module includes a ninth transistor M9 and a tenth transistor M10.
  • the first pole of the ninth transistor M9 is connected to the pull-up control node PU, the second pole is connected to the low-level signal VGL, and the control pole is connected to the pull-down control node. PD.
  • the first pole of the tenth transistor M10 is connected to the signal output terminal OUTPUT, the second pole is connected to the low level signal VGL, and the control pole is connected to the pull-down control node PD.
  • the discharge module includes a discharge capacitor C2. Due to the capacitive coupling of the discharge capacitor C2, the pull-up control node PU can maintain the potential unchanged, so the signal output terminal OUTPUT can be well discharged, thereby reducing the second
  • the size of the transistor M2 can also reduce the size of the seventh transistor M7, and even the seventh transistor M7 can be omitted, thereby saving space and reducing the power consumption of the shift register unit.
  • a gate driving circuit is also provided.
  • 6 is a schematic diagram of a gate drive circuit in accordance with an embodiment of the present invention.
  • the gate drive circuit includes at least four cascaded shift register units.
  • the signal output terminal OUTPUT of each of the other shift register units is connected to the signal input terminal INPUT of the next two stages of shift register units.
  • the signal output terminal OUTPUT of the first stage shift register unit is connected to the signal input terminal INPUT of the third stage shift register unit.
  • the signal output terminal OUTPUT of each of the other shift register units is connected to the output signal reset input terminal RST_OUT of the upper two stage shift register unit.
  • the signal output terminal OUTPUT of the third stage shift register unit is connected to the output signal reset input terminal RST_OUT of the first stage shift register unit.
  • the signal output terminal OUTPUT of each of the other shift register units is connected to the reset signal input terminal RST_PU of the upper three stage shift register unit.
  • the signal output terminal OUTPUT of the fourth stage shift register unit is connected to the reset signal input terminal RST_PU of the first stage shift register unit.
  • the signal input terminal INPUT of the first stage and second stage shift register unit is connected to the frame strobe signal STV.
  • the signal input from the signal input terminal INPUT (frame strobe signal STV) is a high level signal, at which time the first transistor M1 is turned on, and the pull-up control node PU is charged.
  • the first clock signal port CLK (connected to CLK1) inputs a high level signal, and since the pull-up control node PU is charged at S1, it is at a high level, and at this time, the second transistor M2 is turned on, and the signal is output.
  • the terminal OUTPUT outputs a high level signal.
  • the input of the first clock signal port CLK changes from a high level signal to a low level signal
  • the signal input by the output signal reset input terminal RST_OUT is the signal output end OUTPUT output of the next two stages of the shift register unit.
  • the signal because the signal input by the first clock signal port CLK of the next two stages of the shift register unit is a high level signal (CLK3), the signal outputted by the signal output terminal OUTPUT of the next two stages of the shift register unit It is high level, that is to say, the signal input by the output signal reset input terminal RST_OUT is high level. Due to the existence of the discharge capacitor C2, the pull-up control node PU is similar when the storage capacitor C1 and the discharge capacitor C2 are similar in size.
  • the signal output terminal OUTPUT can be well discharged through the second transistor M2.
  • the seventh transistor M7 is turned on, and since the second electrode of the seventh transistor M7 is connected to the low level signal VGL, the signal output terminal OUTPUT can also pass through the seventh transistor. M7 discharge.
  • the reset signal input terminal RST_PU since the reset signal input terminal RST_PU is connected to the signal output terminal OUTPUT of the shift register unit of the lower three stages, and at this time, the signal output terminal OUTPUT of the shift register unit of the lower three stages outputs a high level signal,
  • the signal input by the reset signal input terminal RST_PU is at a high level, and the eighth transistor M8 is turned on. Since the second electrode of the eighth transistor M8 is connected to the low level signal VGL, the pull-up control node PU potential is pulled low, thereby completing Charging of the gate line connected to the shift register unit and resetting of the pull-up control node PU.
  • the discharge module since the discharge module includes the discharge capacitor C2, the voltage of the PU point of the pull-up control node remains unchanged at the S3 stage, and the voltage value of the point is higher than the output voltage of the signal output terminal OUTPUT. It is about twice as high, so the gate of the second transistor M2 will maintain a very high potential, and the signal output terminal OUTPUT can be well discharged to a low potential through the second transistor M2 (because the first clock signal port CLK is The low potential), so that the size of the second transistor M2 can be made smaller, the seventh transistor M7 can also be greatly reduced, and even the seventh transistor M7 can be omitted, so that the power consumption and the occupied area of the shift register unit can be reduced.
  • a display device comprising the above-described gate drive circuit.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device can realize a narrow bezel design because it includes the gate driving circuit provided by the present invention.
  • the display device provided by the present invention may also include other conventional structures, such as a display driving unit, etc., and details are not described herein.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器单元、栅极驱动电路及显示装置，其中，移位寄存器单元包括：输入模块、上拉模块、下拉控制模块、下拉模块、复位模块以及放电模块；输入模块连接信号输入端（IN-PUT）以及上拉控制节点（PU）；上拉模块连接上拉控制节点（PU）、第一时钟信号端口（CLK）以及信号输出端（OUTPUT）；下拉控制模块连接下拉控制节点（PD）以及第二时钟信号端口（CLKR）；下拉模块连接下拉控制节点（PD）、上拉控制节点（PU）和低电平信号（VGL）；放电模块包括放电电容，放电电容的第一端连接上拉模块和上拉控制节点（PU），第二端连接输出信号复位输入端（RST_OUT）；复位模块连接复位信号输入端（RST_PU）、上拉控制节点（PU）和低电平信号（VGL）。

Description

移位寄存器单元、栅极驱动电路及显示装置 技术领域
本发明属于显示技术领域，具体涉及移位寄存器单元、栅极驱动电路及显示装置。
背景技术
TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示装置)实现一帧画面显示的基本原理是通过栅极驱动电路从上到下依次对每一行像素输入一定宽度的方波进行选通，再通过源极驱动电路依次输出该行像素所需的信号。目前，在这种结构的显示器件中，通常将栅极驱动电路和源极驱动电路通过COF(Chip On Film，覆晶薄膜)或COG(Chip On Glass，芯片直接固定在玻璃上)工艺连接在玻璃面板上，但是当分辨率较高时，栅极驱动电路和源极驱动电路的输出均较多，驱动电路的长度也将增大，这不利于模组驱动电路的压焊(Bonding)工艺。
为了克服以上问题，现有显示器件可采用GOA(Gate Drive On Array)电路。与现有的COF或COG工艺相比，GOA电路不仅节约了成本，而且可以做到面板两边对称的美观设计，同时也可省去栅极驱动电路的Bonding区域以及***布线空间，从而实现了显示装置窄边框的设计，提高了显示装置的产能和良率。但是现有GOA电路也存在着一定的问题。如图1所示，现有的GOA电路中的薄膜晶体管(TFT)的个数较多，故占用空间较大。另外，由于现有电路只能通过晶体管M对信号输出端OUTPUT进行放电，因此晶体管M的尺寸很大，占用空间较大。而且晶体管M的控制极电压为该移位寄存器单元下面某级移位寄存器单元的输出，因此晶体管M的控制极电压值为输出电压的高电平，但是由于该高电平并不够高，故晶体管M的尺寸需要比较大，才能保证 输出延迟在正常工作的范围内，从而也导致GOA电路的占用空间较大。
发明内容
本发明所要解决的技术问题包括，针对现有的移位寄存器单元存在的上述问题，提供一种结构简单的移位寄存器单元、栅极驱动电路及显示装置。
解决本发明技术问题所采用的技术方案是一种移位寄存器单元，其包括：输入模块、上拉模块、下拉控制模块、下拉模块、复位模块以及放电模块，其中
所述输入模块连接信号输入端以及上拉控制节点，用于根据信号输入端输入的信号控制上拉控制节点的电位，所述上拉控制节点为所述输入模块与所述上拉模块的连接点；
所述上拉模块连接所述上拉控制节点、第一时钟信号端口以及信号输出端，用于根据所述上拉控制节点的电位和所述第一时钟信号端口输入的时钟信号的控制将信号输出端输出的信号上拉为高电平；
所述下拉控制模块连接下拉控制节点以及第二时钟信号端口，用于根据所述第二时钟信号端口的电平控制所述下拉控制节点的电平，所述下拉控制节点为所述下拉控制模块与下拉模块的连接点；
所述下拉模块连接所述下拉控制节点、所述上拉控制节点、所述第二时钟信号端口和低电平信号，用于根据所述上拉控制节点的电平通过所述低电平信号将所述下拉控制节点的信号下拉为低电平；
所述放电模块包括放电电容，所述放电电容的第一端连接存上拉模块和上拉控制节点，第二端连接输出信号复位输入端，用于在所述输出信号复位输入端输入的信号的控制下维持上拉控制节点的电位，所述信号输出端通过上拉模块进行放电；
所述复位模块连接复位信号输入端、所述上拉控制节点和低 电平信号，用于通过复位信号输入端输入的信号将上拉控制节点的电平拉低。
本发明中，因为寄存器单元的放电模块采用放电电容，其晶体管的个数较现有技术中要少，故其结构简单，功耗较小，减缓延迟问题。
优选的是，所述输入模块包括第一晶体管，其中
所述第一晶体管的第一极连接其控制极和信号输入端，第二极连接上拉控制节点。
进一步优选的是，所述上拉模块包括第二晶体管和存储电容，
所述第二晶体管的第一极连接第一时钟信号端口，第二极连接存储电容的第二端和信号输出端，控制极连接上拉控制节点；
所述存储电容的第一端连接上拉控制节点和放电电容的第一端。
更进一步优选的是，所述下拉控制模块包括第三晶体管和第四晶体管，其中
所述第三晶体管的第一极连接其控制极和第四晶体管的第二极，第二极连接第四晶体管的控制极和下拉模块，控制极连接第二时钟信号端口；
所述第四晶体管的第一极连接下拉控制节点。
更进一步优选的是，所述下拉模块包括第五晶体管和第六晶体管，其中
所述第五晶体管的第一极连接第三晶体管的第二极和第四晶体管的控制极，第二极连接低电平信号，控制极连接第六晶体管的控制极；
所述第六晶体管的第一极连接下拉控制节点，第二极连接低电平信号，控制极连接上拉控制节点。
更进一步优选的是，所述放电模块还包括放电器件，所述放电器件与所述信号输出端、低电平信号和所述放电电容连接，用于根据所述放电电容的电位对所述信号输出端进行放电。
优选地，所述放电器件可以包括第七晶体管，其中，
所述第七晶体管的第一极连接第二晶体管的第二极、存储电容的第二端以及信号输出端，第二极连接低电平信号，控制极连接放电电容的第二端。
更进一步优选的是，所述复位模块包括第八晶体管，其中
所述第八晶体管的第一极连接上拉控制节点，第二极接低电平信号，控制极接复位信号输入端。
优选的是，所述寄存器单元还包括降噪模块，所述降噪模块连接复位模块、低电平信号、上拉控制节点以及下拉控制节点，用于根据下拉控制节点的电位通过低电平信号将上拉控制节点的电位拉低，以去除移位寄存器单元的噪声。
进一步优选的是，所述降噪模块包括第九晶体管和第十晶体管，其中
所述第九晶体管的第一极连接上拉控制节点，第二极连接低电平信号，控制极连接下拉控制节点；
所述第十晶体管的第一极连接信号输出端，第二极连接低电平信号，控制极连接下拉控制节点。
解决本发明技术问题所采用的技术方案是一种栅极驱动电路，其包括至少四个级联的上述的任意一种移位寄存器单元，其中
除倒数第一级和倒数第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其下两级移位寄存器单元的信号输入端连接；
除第一级和第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其上两级移位寄存器单元的输出信号复位输入端连接；
除第一级、第二级和第三级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其上三级移位寄存器单元的复位信号输入端连接；并且，
第一级和第二级移位寄存器单元的信号输入端接帧选通信号。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述栅极驱动电路。
附图说明
图1为现有的移位寄存器单元的示意图；
图2为根据本发明实施例的移位寄存器单元的一种示意图；
图3为根据本发明的实施例的移位寄存器单元的另一种示意图；
图4为根据本发明的实施例的一种移位寄存器单元的电路图；
图5为根据本发明的实施例的一种移位寄存器单元工作的时序图；以及
图6为根据本发明的实施例的栅极驱动电路的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
本发明实施例中所采用的晶体管可以为薄膜晶体管或场效应管或其他类似器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外，晶体管可以分为N型晶体管和P型晶体管。本发明实施例中以N型晶体管为例进行说明，当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极。对本领域技术人员而言，可以在没有付出创造性劳动的前提下容易想到采用P型晶体管来实现本发明，这也在本发明实施例的保护范围内。
如图2所示，本实施例提供一种移位寄存器单元，其包括：输入模块、上拉模块、下拉控制模块、下拉模块、复位模块以及放电模块。所述输入模块连接信号输入端INPUT以及上拉控制节 点PU，用于根据信号输入端INPUT输入的信号控制上拉控制节点PU的电位，所述上拉控制节点PU为所述输入模块与所述上拉模块的连接点。所述上拉模块连接所述上拉控制节点PU、第一时钟信号端口CLK以及信号输出端OUTPUT，用于根据所述上拉控制节点PU的电位和所述第一时钟信号端口CLK输入的时钟信号的控制将信号输出端OUTPUT输出的信号上拉为高电平。所述下拉控制模块连接下拉控制节点PD以及第二时钟信号端口CLKR，用于根据第二时钟信号端口CLKR的电平控制下拉控制节点PD的电平，所述下拉控制节点PD为所述下拉控制模块与下拉模块的连接点。所述下拉模块连接上拉控制节点PU、下拉控制节点PD和低电平信号VGL，用于在所述下拉模块开启时，通过所述低电平信号将所述下拉控制节点PD下拉为低电平。所述放电模块至少包括放电电容，所述放电电容的第一端连接上拉模块和上拉控制节点PU，第二端连接输出信号复位输入端RST_OUT，其中，所述输出信号复位输入端RST_OUT输入的信号控制放电电容C2以维持上拉控制节点PU的电位，所述信号输出端OUTPUT通过上拉模块进行放电。所述复位模块连接复位信号输入端RST_PU和上拉控制节点PU，用于通过复位信号输入端RST_PU输入的信号将上拉控制节点PU的电平拉低。
在本实施例中放电电容C2作为放电模块，与现有技术中由晶体管组成的放电模块相比，放电电容C2占用面积较小，从而能在很好地为移位寄存器单元放电的同时减小移位寄存器单元的占用空间。
如图4所示，优选地，在本实施例的移位寄存器单元中，所述输入模块包括第一晶体管M1，所述第一晶体管M1的第一极连接其控制极和信号输入端INPUT，第二极连接上拉控制节点PU和所述复位模块。
在本实施例中，上拉控制节点PU是控制上拉模块开启或者关断的节点。输入模块用于根据信号输入端INPUT输入的信号为高电平或者是低电平来确定移位寄存器单元中的上拉控制节点 PU的状态。
优选地，上拉模块包括第二晶体管M2和存储电容C1。所述第二晶体管M2的第一极连接第一时钟信号端口CLK，第二极连接存储电容C1的第二端和信号输出端OUTPUT，控制极连接上拉控制节点PU。所述存储电容C1的第一端连接上拉控制节点PU和放电模块中的放电电容C2的第一端。
优选地，所述下拉控制模块包括第三晶体管M3和第四晶体管M4。所述第三晶体管M3的第一极连接其控制极和第四晶体管M4的第二极，第二极连接第四晶体管M4的控制极和下拉模块，控制极连接第二时钟信号端口CLKR。所述第四晶体管M4的第一极连接下拉控制节点PD。
优选地，所述下拉模块包括第五晶体管M5和第六晶体管M6。所述第五晶体管M5的第一极连接第三晶体管M3的第二极和第四晶体管M4的控制极，第二极连接低电平信号，控制极连接第六晶体管M6的控制极。所述第六晶体管M6的第一极连接下拉控制节点PD，第二极连接低电平信号，控制极连接上拉控制节点PU。
除了放电电容C2，所述放电模块还可以包括第七晶体管M7(即放电器件)。所述第七晶体管M7的第一极连接第二晶体管M2的第二极、存储电容C1的第二端以及信号输出端OUTPUT，第二极连接低电平信号，控制极连接放电电容C2的第二端。
优选地，所述复位模块包括第八晶体管M8。所述第八晶体管M8的第一极连接上拉控制节点PU，第二极连接低电平信号VGL，控制极连接复位信号输入端RST_PU。
所述寄存器单元还可以包括降噪模块，如图3和图4所示。所述降噪模块连接低电平信号VGL、上拉控制节点PU以及下拉控制节点PD，用于根据下拉控制节点PD的电位通过低电平信号VGL将上拉控制节点PU的电位拉低，以去除移位寄存器单元输出信号中的噪声。优选地，所述降噪模块包括第九晶体管M9和第十晶体管M10。所述第九晶体管M9的第一极连接上拉控制节点PU，第二极连接低电平信号VGL，控制极连接下拉控制节点 PD。所述第十晶体管M10的第一极连接信号输出端OUTPUT，第二极连接低电平信号VGL，控制极连接下拉控制节点PD。
在本实施例中，放电模块包括放电电容C2，由于放电电容C2的电容耦合作用，上拉控制节点PU可以保持电位不变，因此信号输出端OUTPUT可很好地放电，从而可以减小第二晶体管M2的尺寸，也可以减小第七晶体管M7的尺寸，甚至可以省略第七晶体管M7，进而节省空间，并降低移位寄存器单元的功耗。
根据本发明的另一方面，还提供了一种栅极驱动电路。图6所示为根据本发明的实施例的栅极驱动电路的示意图，如图6所示，该栅极驱动电路包括至少四个级联的上述移位寄存器单元。除倒数第一级和倒数第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端OUTPUT与其下两级移位寄存器单元的信号输入端INPUT连接。例如，第一级移位寄存器单元的信号输出端OUTPUT与第三级移位寄存器单元的信号输入端INPUT连接。除第一级和第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端OUTPUT与其上两级移位寄存器单元的输出信号复位输入端RST_OUT连接。例如，第三级移位寄存器单元的信号输出端OUTPUT与第一级移位寄存器单元的输出信号复位输入端RST_OUT连接。除第一级、第二级和第三级移位寄存器单元外，其他每个移位寄存器单元的信号输出端OUTPUT与其上三级移位寄存器单元的复位信号输入端RST_PU连接。例如，第四级移位寄存器单元的信号输出端OUTPUT与第一级移位寄存器单元的复位信号输入端RST_PU连接。第一级和第二级移位寄存器单元的信号输入端INPUT接帧选通信号STV。
为简明起见，图6中仅示出了四个级联的移位寄存器单元，但本领域技术人员应理解，移位寄存器单元的数量尽量可以根据实际需要而进行任意选择，具体的连接方式可参见上述说明，在此不予赘述。
为了更清楚了解本实施例的栅极驱动电路，以下结合图4和图5所示对该栅极驱动电路的驱动方法进行说明。
在S1阶段，信号输入端INPUT输入的信号(帧选通信号STV)为高电平信号，此时第一晶体管M1被导通，上拉控制节点PU被充电。
在S2阶段，第一时钟信号端口CLK(连接CLK1)输入高电平信号，由于上拉控制节点PU在S1时被充电，故处于高电平，此时第二晶体管M2被导通，信号输出端OUTPUT输出高电平信号。
在S3阶段、第一时钟信号端口CLK的输入由高电平信号变为低电平信号，同时输出信号复位输入端RST_OUT所输入的信号是其下两级移位寄存器单元的信号输出端OUTPUT输出的信号，由于此时其下两级移位寄存器单元的第一时钟信号端口CLK输入的信号为高电平信号(CLK3)，故其下两级移位寄存器单元的信号输出端OUTPUT输出的信号为高电平，也就说输出信号复位输入端RST_OUT所输入的信号为高电平，由于放电电容C2的存在，在存储电容C1和放电电容C2的大小相近的情况下，上拉控制节点PU的电位基本不变，因此信号输出端OUTPUT可以通过第二晶体管M2很好地放电。此外，当RST_OUT所输入的信号为高电平时，第七晶体管M7被导通，由于第七晶体管M7的第二极连接低电平信号VGL，因此此时信号输出端OUTPUT还可以通过第七晶体管M7放电。
在S4阶段，由于复位信号输入端RST_PU与其下三级的移位寄存器单元的信号输出端OUTPUT连接，且此时其下三级的移位寄存器单元的信号输出端OUTPUT输出高电平信号，故复位信号输入端RST_PU输入的信号为高电平，第八晶体管M8被导通，由于第八晶体管M8的第二极连接低电平信号VGL，因此上拉控制节点PU电位被拉低，从而完成与该移位寄存器单元连接的栅线的充电以及上拉控制节点PU的复位。
在其余的工作过程中，为了进一步避免信号输出端OUTPUT 所输出的信号中存在噪声，当下拉控制节点PD周期性地被第二时钟信号端口CLKR(连接CLK4)的信号上拉为高电平时，第九晶体管M9和第十晶体管M10被导通，故上拉控制节点PU与信号输出端OUTPUT的电位被拉低，从而去除了噪声，防止误输出。
由前所述，在本实施例中，由于放电模块包括放电电容C2，因此在S3阶段上拉控制节点PU点电压保持不变，该点电压值会比信号输出端OUTPUT输出电压的高电平高出一倍左右，因此第二晶体管M2的控制极会保持一个非常高的电位，信号输出端OUTPUT可以通过第二晶体管M2很好被放电到低电位(因为此时第一时钟信号端口CLK为低电位)，所以第二晶体管M2的尺寸可以变小，第七晶体管M7也可以大幅变小，甚至可以省略第七晶体管M7，以使得移位寄存器单元的功耗和占用面积都可以减小。
根据本发明的又一方面，还提供了一种显示装置，该显示装置包括上述的栅极驱动电路。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于包括本发明提供的栅极驱动电路，因此该显示装置可以实现窄边框设计。
当然，本发明提供的显示装置还可以包括其他常规的结构，如显示驱动单元等，在此不予赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种移位寄存器单元，其特征在于，包括：输入模块、上拉模块、下拉控制模块、下拉模块、复位模块以及放电模块；
    所述输入模块连接信号输入端以及上拉控制节点，用于根据所述信号输入端输入的信号控制所述上拉控制节点的电位，所述上拉控制节点为所述输入模块与所述上拉模块的连接点；
    所述上拉模块连接所述上拉控制节点、第一时钟信号端口以及信号输出端，用于根据所述上拉控制节点的电位和所述第一时钟信号端口输入的时钟信号的控制将所述信号输出端输出的信号上拉为高电平；
    所述下拉控制模块连接下拉控制节点以及第二时钟信号端口，用于根据所述第二时钟信号端口的电平控制所述下拉控制节点的电平，所述下拉控制节点为所述下拉控制模块与下拉模块的连接点；
    所述下拉模块连接所述下拉控制节点、所述上拉控制节点、所述第二时钟信号端口和低电平信号，用于根据所述上拉控制节点的电位通过所述低电平信号将所述下拉控制节点下拉为低电平；
    所述放电模块包括放电电容，所述放电电容的第一端连接所述上拉模块和所述上拉控制节点，第二端连接输出信号复位输入端，用于在所述输出信号复位输入端输入的信号的控制下维持所述上拉控制节点的电位，所述信号输出端通过所述上拉模块进行放电；
    所述复位模块连接复位信号输入端、所述上拉控制节点和低电平信号，用于通过所述复位信号输入端输入的信号将所述上拉控制节点的电平拉低。
  2. 根据权利要求1所述的移位寄存器单元，其特征在于，所述输入模块包括第一晶体管，其中
    所述第一晶体管的第一极连接其控制极和所述信号输入端，第二极连接所述上拉控制节点。
  3. 根据权利要求2所述的移位寄存器单元，其特征在于，上拉模块包括第二晶体管和存储电容，其中
    所述第二晶体管的第一极连接所述第一时钟信号端口，第二极连接所述存储电容的第二端和所述信号输出端，控制极连接所述上拉控制节点；
    所述存储电容的第一端连接所述上拉控制节点和所述放电电容的第一端。
  4. 根据权利要求3所述的移位寄存器单元，其特征在于，所述下拉控制模块包括第三晶体管和第四晶体管，其中
    所述第三晶体管的第一极连接其控制极和所述第四晶体管的第二极，第二极连接所述第四晶体管的控制极和所述下拉模块，控制极连接所述第二时钟信号端口；
    所述第四晶体管的第一极连接所述下拉控制节点。
  5. 根据权利要求4所述的移位寄存器单元，其特征在于，所述下拉模块包括第五晶体管和第六晶体管，其中
    所述第五晶体管的第一极连接所述第三晶体管的第二极和所述第四晶体管的控制极，第二极连接低电平信号，控制极连接所述第六晶体管的控制极；
    所述第六晶体管的第一极连接所述下拉控制节点，第二极连接低电平信号，控制极连接所述上拉控制节点。
  6. 根据权利要求1所述的移位寄存器单元，其特征在于，所述放电模块还包括放电器件，所述放电器件与所述信号输出端、低电平信号和所述放电电容连接，用于根据所述放电电容的电位对所述信号输出端进行放电。
  7. 根据权利要求6所述的移位寄存器单元，其特征在于，所述放电器件包括第七晶体管，其中
    所述第七晶体管的第一极连接所述第二晶体管的第二极、所述存储电容的第二端以及所述信号输出端，第二极连接低电平信号，控制极连接所述放电电容的第二端。
  8. 根据权利要求1所述的移位寄存器单元，其特征在于，所述复位模块包括第八晶体管，其中
    所述第八晶体管的第一极连接所述上拉控制节点，第二极连接低电平信号，控制极连接复位信号输入端。
  9. 根据权利要求1至8中任意一项所述的移位寄存器单元，其特征在于，所述寄存器单元还包括降噪模块，所述降噪模块连接所述低电平信号、所述上拉控制节点以及所述下拉控制节点，用于根据所述下拉控制节点的电位通过低电平信号将所述上拉控制节点的电位拉低，以去除所述移位寄存器单元的噪声。
  10. 根据权利要求9所述的移位寄存器单元，其特征在于，所述降噪模块包括第九晶体管和第十晶体管，其中
    所述第九晶体管的第一极连接所述上拉控制节点，第二极连接低电平信号，控制极连接所述下拉控制节点；
    所述第十晶体管的第一极连接所述信号输出端，第二极连接低电平信号，控制极连接所述下拉控制节点。
  11. 一种栅极驱动电路，包括至少四个级联的根据权利要求1至9中任意一项所述的移位寄存器单元，其中，
    除倒数第一级和倒数第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其下两级移位寄存器单元的信号输入端连接；
    除第一级和第二级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其上两级移位寄存器单元的输出信号复位输入端连接；
    除第一级、第二级和第三级移位寄存器单元外，其他每个移位寄存器单元的信号输出端与其上三级移位寄存器单元的复位信号输入端连接；并且，
    第一级和第二级移位寄存器单元的信号输入端接帧选通信号。
  12. 一种显示装置，包括根据权利要求11所述的栅极驱动电路。
PCT/CN2015/074562 2014-11-07 2015-03-19 移位寄存器单元、栅极驱动电路及显示装置 WO2016070543A1 (zh)

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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104217763B (zh) * 2014-08-28 2018-01-02 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN104299594B (zh) * 2014-11-07 2017-02-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104464600B (zh) * 2014-12-26 2017-02-01 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN105895011B (zh) * 2015-01-26 2019-02-15 上海和辉光电有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN104575429A (zh) * 2015-01-30 2015-04-29 合肥京东方光电科技有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN104637461B (zh) * 2015-02-12 2017-03-15 昆山龙腾光电有限公司 一种栅极驱动电路及显示装置
CN104700805B (zh) * 2015-03-26 2016-09-07 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104700803B (zh) * 2015-03-26 2017-02-22 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104732939A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
CN104700812A (zh) * 2015-03-31 2015-06-10 京东方科技集团股份有限公司 一种移位寄存器及阵列基板栅极驱动装置
CN104700766B (zh) * 2015-03-31 2017-12-15 京东方科技集团股份有限公司 控制子单元、移位寄存单元、移位寄存器和显示装置
CN104700814B (zh) * 2015-04-09 2017-03-22 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置以及显示装置
CN104810058B (zh) * 2015-05-13 2018-04-06 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN104810003A (zh) * 2015-05-21 2015-07-29 合肥京东方光电科技有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN104809978B (zh) 2015-05-21 2017-05-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US10037738B2 (en) * 2015-07-02 2018-07-31 Apple Inc. Display gate driver circuits with dual pulldown transistors
KR102426106B1 (ko) * 2015-07-28 2022-07-29 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
CN105096902B (zh) * 2015-09-28 2018-09-11 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105244000B (zh) * 2015-11-06 2018-01-09 京东方科技集团股份有限公司 一种goa单元、goa电路及显示装置
CN105427799B (zh) * 2016-01-05 2018-03-06 京东方科技集团股份有限公司 移位寄存单元、移位寄存器、栅极驱动电路及显示装置
CN105679238B (zh) * 2016-01-05 2018-06-29 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、阵列基板、显示装置
CN105427826B (zh) * 2016-01-07 2018-06-05 京东方科技集团股份有限公司 一种goa驱动电路及其驱动方法、显示装置
CN105632392B (zh) * 2016-01-11 2019-09-06 京东方科技集团股份有限公司 一种goa单元及其驱动方法、goa电路、显示装置
CN105609041B (zh) * 2016-03-23 2018-08-07 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105654905B (zh) * 2016-03-30 2018-01-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、驱动电路和显示装置
CN105761660B (zh) * 2016-05-16 2018-01-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105869563B (zh) * 2016-05-30 2019-01-18 京东方科技集团股份有限公司 Goa单元电路及其驱动方法、goa电路
CN105895047B (zh) * 2016-06-24 2018-10-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置、显示装置、控制方法
CN105913826B (zh) * 2016-06-30 2018-05-08 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、移位寄存器电路及显示装置
CN107993603B (zh) * 2016-10-27 2023-08-18 合肥鑫晟光电科技有限公司 移位寄存单元、移位寄存器、栅极驱动电路、显示装置
CN106448596B (zh) * 2016-10-31 2019-03-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN108022560B (zh) * 2016-11-01 2023-10-10 合肥鑫晟光电科技有限公司 栅极驱动电路及其驱动方法、显示基板和显示装置
CN106504719A (zh) * 2017-01-03 2017-03-15 合肥京东方光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN107622746B (zh) * 2017-09-28 2020-01-03 上海天马有机发光显示技术有限公司 移位寄存单元、其驱动方法、显示面板及显示装置
CN116312411A (zh) * 2017-10-20 2023-06-23 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法和显示装置
CN107945765B (zh) * 2018-01-10 2021-03-26 京东方科技集团股份有限公司 移位寄存器电路及其控制方法、栅极驱动电路、显示装置
CN108257568B (zh) * 2018-02-01 2020-06-12 京东方科技集团股份有限公司 移位寄存器、栅极集成驱动电路、显示面板及显示装置
CN108735176B (zh) * 2018-06-06 2020-01-03 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示装置
CN108806611B (zh) * 2018-06-28 2021-03-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN109213380A (zh) * 2018-11-12 2019-01-15 京东方科技集团股份有限公司 输入控制电路及方法、输入控制装置、显示面板
CN110599959B (zh) * 2019-08-08 2020-11-06 南京中电熊猫液晶显示科技有限公司 触发驱动电路及显示装置
KR20210045171A (ko) * 2019-10-16 2021-04-26 엘지디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시장치
CN113299217B (zh) * 2021-05-31 2022-08-02 武汉天马微电子有限公司 显示面板和显示装置
CN114495801B (zh) * 2022-03-10 2023-11-28 北京京东方显示技术有限公司 显示装置、栅极驱动电路、移位寄存单元及其驱动方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110142191A1 (en) * 2009-12-11 2011-06-16 Mitsubishi Electric Corporation Shift register circuit
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103093825A (zh) * 2013-01-14 2013-05-08 北京京东方光电科技有限公司 一种移位寄存器及阵列基板栅极驱动装置
CN103680452A (zh) * 2013-12-18 2014-03-26 合肥京东方光电科技有限公司 一种移位寄存器、栅极驱动电路、阵列基板和显示装置
CN103700356A (zh) * 2013-12-27 2014-04-02 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器、显示装置
CN204102544U (zh) * 2014-11-07 2015-01-14 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104299594A (zh) * 2014-11-07 2015-01-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101536218B1 (ko) * 2008-12-26 2015-07-13 삼성디스플레이 주식회사 게이트 구동회로, 이를 갖는 표시 장치 및 이 게이트 구동회로의 제조 방법
CN102012591B (zh) * 2009-09-04 2012-05-30 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
RU2514903C2 (ru) * 2009-12-15 2014-05-10 Шарп Кабусики Кайся Схема возбуждения линий сигнала сканирования и устройство отображения, включающее в себя данную схему
WO2011148655A1 (ja) * 2010-05-24 2011-12-01 シャープ株式会社 シフトレジスタ
CN202487125U (zh) * 2012-01-06 2012-10-10 京东方科技集团股份有限公司 移位寄存器和阵列基板栅极驱动电路
CN202502720U (zh) * 2012-03-16 2012-10-24 合肥京东方光电科技有限公司 一种移位寄存器、阵列基板栅极驱动装置和显示装置
CN102855938B (zh) * 2012-08-31 2015-06-03 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN102831860B (zh) * 2012-09-05 2014-10-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN103050106B (zh) * 2012-12-26 2015-02-11 京东方科技集团股份有限公司 栅极驱动电路、显示模组和显示器
CN103280201B (zh) * 2013-04-27 2015-09-23 京东方科技集团股份有限公司 栅极驱动装置和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110142191A1 (en) * 2009-12-11 2011-06-16 Mitsubishi Electric Corporation Shift register circuit
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103093825A (zh) * 2013-01-14 2013-05-08 北京京东方光电科技有限公司 一种移位寄存器及阵列基板栅极驱动装置
CN103680452A (zh) * 2013-12-18 2014-03-26 合肥京东方光电科技有限公司 一种移位寄存器、栅极驱动电路、阵列基板和显示装置
CN103700356A (zh) * 2013-12-27 2014-04-02 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器、显示装置
CN204102544U (zh) * 2014-11-07 2015-01-14 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104299594A (zh) * 2014-11-07 2015-01-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置

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