WO2011047544A1 - 柔性多层基板的金属层结构及其制造方法 - Google Patents

柔性多层基板的金属层结构及其制造方法 Download PDF

Info

Publication number
WO2011047544A1
WO2011047544A1 PCT/CN2010/070351 CN2010070351W WO2011047544A1 WO 2011047544 A1 WO2011047544 A1 WO 2011047544A1 CN 2010070351 W CN2010070351 W CN 2010070351W WO 2011047544 A1 WO2011047544 A1 WO 2011047544A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
multilayer substrate
flexible multilayer
layer structure
substrate according
Prior art date
Application number
PCT/CN2010/070351
Other languages
English (en)
French (fr)
Inventor
杨之光
Original Assignee
巨擘科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 巨擘科技股份有限公司 filed Critical 巨擘科技股份有限公司
Priority to EP20100824385 priority Critical patent/EP2493274A4/en
Priority to KR1020127011539A priority patent/KR101395336B1/ko
Priority to JP2012533460A priority patent/JP5507697B2/ja
Publication of WO2011047544A1 publication Critical patent/WO2011047544A1/zh

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/118Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845Stepped hole, via, edge, bump or conductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0588Second resist used as pattern over first resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0594Insulating resist or coating with special shaped edges
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern

Definitions

  • the present invention relates to a metal layer structure of a multilayer substrate and a method of fabricating the same, and more particularly to a metal layer structure of a flexible multilayer package substrate and a method of fabricating the same.
  • Multi-layer substrates are used in the fields of packaging substrates, printed circuit boards, flexible package substrates, and flexible circuit boards.
  • the integration of high-density systems is an inevitable trend in the miniaturization of today's electronic products, especially when flexible flexible substrates are used to make flexible package structures. It can be effectively applied to various products and meets the needs of miniaturization.
  • the thickness of the flexible multilayer substrate is thinner, and the higher the routing density of the multilayer substrate, the finer the dimensional requirements of the metal layer structure of the flexible multilayer substrate.
  • the flexible multilayer substrate of the prior art is usually only two to three layers, each layer having a thickness of about 50 to 60 ⁇ m, and a metal layer having a thickness of about 30 ⁇ m.
  • FIG. 1 is a schematic view showing a state in which bubbles are generated on the side of the metal layer structure of the flexible multilayer substrate in the prior art.
  • the existing flexible multilayer substrate has a metal layer 100 and a dielectric layer 102 overlying it.
  • the metal layer 100 of the conventional flexible multilayer substrate is formed by a etching method or a lamination method. If the metal layer 100 is used as a metal wiring or a pad, the cross-sectional shape is rectangular or rectangular as shown.
  • a common problem when making metal layers is that bubbles are generated at the edges of the metal layer, and as shown, the adhesion or peeling phenomenon is caused. Further, it may result in a decrease in the manufacturing yield of the flexible multilayer substrate. In particular, when the thickness of the above-mentioned flexible multilayer substrate is further thinned and the thickness of the metal layer is also thinner, the influence of the above-mentioned adhesion failure or peeling phenomenon becomes more and more conspicuous.
  • FIG. 2 is a schematic view showing that the metal layer structure of the flexible multilayer substrate of the prior art may be peeled off from the multilayer substrate together with the packaged solder balls due to external force.
  • the metal layer 100 is used as a metal line or a pad, the cross-sectional shape is rectangular or rectangular as shown. And if the metal layer 100 is used as a metal layer for encapsulating and bonding the IC, the dielectric layer 102 coated on the metal layer 100 in the flexible multilayer substrate is opened, and the metal material 106 is filled and packaged. The solder balls 108 are joined.
  • the flexible multilayer substrate When the flexible multilayer substrate is used as a flexible package substrate and a flexible circuit board as described above, it is applied to a multi-flex product, in other words, when the flexible substrate is bent, the metal layer 100 and the package may occur.
  • the bonding force between the solder balls 108 is strong, and the metal layer 100 and the package solder ball 108 are peeled off from the multilayer substrate together due to the bending external force.
  • Question. The above situation is shown in Figure 2.
  • the thickness of the above-mentioned flexible multilayer substrate is further thinner and the thickness of the metal layer is also thinner, the influence of the aforementioned peeling phenomenon becomes more apparent.
  • the technical problem to be solved by the present invention is to study the metal layer structure of a flexible multilayer substrate and a manufacturing method thereof, which can still be effective when the thickness of the flexible multilayer substrate is further reduced and the thickness of the metal layer is also thinner.
  • the metal layer structure is not easily delaminated or separated from the dielectric layer to be contacted, and has higher reliability.
  • the present invention provides a metal layer structure of a flexible multilayer substrate comprising a first metal layer and a dielectric layer.
  • the first metal layer has a body and an embedded base, and the body is located above the embedded base, and the bottom area of the embedded base is larger than the bottom area of the body.
  • the dielectric layer is disposed on the body and the embedded layer of the first metal layer, and a via hole is formed at the position of the first metal layer for the second metal layer on the body of the first metal layer and the dielectric layer Engage.
  • the body and the insert base may be integrally formed and formed at the same time. Alternatively, the same or different metal materials may be used, and after the embedded substrate is formed by different processes, the body is formed on the embedded substrate.
  • the present invention also provides a method for fabricating a metal layer structure of a flexible multilayer substrate, comprising the steps of: coating at least one photoresist layer on the first dielectric layer; and performing photolithography on a predetermined position of the first metal layer Developing a glue layer; removing a photoresist layer at a predetermined position; and forming a first metal layer at a predetermined position, wherein a bottom edge area of the first metal layer is larger than a top area, or may be resisted to the photoresist layer to form A metal layer structure having a body and an embedded base.
  • the present invention further provides a method for fabricating a metal layer structure of another flexible multilayer substrate, comprising the steps of: coating a first photoresist layer on the first dielectric layer; at a predetermined position of the first metal layer, a photoresist layer is developed; removing a first photoresist layer at a predetermined position; forming an embedded layer of the first metal layer at a predetermined position; and removing the first photoresist layer, coating the second photoresist Developing a second photoresist layer at a predetermined position of the first metal layer; removing the second photoresist layer at the predetermined position, so that the opening of the second photoresist layer is smaller than the first photoresist layer And a body forming a first metal layer at a predetermined position, forming a metal layer structure in which the embedded base is located below the body, and the bottom area of the embedded base is larger than the bottom area of the body.
  • An advantage of the present invention is that the metal layer structure of the flexible multilayer substrate can be used not only for a package substrate but also for the technical field of manufacturing a flexible printed circuit board or a flexible package substrate.
  • the invention The spirit of the method for fabricating a layer structure is to fabricate a metal layer structure having a body and an embedded layer.
  • the metal layer structure of the thin flexible multilayer substrate is not easily contacted with the adjacent layer.
  • the delamination or separation phenomenon of the dielectric layer can be used as a hole pad or a metal line of a flexible multilayer substrate, and can have higher reliability.
  • FIG. 1 is a schematic view showing a state in which a bubble is generated on a side of a metal layer structure of a prior art flexible multilayer substrate
  • FIG. 2 is a metal layer structure of a prior art flexible multilayer substrate which may be self-layered with a packaged solder ball due to an external force. a schematic view of the substrate being peeled off;
  • Figure 3 is a cross-sectional view showing a first embodiment of a metal layer structure of a flexible multilayer substrate of the present invention
  • Figure 4 is a cross-sectional view showing a second embodiment of a metal layer structure of a flexible multilayer substrate of the present invention.
  • Figure 5 is a view showing a manufacturing method of a first embodiment of a metal layer structure of a flexible multilayer substrate of the present invention
  • Figure 6 is a view showing a second embodiment of a metal layer structure of a flexible multilayer substrate of the present invention.
  • FIG. 3 there is shown a cross-sectional view of a first embodiment of a metal layer structure of a flexible multilayer substrate of the present invention.
  • the metal layer structure of the flexible multilayer substrate is used as a hole pad, and the flexible multilayer substrate is used for package connection of a not shown:).
  • the metal layer structure of the flexible multilayer substrate includes a first metal layer 300 having a body 302 and an embedded substrate 304 and a second dielectric layer 308.
  • the flexible multilayer substrate also has a first dielectric layer 200 beneath it.
  • the body 302 is positioned over the embedded substrate 304, and the bottom area of the embedded base 304 is greater than the bottom area of the body 302.
  • the second dielectric layer 308 is overlying the body 302 and the embedded substrate 304 of the first metal layer 300. After the second dielectric layer 308 is applied, the embedded substrate 304 is sandwiched by the first dielectric layer 200 and the second dielectric layer 308 as shown.
  • a via hole is disposed on the second dielectric layer 308 above the body 302 to bond the body 302 to the package solder ball 310, and the package is not shown to the IC:). If bubbles are generated on the side of the first metal layer 300, the embedded The base 304 can reduce the effects of peeling and delamination due to bubbles. Moreover, although the bonding between the first metal layer 300 and the first dielectric layer 200 has a certain strength, the present embodiment is sandwiched by the first dielectric layer 200 and the second dielectric layer 308 by using the embedded substrate 304. The force can effectively prevent the problem that the first metal layer 300 and the package solder ball 310 are peeled off from the multilayer substrate when the flexible multilayer substrate is bent.
  • the thickness of the first metal layer 300 is only about 5 ⁇ m.
  • the metal layer structure of the flexible multilayer substrate is used as an aperture pad.
  • the metal layer structure of the flexible multilayer substrate is used as a metal line, the upper layer is bonded to the other layer. Metal lines.
  • the metal layer structure of the multi-layer substrate of the specific embodiment can solve the disadvantages faced by the prior art, and more effectively improve the reliability of the flexible multi-layer substrate.
  • the metal layer structure of the flexible multilayer substrate includes a first metal layer 400 having a body 402 and an embedded base 404 and a second dielectric layer 308.
  • the flexible multilayer substrate further has a first dielectric layer 200 beneath it. As shown, the body 402 is positioned over the embedded base 404, and the bottom surface of the embedded base 404 is larger than the bottom area of the body 402.
  • the second dielectric layer 308 is coated on the body 302 and the embedded substrate 304 of the first metal layer 300. After the second dielectric layer 308 is applied, the embedded substrate 404 is sandwiched by the first dielectric layer 200 and the second dielectric layer 308 as shown. A via hole is disposed on the second dielectric layer 308 above the body 402, and the body 402 is bonded to the package solder ball 310 to encapsulate the IC (not shown).
  • the body 402 and the insert base 404 may be formed of the same or different metal materials. Moreover, the body 402 and the insert base 404 can be integrally formed by the same process and formed at the same time. Furthermore, it is also possible to employ two processes, first forming the embedded base 404 and then forming the body 402 on the embedded base 404. Similarly, if the metal layer structure of the flexible multilayer substrate is used as a metal wiring, the metal layer which is joined to the upper side is another metal wiring.
  • the metal layer structure of the flexible multilayer substrate of the present invention can solve the disadvantages described in the prior art, and more effectively improve the reliability of the flexible multilayer substrate.
  • the material of the metal layer may be copper, and the material of the dielectric layer may be polyimide.
  • the metal layer structure manufacturing method of the flexible multilayer substrate of the present embodiment includes the following steps: coating a negative photoresist layer 306 on the first dielectric layer 200.
  • the negative photoresist layer 306 is exposed and developed at a predetermined position of the first metal layer 300.
  • the negative photoresist layer 306 at the predetermined location is removed. Since the photoresist layer above the negative photoresist layer 306 receives more light than the lower negative photoresist layer 306, the edge of the negative photoresist layer 306 adjacent to the predetermined position will form an upper side as shown in the figure.
  • a first metal layer 300 having a metal layer structure of the body 302 and the embedded base 304 is formed at a predetermined position as shown.
  • the embedded substrate 304 may extend outside the body 302 or may abut the negative photoresist layer 306.
  • the bottom edge area of the first metal layer is larger than the area of the top portion, i.e., the area of the embedded base 304 is larger than the area of the body 302.
  • the second dielectric layer 308 is overlying the body 302 and the embedded substrate 304 of the first metal layer 300.
  • the embedded substrate 304 is sandwiched by the first dielectric layer 200 and the second dielectric layer 308.
  • the via hole is formed at the position of the first metal layer 300, it can be bonded to the upper second metal layer (the package tin ball 310 or another metal line). If the first metal layer 300 is used as a hole pad, The package solder balls 310 are bonded and packaged. If the first metal layer 300 is used as a metal line, it is bonded to another metal line to realize internal communication of the flexible multilayer substrate.
  • FIG. 6 is a schematic diagram showing a manufacturing method of a second embodiment of a metal layer structure of a flexible multilayer substrate according to the present invention.
  • the first way is to directly form at least two upper and lower first photoresist layers 406 and a second photoresist layer 408 having different development rates.
  • the first photoresist layer 406 and the second photoresist layer 408 may be a positive photoresist layer or a negative photoresist layer, while the first photoresist layer 406 and the second photoresist layer 408 are simultaneously developed.
  • first photoresist layer 406 and the second photoresist layer 408 since the development rates of the first photoresist layer 406 and the second photoresist layer 408 are different, openings having different sizes as shown are formed.
  • the opening of the first photoresist layer 406 is larger than the opening of the second photoresist layer 408.
  • first metal layer 400 is formed at a predetermined position, a metal layer structure having the body 402 and the embedded base 404 is formed.
  • This manufacturing method can simultaneously form the body 402 and the embedded base 404 with the same metal material.
  • the method for fabricating the metal layer structure of the flexible multilayer substrate of the present invention comprises the following steps: coating the first dielectric layer 200 A photoresist layer 406.
  • the first photoresist layer 406 is developed at a predetermined position of the first metal layer 400.
  • the first photoresist layer 406 at a predetermined location is removed.
  • the embedded base 404 of the first metal layer 402 is formed at a predetermined position.
  • a second photoresist layer 408 is applied.
  • the second photoresist layer 408 is developed at a predetermined position of the first metal layer 400.
  • the second photoresist layer 408 at the predetermined position is removed such that the opening of the second photoresist layer 408 is smaller than the opening of the first photoresist layer 406.
  • the body 402 of the first metal layer 400 is formed at a predetermined position, and the formed body 402 is located above the embedded base 404, that is, the metal layer structure in which the bottom area of the embedded base 404 is larger than the bottom area of the body 402.
  • a second dielectric layer 308 is coated on the body 402 and the embedded substrate 404 of the first metal layer 400.
  • the embedded substrate 404 is sandwiched by the first dielectric layer 200 and the second dielectric layer 308.
  • the upper second metal layer (the package tin ball 310 or another metal line) can be bonded. If the first metal layer 400 is used as a hole pad, The package solder balls 310 are bonded and packaged; if the first metal layer 400 is used as a metal line, it is bonded to another metal line to realize internal communication of the flexible multilayer substrate.
  • the manufacturing method of the present invention can form the body 402 with the same or different metal materials in a two-step process, and then form the body 402 on the embedded substrate 404.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Laminated Bodies (AREA)

Description

柔性多层基板的金属层结构及其制造方法
【技术领域】
本发明涉及一种多层基板的金属层结构及其制造方法,尤其涉及关于一种 柔性多层封装基板的金属层结构及其制造方法。
【背景技术】
多层基板用于制作封装基板、 印刷电路板、 柔性封装基板及柔性电路板等 领域, 整合成高密度***为现今电子产品小型化必然趋势, 特别是利用柔性多 层基板制作柔性封装结构,则更能有效地应用于各类产品,符合微型化的需求。 柔性多层基板的厚度更薄, 多层基板的绕线密度 (routing density)越高, 柔性多 层基板的金属层结构的尺寸要求便越精细。现有技术中的柔性多层基板通常仅 制作二至三层, 每层厚度大约 50~60μηι, 金属层厚度则约 30μηι左右。
请参考附图 1所示为现有技术中柔性多层基板的金属层结构侧边产生气泡 时的示意图。现有的柔性多层基板具有一金属层 100、披覆于其上的介电层 102。 现有的柔性多层基板的金属层 100多以蚀刻法或叠层法形成金属层,若金属层 100作为金属线路或焊垫, 则如图所示其剖面形状是矩形或长方形。 而当制作 金属层时一常见的问题即如在金属层边缘产生气泡等因素,而如图所示导致附 着不良或剥离的现象。更因此可能导致柔性多层基板的制造良率下降。特别是 当前述柔性多层基板的制作厚度进一步变薄, 同时金属层厚度也更薄时, 前述 附着不良或剥离现象的影响会愈加明显。
请参考附图 2所示为现有技术的柔性多层基板的金属层结构可能因外力而 与封装锡球一同自多层基板被剥离的示意图。若金属层 100作为金属线路或焊 垫, 则如图所示其剖面形状为矩形或长方形。 且如果在金属层 100作为对 IC 进行封装连结的金属层的情况下,会对柔性多层基板中披覆在金属层 100上的 介电层 102进行开孔, 填入金属材料 106后与封装锡球 108接合。如前所述柔 性多层基板作为柔性封装基板及柔性电路板时, 是应用于多折曲的产品的中, 换言的, 此柔性基板被弯折时, 可能会发生因金属层 100与封装锡球 108间的 结合力强,金属层 100与封装锡球 108由于折曲外力一同自多层基板被剥离的 问题。 以上情况如附图 2所示。 同样地, 特别是当前述柔性多层基板的制作厚 度进一步更薄, 同时金属层厚度也更薄时, 前述剥离现象的影响会愈加明显。 【发明内容】
本发明所要解决的技术问题是,研宄一种柔性多层基板的金属层结构及其 制造方法,在柔性多层基板的制作厚度进一步变薄,同时金属层厚度也更薄时, 仍能有效解决前述问题, 金属层结构不易与所接触的介电层发生脱层或分离, 具有更高可靠性。
为了解决上述问题, 本发明提供了一种柔性多层基板的金属层结构, 包括 一第一金属层以及一介电层。第一金属层具有一本体及一嵌基, 本***于嵌基 上方, 且嵌基的底面积大于本体的底面积。介电层披覆于第一金属层的本体及 嵌基上, 在第一金属层的位置开设一导通孔, 用于使第一金属层的本体与介电 层上的一第二金属层接合。本体及嵌基可为一体成型且同时形成。或者也可以 采用相同或不同的金属材料, 以不同的工艺先形成嵌基后, 再于嵌基上形成本 体。
本发明还提出一种柔性多层基板的金属层结构制造方法, 包括下述步骤: 于第一介电层上涂布至少一光刻胶层; 于第一金属层的预定位置, 对光刻胶层 进行显影; 移除位于预定位置的光刻胶层; 以及在预定位置形成第一金属层, 其中第一金属层的底部边缘面积大于顶部面积, 或可抵至光刻胶层, 以形成具 有本体及嵌基的金属层结构。
本发明进一步提出另一种柔性多层基板的金属层结构制造方法,包括下述 步骤: 于第一介电层上涂布第一光刻胶层; 于第一金属层的预定位置, 对第一 光刻胶层进行显影; 移除位于预定位置的第一光刻胶层; 在预定位置形成第一 金属层的嵌基; 移除第一光刻胶层后, 涂布第二光刻胶层; 于第一金属层的预 定位置, 对第二光刻胶层进行显影; 移除位于预定位置的第二光刻胶层, 使第 二光刻胶层的开口小于第一光刻胶层的开口; 以及在预定位置形成第一金属层 的本体, 形成嵌基位于本体下方, 且嵌基的底面积大于本体底面积的金属层结 构。
本发明的优点在于, 所述柔性多层基板的金属层结构不仅能用于封装基 板, 更可应用于制作柔性印刷电路板或柔性封装基板的技术领域。而本发明金 属层结构制造方法的精神在于制作出具有本体及嵌基的金属层结构, 当上方披 覆第二介电层后,能使厚度薄的柔性多层基板的金属层结构不易与其相邻接触 的介电层发生脱层或分离现象, 作为柔性多层基板的孔垫或金属线路, 能具有 更高的可靠度。
【附图说明】
附图 1是现有技术柔性多层基板的金属层结构侧边产生气泡时的示意图; 附图 2是现有技术柔性多层基板的金属层结构可能因外力而与封装锡球一 同自多层基板被剥离的示意图;
附图 3 是表示本发明柔性多层基板的金属层结构第一实施例的剖面示意 图;
附图 4 是表示本发明柔性多层基板的金属层结构第二实施例的剖面示意 图;
附图 5是表示本发明柔性多层基板的金属层结构第一实施例的制作方法示 意图;
附图 6是表示本发明柔性多层基板的金属层结构第二实施例额制作方法示 意图。
【具体实施方式】
下面结合附图对本发明提供的柔性多层基板的金属层结构及其制作方法 的具体实施方式做详细说明。
请参考附图 3所示为本发明柔性多层基板的金属层结构第一实施例的剖面 示意图。 在此实施例中, 柔性多层基板的金属层结构用以作为孔垫, 柔性多层 基板用以对一 未显示:)进行封装连结。柔性多层基板的金属层结构包括第一 金属层 300, 其具有本体 302与嵌基 304以及第二介电层 308。 柔性多层基板 还具有在其下方的第一介电层 200,如图 3所示,本体 302位于嵌基 304上方, 且嵌基 304的底面积大于本体 302的底面积。第二介电层 308则披覆于第一金 属层 300的本体 302及嵌基 304上。 当披覆第二介电层 308后, 如图所示嵌基 304即为第一介电层 200及第二介电层 308所包夹。
在本体 302上方的第二介电层 308设置一导通孔,使本体 302与封装锡球 310接合, 对 IC 未显示:)进行封装连结。 若第一金属层 300侧边产生气泡, 嵌 基 304能减少由于气泡而导致剥离和脱层所产生的影响。再者,第一金属层 300 与第一介电层 200间的结合虽具有一定强度, 本具体实施方式则利用嵌基 304 被第一介电层 200和第二介电层 308所包夹的力量可有效防止当柔性多层基板 被折曲时,发生第一金属层 300与封装锡球 310—同自多层基板被剥离的问题。 特别是当本具体实施方式柔性多层基板所制作的层数达 6至 7层,甚至 10层, 且其实际厚度已薄至每层约 ΙΟμηι, 第一金属层 300厚度更仅有 5μηι左右, 远 较现有技术的厚度薄许多, 更需要避免金属层结构侧边产生气泡、 金属层与相 邻接触介电层附着不良或剥离的现象。在本具体实施方式中, 虽以柔性多层基 板的金属层结构用作为孔垫为例, 同样地若柔性多层基板的金属层结构用作为 金属线路, 则上方与其接合的则为另一层的金属线路。 同样地, 能避免金属层 结构与邻近接触的介电层间发生附着不良或剥离现象。 因此, 本具体实施方式 性多层基板的金属层结构能解决现有技术所面临的缺点,而更有效提高柔性多 层基板的可靠性。
请参考附图 4所示为本发明柔性多层基板的金属层结构第二实施例的剖面 示意图。 在此实施例中, 柔性多层基板的金属层结构用以作为孔垫, 柔性多层 基板用以对一 未显示:)进行封装连结。柔性多层基板的金属层结构包括第一 金属层 400, 其具有本体 402与嵌基 404以及第二介电层 308。 柔性多层基板 在其下方还具有第一介电层 200, 如图所示, 本体 402位于嵌基 404上方, 且 嵌基 404的底面积大于本体 402的底面积。第二介电层 308则披覆于第一金属 层 300的本体 302及嵌基 304上。当披覆第二介电层 308后,如图所示嵌基 404 即为第一介电层 200及第二介电层 308所包夹。于本体 402的上方第二介电层 308设置一导通孔, 使本体 402与封装锡球 310接合, 对 IC(未显示:)进行封装 连结。
如图中所示, 与本发明的第一实施例不同的是, 第二实施例中, 本体 402 与嵌基 404可以相同或不同的金属材料形成。 并且, 本体 402与嵌基 404可以 采用同一种工艺一体成形, 同时形成。 再者, 还可以采用两道工艺, 先形成嵌 基 404后, 再于嵌基 404上形成本体 402。 同样地若柔性多层基板的金属层结 构用作为金属线路, 则上方与其接合的则为另一层的金属线路。
本实施例也能够避免第一金属层 400侧边产生气泡导致剥离、脱层产生的 影响,或金属层结构与邻近接触的介电层间发生附着不良或剥离的现象。因此, 本发明柔性多层基板的金属层结构能解决现有技术所述的缺点,而更有效的提 高柔性多层基板的可靠性。 再者, 本发明的第一实施例、 第二实施例中, 金属 层的材料可为铜, 介电层的材料则可为聚酰亚胺。
请参考附图 5所示为本发明柔性多层基板的金属层结构第一实施例的制作 方法示意图。 请一并参照附图 3, 本实施例柔性多层基板的金属层结构制造方 法包括下列步骤:在第一介电层 200上涂布负光刻胶层 306。在第一金属层 300 的预定位置, 对负光刻胶层 306进行曝光与显影。移除位于预定位置的负光刻 胶层 306。 而由于负光刻胶层 306上方的光刻胶层受光程度较下方的负光刻胶 层 306为多, 因此邻接预定位置的负光刻胶层 306边缘会形成如图中所示上侧 较下侧突出的结构。 接着, 如图所示在预定位置形成第一金属层 300, 具有本 体 302及嵌基 304的金属层结构。 并且形成第一金属层 300时, 由于负光刻胶 层 306边缘上侧较下侧突出, 因此嵌基 304会向本体 302外延伸, 或可抵至负 光刻胶层 306。 如附图 3所示第一金属层的底部边缘面积大于顶部的面积, 即 嵌基 304的面积大于本体 302的面积。
如附图 3中所示, 去除负光刻胶层 306后, 在第一金属层 300的本体 302 及嵌基 304上披覆第二介电层 308。 嵌基 304即被第一介电层 200及第二介电 层 308所包夹。接着, 在第一金属层 300的位置开设导通孔后即可与上方的第 二金属层 (封装锡球 310或另一金属线路)接合, 若第一金属层 300作为孔垫, 则是与封装锡球 310接合, 进行封装; 若第一金属层 300作为金属线路, 则是 与另一金属线路接合, 实现柔性多层基板的内联通。
请参考附图 6所示为本发明柔性多层基板的金属层结构第二实施例的制作 方法示意图。本发明第二实施例的制作方法可以有两种方式。第一种方式是直 接形成至少两层不同显影速率的上下侧第一光刻胶层 406 和第二光刻胶层 408。 第一光刻胶层 406与第二光刻胶层 408可为正光刻胶层或负光刻胶层, 虽同时对第一光刻胶层 406和第二光刻胶层 408进行显影。但由于第一光刻胶 层 406和第二光刻胶层 408显影速率不同,因此形成如图所示大小不同的开口。 第一光刻胶层 406的开口大于第二光刻胶层 408的开口。当于预定位置形成第 一金属层 400时, 即会形成具有本体 402及嵌基 404的金属层结构。本发明的 此制造方法能以相同的金属材料, 同时形成本体 402及嵌基 404。
请一并参照附图 4, 本发明第二实施例若以第二种方式制作, 则本发明柔 性多层基板的金属层结构制造方法包括下列步骤:在第一介电层 200上涂布第 一光刻胶层 406。 在第一金属层 400的预定位置, 对第一光刻胶层 406进行显 影。 移除位于预定位置的第一光刻胶层 406。 在预定位置形成第一金属层 402 的嵌基 404。 移除第一光刻胶层 406后, 涂布第二光刻胶层 408。 在第一金属 层 400的预定位置, 对第二光刻胶层 408进行显影。移除位于预定位置的第二 光刻胶层 408, 使第二光刻胶层 408的开口小于第一光刻胶层 406的开口。 于 预定位置形成第一金属层 400的本体 402,形成的本体 402位于嵌基 404上方, 即完成嵌基 404底面积系大于本体 402底面积的金属层结构。
接着, 如附图 4所示, 在第一金属层 400的本体 402及嵌基 404上披覆一 第二介电层 308。 嵌基 404即被第一介电层 200及第二介电层 308所包夹。 接 着, 在第一金属层 400 的位置开设导通孔后即可与上方的第二金属层 (封装锡 球 310或另一金属线路)接合, 若第一金属层 400作为孔垫, 则是与封装锡球 310接合, 进行封装; 若第一金属层 400作为金属线路, 则是与另一金属线路 接合, 实现柔性多层基板的内联通。 本发明的此制造方法能以相同或不同的金 属材料, 以两步工艺先形成嵌基 404后, 再于嵌基 404上形成本体 402。
以上所述仅是本发明的优选实施方式, 应当指出, 对于本技术领域的普通 技术人员, 在不脱离本发明原理的前提下, 还可以做出若干改进和润饰, 这些 改进和润饰也应视为本发明的保护范围。

Claims

1. 一种柔性多层基板的金属层结构, 其特征在于, 包括:
一第一金属层, 具有一本体及一嵌基, 所述本***于所述嵌基上方, 且所 述嵌基的底面积大于所述本体的底面积; 以及
一介电层, 披覆于所述第一金属层的所述本体及所述嵌基上, 在所述第一 金属层的位置开设一导通孔, 用于使所述第一金属层的所述本体与所述介 电层上方的一第二金属层接合。
2. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述本 体及所述嵌基为一体成型且同时形成。
3. 根据权利要求 2所述的柔性多层基板的金属层结构, 其特征在于, 所述第 一金属层的所述本体及所述嵌基同时形成。
4. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述本 体及所述嵌基以相同的金属材料形成。
5. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述本 体及所述嵌基以两种金属材料形成。
6. 根据权利要求 5所述的柔性多层基板的金属层结构, 其特征在于, 所述本 体及所述嵌基以两步工艺形成, 先形成所述嵌基后再于所述嵌基上形成所 述本体。
7. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述第 一金属层的材料为铜。
8. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述第 二金属层的材料为铜。
9. 根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述第 二金属层的材料为锡。
10.根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述介 电层的材料为聚酰亚胺。
11.根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述第 一金属层为所述柔性多层基板的孔垫。
12.根据权利要求 11所述的柔性多层基板的金属层结构, 其特征在于, 所述第 二金属层为封装用的锡球。
根据权利要求 1所述的柔性多层基板的金属层结构, 其特征在于, 所述第 一金属层为所述柔性多层基板中的金属线路。
根据权利要求 13所述的柔性多层基板的金属层结构, 其特征在于, 所述第 二金属层为所述柔性多层基板中的金属线路。
一种柔性多层基板的金属层结构制造方法, 其特征在于, 包括如下步骤: 在一第一介电层上涂布至少一光刻胶层;
在一第一金属层的预定位置, 对所述光刻胶层进行显影;
移除位于所述预定位置的所述光刻胶层; 以及
在所述预定位置形成所述第一金属层, 其中所述第一金属层的底部边缘面 积大于顶部的面积, 以形成具有一本体及一嵌基的所述金属层结构。
根据权利要求 15所述的柔性多层基板的金属层结构制造方法,其特征在于, 在形成所述第一金属层的步骤后, 进一步包括在所述第一金属层的所述本 体及所述嵌基上一披覆一第二介电层的步骤。
根据权利要求 16所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述嵌基被所述第一介电层及所述第二介电层所包夹。
根据权利要求 16所述的柔性多层基板的金属层结构制造方法,其特征在于, 在披覆所述第二介电层的步骤后, 进一步包括一在所述第一金属层的位置 开设一导通孔的步骤, 用于使所述本体与所述第二介电层上的一第二金属 层接合。
根据权利要求 18所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层的材料为铜。
根据权利要求 18所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层的材料为锡。
根据权利要求 20所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层为封装用的锡球。
根据权利要求 16所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一介电层与所述第二介电层的材料为聚酰亚胺。 根据权利要求 15所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一金属层的材料为铜。
根据权利要求 15所述的柔性多层基板的金属层结构制造方法,其特征在于, 在涂布至少一光刻胶层的步骤中涂布一负光刻胶层。
根据权利要求 24所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一金属层的所述本体及所述嵌基系同时形成。
根据权利要求 15所述的柔性多层基板的金属层结构制造方法,其特征在于, 在涂布至少一光刻胶层的步骤中涂布至少两层不同显影速率的上下侧光刻 胶层,且所述上侧光刻胶层的显影速度小于所述下侧光刻胶层的显影速度。 根据权利要求 26所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一金属层的所述本体及所述嵌基同时形成。
一种柔性多层基板的金属层结构制造方法, 其特征在于, 包括如下步骤: 在一第一介电层上涂布一第一光刻胶层;
在一第一金属层的预定位置, 对所述第一光刻胶层进行显影;
移除位于所述预定位置的所述第一光刻胶层;
在所述预定位置形成所述第一金属层的一嵌基;
移除所述第一光刻胶层后, 涂布一第二光刻胶层;
在所述第一金属层的所述预定位置, 对所述第二光刻胶层进行显影; 移除位于所述预定位置的所述第二光刻胶层, 使所述第二光刻胶层的开口 小于所述第一光刻胶层的开口; 以及
在所述预定位置形成所述第一金属层的一本体, 形成的所述本***于所述 嵌基上方, 且所述嵌基的底面积大于所述本体的底面积的金属层结构。 根据权利要求 28所述的柔性多层基板的金属层结构制造方法,其特征在于, 在形成所述第一金属层的步骤后, 进一步包括一在所述第一金属层的所述 本体及所述嵌基上披覆一第二介电层的步骤。
根据权利要求 29所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述嵌基为所述第一介电层及所述第二介电层所包夹。
根据权利要求 29所述的柔性多层基板的金属层结构制造方法,其特征在于, 在披覆所述第二介电层的步骤后, 进一步包括一在所述第一金属层的位置 开设一导通孔的步骤, 用于使所述本体与所述第二介电层上的一第二金属 层接合。
根据权利要求 31所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层的材料为铜。
根据权利要求 31所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层的材料为锡。
根据权利要求 33所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第二金属层为封装用的锡球。
根据权利要求 29所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一介电层与所述第二介电层的材料为聚酰亚胺。
根据权利要求 29所述的柔性多层基板的金属层结构制造方法,其特征在于, 所述第一金属层的材料为铜。
PCT/CN2010/070351 2009-10-19 2010-01-25 柔性多层基板的金属层结构及其制造方法 WO2011047544A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP20100824385 EP2493274A4 (en) 2009-10-19 2010-01-25 METAL SHIELD STRUCTURE FOR A MULTILAYER FLEXIBLE PLATE AND METHOD OF MANUFACTURING THEREOF
KR1020127011539A KR101395336B1 (ko) 2009-10-19 2010-01-25 다층 연성기판의 금속층 구조 및 그 제조방법
JP2012533460A JP5507697B2 (ja) 2009-10-19 2010-01-25 フレキシブル多層基板の金属層構造及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200910205487.6A CN102045939B (zh) 2009-10-19 2009-10-19 柔性多层基板的金属层结构及其制造方法
CN200910205487.6 2009-10-19

Publications (1)

Publication Number Publication Date
WO2011047544A1 true WO2011047544A1 (zh) 2011-04-28

Family

ID=43899795

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/070351 WO2011047544A1 (zh) 2009-10-19 2010-01-25 柔性多层基板的金属层结构及其制造方法

Country Status (5)

Country Link
EP (1) EP2493274A4 (zh)
JP (1) JP5507697B2 (zh)
KR (1) KR101395336B1 (zh)
CN (1) CN102045939B (zh)
WO (1) WO2011047544A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10729009B2 (en) * 2016-05-16 2020-07-28 Murata Manufacturing Co., Ltd. Ceramic electronic component

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106604540B (zh) * 2015-10-19 2019-08-13 南昌欧菲光电技术有限公司 电路板
KR102493465B1 (ko) * 2016-03-22 2023-01-30 삼성전자 주식회사 인쇄회로기판 및 이를 가지는 반도체 패키지
CN106711085B (zh) * 2016-12-12 2019-02-19 东莞市广信知识产权服务有限公司 一种柔性互连金属的制备方法
WO2024058641A1 (ko) * 2022-09-16 2024-03-21 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020162687A1 (en) * 2001-02-26 2002-11-07 Nishimoto Akihiko Multi-layer wiring board and method of producing the same
US20030137056A1 (en) * 2002-01-18 2003-07-24 Fujitsu Limited Circuit substrate and method for fabricating the same
JP2005098861A (ja) * 2003-09-25 2005-04-14 Kyocera Corp マイクロ空間配線基板及びその製造方法
CN1671268A (zh) * 2004-03-19 2005-09-21 松下电器产业株式会社 柔性基板、多层柔性基板及它们的制造方法
CN101312620A (zh) * 2007-05-24 2008-11-26 巨擘科技股份有限公司 多层基板金属线路制造方法及其结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202491A (ja) * 1985-03-05 1986-09-08 日立化成工業株式会社 配線板の製造法
JPS6482595A (en) * 1987-09-25 1989-03-28 Meiko Electronics Co Ltd Printed wiring board
JPH0722735A (ja) * 1993-07-05 1995-01-24 Ibiden Co Ltd プリント配線板
JP3890631B2 (ja) * 1996-08-08 2007-03-07 イビデン株式会社 プリント配線板の製造方法
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法
JP2000058986A (ja) * 1998-08-04 2000-02-25 Matsushita Electric Ind Co Ltd 配線基板およびその製造方法
JP2000164996A (ja) * 1998-11-30 2000-06-16 Kyocera Corp セラミック配線基板
JP4392677B2 (ja) * 1999-01-19 2010-01-06 イビデン株式会社 プリント配線板
JP2003298240A (ja) * 2002-04-05 2003-10-17 Sohwa Corporation 多層回路基板
JP2005243899A (ja) * 2004-02-26 2005-09-08 Toppan Printing Co Ltd プリント配線板及びその製造方法
KR100626617B1 (ko) * 2004-12-07 2006-09-25 삼성전자주식회사 반도체 패키지용 배선 기판의 볼 랜드 구조
TWI307613B (en) * 2005-03-29 2009-03-11 Phoenix Prec Technology Corp Circuit board formed conductor structure method for fabrication
KR100743233B1 (ko) * 2005-07-18 2007-07-27 엘지전자 주식회사 인쇄회로기판의 패드 및 그 제조방법
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
US20090133908A1 (en) * 2007-11-28 2009-05-28 Goodner Michael D Interconnect structure for a microelectronic device, method of manfacturing same, and microelectronic structure containing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020162687A1 (en) * 2001-02-26 2002-11-07 Nishimoto Akihiko Multi-layer wiring board and method of producing the same
US20030137056A1 (en) * 2002-01-18 2003-07-24 Fujitsu Limited Circuit substrate and method for fabricating the same
JP2005098861A (ja) * 2003-09-25 2005-04-14 Kyocera Corp マイクロ空間配線基板及びその製造方法
CN1671268A (zh) * 2004-03-19 2005-09-21 松下电器产业株式会社 柔性基板、多层柔性基板及它们的制造方法
CN101312620A (zh) * 2007-05-24 2008-11-26 巨擘科技股份有限公司 多层基板金属线路制造方法及其结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10729009B2 (en) * 2016-05-16 2020-07-28 Murata Manufacturing Co., Ltd. Ceramic electronic component
US11641712B2 (en) 2016-05-16 2023-05-02 Murata Manufacturing Co., Ltd. Ceramic electronic component
US11647581B2 (en) 2016-05-16 2023-05-09 Murata Manufacturing Co., Ltd. Ceramic electronic component

Also Published As

Publication number Publication date
EP2493274A1 (en) 2012-08-29
KR101395336B1 (ko) 2014-05-16
JP2013507777A (ja) 2013-03-04
CN102045939B (zh) 2014-04-30
KR20120084752A (ko) 2012-07-30
EP2493274A4 (en) 2014-04-16
JP5507697B2 (ja) 2014-05-28
CN102045939A (zh) 2011-05-04

Similar Documents

Publication Publication Date Title
JP4171499B2 (ja) 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
TWI387409B (zh) 內建半導體元件之印刷布線板及其製造方法
JP2012191204A (ja) プリント配線板の製造方法
JP2009141041A (ja) 電子部品実装用パッケージ
JP2006222164A (ja) 半導体装置及びその製造方法
JP2009253261A (ja) 高密度回路基板及びその形成方法
TWI484605B (zh) 封裝基板及其製造方法
WO2011047544A1 (zh) 柔性多层基板的金属层结构及其制造方法
JP4170266B2 (ja) 配線基板の製造方法
JP2003218264A (ja) 半導体装置用多層回路基板及びその製造方法並びに半導体装置
TWI402003B (zh) 軟性多層基板之金屬層結構及其製造方法
JP4203538B2 (ja) 配線基板の製造方法、及び配線基板
JP4759041B2 (ja) 電子部品内蔵型多層基板
JP4638657B2 (ja) 電子部品内蔵型多層基板
JP4549695B2 (ja) 配線基板の製造方法
JP2009004813A (ja) 半導体搭載用配線基板
KR20090051529A (ko) 전기소자 내장 다층 연성 인쇄회로기판 및 그 제조 방법
JP4549693B2 (ja) 配線基板の製造方法
JP2001223289A (ja) リードフレームと、その製造方法と、半導体集積回路装置と、その製造方法
JP4429280B2 (ja) 半導体搭載用配線基板の製造方法、及び半導体装置の製造方法
US20210136929A1 (en) Wiring board and method for manufacturing the same
JPH06168985A (ja) 半導体素子の実装構造
JP2006186396A (ja) 半導体搭載用配線基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10824385

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2010824385

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2012533460

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127011539

Country of ref document: KR

Kind code of ref document: A