TWI387409B - 內建半導體元件之印刷布線板及其製造方法 - Google Patents

內建半導體元件之印刷布線板及其製造方法 Download PDF

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TWI387409B
TWI387409B TW095147103A TW95147103A TWI387409B TW I387409 B TWI387409 B TW I387409B TW 095147103 A TW095147103 A TW 095147103A TW 95147103 A TW95147103 A TW 95147103A TW I387409 B TWI387409 B TW I387409B
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semiconductor element
built
wiring board
printed wiring
insulating film
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TW095147103A
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TW200806108A (en
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Yutaka Yoshino
Takahiro Shirai
Shinji Kadono
Mineo Kawamoto
Minoru Enomoto
Masakatsu Goto
Makoto Araki
Naoki Toda
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Nippon Cmk Kk
Renesas E Jp Semiconductor Inc
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Description

內建半導體元件之印刷布線板及其製造方法
本發明係關於以絶縁膜將半導體元件覆蓋之內建半導體元件之印刷布線板及其製造方法。
以往，隨著攜帶機器等之小型化、薄型化、高功能化的進展，而有將機器整體厚度薄化的要求。作為因應其要求之一的構想，乃提出一種內建半導體元件之印刷布線板。
以往，內建半導體元件之印刷布線板係於密封材上亦形成布線電路，且實施高密度布線(請參照例如專利文獻1)。
此外，習知之內建半導體元件之印刷布線板，主要係對於有機基板施加挖孔加工以形成凹部，且於該凹部搭載半導體元件，並藉由打線接合(wire bonding)連接，再以密封材將前述半導體元件密封後，於上層形成布線層(請參照例如專利文獻2)。
[專利文獻1]日本特開平9－46046號公報[專利文獻2]日本特開2001－15926號公報
然而，習知之內建半導體元件之印刷布線板具有下列問題。
首先，使用圖9(A)說明上述習知之內建半導體元件之印刷布線板之第1問題點。如該圖9(A)所示之內建半導體元件之印刷布線板600係於將半導體元件602打線接合603連接於基底基板601之後，包括該打線接合603，藉由密封材604將半導體元件602密封而構成。然而，為了要緩和半導體元件602與有機基板之側方及上層之布線層605的線膨脹係數，密封材604包含有許多無機填充物(filler)，而成為樹脂成分較少的組成，因此會因為形成電路時的除膠渣(desmear)處理，而容易使只有密封材604之表面過於粗化，且因為在後步驟的熱履歷等而使布線電路與密封材604的密著性變弱而易於剝離的問題產生。圖9(B)係表示此種布線電路剝離606之狀態的剖面圖。
接著，茲就圖10(A)所示埋入有半導體元件701之印刷布線板700之習知的第2問題點進行說明。該內建半導體元件之印刷布線板700係將半導體元件701搭載於絕緣基板之施加有挖孔加工的凹部，且於打線接合702連接後，包括該打線接合702在內，將半導體元件701藉由作為密封材703之環氧樹脂密封而構成。
然而，若調節密封材703的填充量而以較少量填充時，則在與上層的布線層之間會產生間隙704，且間隙在表面安裝零件進行安裝之際，會因為回焊等的加熱而膨脹，產生裂縫(crack)或如圖10(B)所示產生上層之布線基板剝離705的問題。
再者，茲使用圖11(A)說明習知之第3問題點。如該圖11(A)所示之內建半導體元件之印刷布線板800係包括打線接合在內，將半導體元件藉由密封材801密封而構成。然而，密封材801的填充量增多時，由於密封材801亦會溢出於側方的布線基板上面，因此會有研磨步驟增加的問題。
再者，不僅研磨步驟增加，且由於密封材的材質與側方之布線基板的材質不同，因此難以進行均勻的研磨，如圖11(B)所示，亦會有在密封材801表面容易形成凹凸802的問題產生。
無法將填充有密封材801的面進行均勻地研磨時，上層的布線層亦會受到凹凸的影響而難以形成平坦。亦即，上層的布線層會受到凹凸的影響，而於布線電路形成時難以形成微細電路(尤其是50 μm)以下的電路。
再者，由於在密封材801含有許多無機填充物等的填充材，因此與上層之布線基板間的密著性亦產生問題。
此外，若將搭載有半導體元件之凹部全部以密封材801來覆蓋，則如上所述，由於密封樹脂有較多無機填充物的填充量，而樹脂成分較少，因此在層間連接之通孔(through hole)或導孔(via)等之開孔步驟後進行除膠渣處理之際，會有無法保持孔的形狀的問題產生。
本發明係有鑑於上述之習知問題而研創者，其課題在提供一種內建半導體元件之印刷布線板及其製造方法，將半導體元件內建於印刷布線板內，即使以密封材覆蓋半導體元件使其免於吸濕，也不會有因為密封材之填充不足所產生之間隙的問題，而且反之即使填充過度的填充材，亦不須研磨等的後步驟，具有與上層之布線基板間之優異的密著性。
本發明係藉由內建半導體元件之印刷布線板以解決上述問題者，該內建半導體元件之印刷布線板之特徵為：以絕緣膜覆蓋內建之半導體元件之至少下面、上面或側面，同時在其側方及上方形成有絕緣層。
此外，本發明係藉由內建半導體元件之印刷布線板之製造方法以解決上述問題者，該製造方法之特徵為包含：於基底基板搭載半導體元件，且以絕緣膜覆蓋該半導體元件之至少下面、上面或側面之步驟；將半硬化狀態之絕緣薄片(sheet)配置且層疊於前述半導體元件之側方之步驟；及將半硬化狀態之絕緣薄片配置且層疊於前述半導體元件之上方的步驟。
此外，本發明係藉由內建半導體元件之印刷布線板之製造方法以解決上述問題者，該製造方法之特徵為包含：於基底基板搭載半導體元件，且以第1絕緣膜覆蓋該半導體元件之下面或上面之步驟；將半硬化狀態之絕緣薄片配置於前述半導體元件之側方之步驟；將半硬化狀態之絕緣薄片配置於前述半導體元件之上方的步驟；及將前述側方及上層之半硬化狀態之薄片同時層疊並以第2絕緣層覆蓋半導體元件之側面及/或上面之步驟。
依據本發明，由於所搭載之半導體元件至少由第1絕緣膜所覆蓋，因此可緩和有機基板與半導體元件之線膨脹係數，再者，由於第2絕緣膜的存在，故可以保護半導體元件免於吸濕。其結果，可提升與上層之布線基板間的密著性。
此外，在本發明中，由於使用半硬化狀態的絕緣薄片，且以第2絕緣膜來填埋半導體元件周圍的間隙，故可將層間連接導孔形成到第1絶縁膜的附近。
再者，亦可消除密封材的填充不足或過多的問題。
茲使用圖1說明本發明之內建半導體元件之印刷布線板之第1實施形態。
在圖1(a)中，100係內建半導體元件之印刷布線板，以下說明此結構。
3層的基底基板101係由增層(build－up)基板所形成，在搭載半導體元件102的面係形成有用以保護安裝焊墊103以外的保護膜104。藉由銲錫105的覆晶接合而使半導體元件102連接於基底基板101，且使至少第1絕緣膜106，藉由以填底膠(underfill)形成之密封材的填充而形成於基底基板101側，亦即形成於半導體元件102下面與基底基板101的連接端子面。在半導體元件102之側方與上方，係藉由半硬化狀態的絕緣薄片的層疊而形成有絕緣層107，同時由該層疊之際的熱所熔融的絕緣樹脂所形成之半導體元件102之周圍及第1絕緣膜106之周圍的間隙係藉由第2絕緣膜108來填埋。
在此實施形態中，由於在半導體元件102之下面與連接電極面，存在有藉由以填底膠而成之密封材的填充所形成之第1絕緣膜106，因此可緩和作為半導體元件102之矽與有機基板之線膨脹係數，而防止因為後步驟之熱履歷等所造成之半導體元件102的連接不良。
此外，半導體元件102之周圍及第1絕緣膜106之周圍的間隙，由於係藉由因半硬化狀態之絕緣薄片107之層疊時之熱而熔融之絕緣樹脂所形成之第2絕緣膜108來填埋，因此可防止裂縫的產生，而提昇側方及上方之絕緣層的密著性。
第1絕緣膜106為了緩和作為半導體元件102之矽與有機基板之線膨脹係數，故有較多無機填充物的填充量，而樹脂成分較少。因此，藉由第2絕緣膜108將半導體元件102及第1絕緣膜106加以覆蓋，即可解決與側方或上方之絕緣層107之密著性變差的問題。
再者，於半導體元件102之上層及下層亦形成增層層109，使布線電路110及層間連接導孔111的形成成為可能。在側方係設有用以聯繫半導體元件102之上下之增層層109的貫通通孔112。在此實施形態中雖係形成貫通通孔112，然而形成複數層層間連接導孔以聯繫表背之增層層亦無妨。
在最外層係形成有阻焊劑(solder resist)113與母板(mother board)連接用的焊球114。在此，焊球114形成於表背之任一面均無妨。
再者，如圖1(b)之內建半導體元件之印刷布線板150所示，係以在上述圖1(a)之半導體元件102的下方部，亦即在半導體元件102之正下方區域至少存在有零件的一部分之方式，經由銲錫搭載被動零件115，同時將與母板連接用之焊球114形成於半導體元件102之上方側最外層亦無妨。此外，該被動零件115亦可經由層間連接導孔111與半導體元件102連接。在此所稱之被動零件係例如為電容器、電阻、線圈、電感等，該等均係為晶片型，不論形成形態為何，可適當組合其中1或2個以上來使用。
如此，藉由將被動零件配置於半導體元件102之下方部，該內建之半導體元件102與所搭載之被動零件115之布線距離即可縮短，而降低該半導體元件102與被動零件115之連接阻抗，且可使由於被動零件115所產生之電源線的雜訊去除效果或電源電壓安定效果更為良好。
茲使用圖2說明本發明之內建半導體元件之印刷布線板之第2實施形態。
在第2圖中，200係內建半導體元件之印刷布線板，以下說明此結構。
第2實施形態之內建半導體元件之印刷布線板200係藉由第1絕緣膜204將所內建之半導體元件202之上面及側面加以覆蓋，同時又以線膨脹係數不同的第2絕緣膜205將該第1絕緣膜204加以覆蓋以外，其餘均以與第1實施形態之內建半導體元件之印刷布線板100相同方式構成。
此外，上述相異點係導因於該半導體元件202並非覆晶連接，而為打線接合203連接之故。
茲使用圖3至圖4說明本發明之內建半導體元件之印刷布線板之製造方法之第1實施形態。
首先，如圖3(a)所示，茲準備兩面銅面積層板300，如圖3(b)所示，藉由雷射加工形成非貫通孔301。接著，藉由無電解．電解銅鍍對於包括非貫通孔301的全面施行銅鍍處理，且如圖3(C)所示，藉由照相法僅於片側施以布線電路302。接著，如圖3(d)所示，將增層基材303層疊，藉由雷射加工形成非貫通孔，並全面實施無電解．電解銅鍍，並僅於藉由照相法層疊的增層基材面形成布線電路304。接著，如圖3(e)所示，在除了與半導體元件之連接端子之接合部分以外的全面形成保護層305，以獲得3層結構的基底基板306。另外，在此雖係顯示使用此3層結構之基底基板之態樣，然而並不以此為限，亦可使用兩面或4層以上之多層印刷布線板作為基底基板。
接著，如圖3(f)所示，以覆晶安裝方式藉由銲錫308連接半導體元件307。接著，使用在環氧樹脂填充有無機填充物的密封材，將基底基板306側，亦即半導體元件307之下面及連接端子部予以密封，形成第1絕緣膜309。另外，以半導體元件307之安裝方法而言，另亦有打線接合法等。
此外，以覆晶連接法而言，例如有Au銲錫接合、銲錫接合、Au．超音波接合、AU．ACF接合等。
在此第1絕緣膜309係至少將半導體元件307之下面及連接端子部加以密封，藉此以達成緩和半導體元件307之線膨脹係數與有機基板之線膨脹係數之不同的功用。
接著，如圖4(g)所示，將設有與所搭載之半導體元件307對應之開口部的複數片半硬化狀態的絕緣薄片310、及不存在有該開口部之半硬化狀態的絕緣薄片310加以重疊，並且更重疊銅箔311而層疊。
在此，以半硬化狀態之絕緣薄片310而言，係適當使用將環氧樹脂浸漬於玻璃纖維的預浸材料(prepreg)或將二氧化矽(silica)等無機填充物混入於環氧樹脂之增層基材等。
接著，如圖4(h)所示，在使因為半硬化狀態之絕緣薄片310之層疊時之熱而熔融之樹脂所構成之第2絶縁膜311硬化形成之後，形成貫通孔且進行除膠渣處理後，藉由無電解．電解銅鍍而形成獲得表背導通之貫通鍍覆通孔312，再藉由照相法形成表背兩面的布線電路313。
接著，如圖4(i)所示，將半硬化狀態之絕緣薄片314層疊於表背上下，且藉由半加成(semi－additive)法形成最外層的布線電路。亦即，首先，藉由雷射形成非貫通孔，全面析出無電解銅鍍，接著形成鍍覆阻劑，且僅於形成布線電路之部分曝光．顯影後，藉由電解銅鍍形成微細布線電路315，將鍍覆阻劑去除，再將所露出的無電解銅鍍去除，最後形成最外層的阻焊劑316，並形成用以搭載於母板之焊球317。在此，焊球317形成於表背之任一面均無妨。此外，在該半導體元件307之下方部係可與前述相同搭載被動零件(未圖示)。
茲使用圖5至6說明本發明之內建半導體元件之印刷布線板之製造方法之第2實施形態。
首先，如圖5(a)所示，準備兩面銅面積層板400，如圖5(b)所示藉由雷射加工形成非貫通孔401。接著，藉由無電解．電解銅鍍，對包括非貫通孔401的全面施以銅鍍覆處理，且如圖5(c)所示，藉由照相法僅於片側施以布線電路402。此時製作2片施以該配線電路402之基板。接著，如圖5(d)所示，在其中一片基板，於除了與半導體元件之連接端子之接合部分以外的全面形成保護層403，而獲得2層結構的基底基板404。另外，在此雖係顯示使用此2層結構之基底基板的態樣，然而並不以此為限，亦可使用3層或4層以上之多層印刷布線板作為基底基板。
接著，如圖5(e)所示，以覆晶安裝方式藉由銲錫406連接半導體元件405。接著，使用在環氧樹脂填充有無機填充物的密封材，將基底基板404側，亦即半導體元件405之下面及連接端子部予以密封，形成第1絕緣膜407。另外，以半導體元件之安裝方法而言，另亦有打線接合法等。
此外，以覆晶連接法而言，例如有Au銲錫接合、銲錫接合、Au．超音波接合、AU．ACF接合等。
在此第1絕緣膜407係至少將半導體元件405之下面及連接端子部加以密封，藉此以達成緩和半導體元件405之線膨脹係數與有機基板之線膨脹係數之不同的功用。
接著，如圖5(f)所示，將設有與所搭載之半導體元件405對應之開口部的複數片半硬化狀態的絕緣薄片408、及不存在有該開口部之半硬化狀態的絕緣薄片408加以重疊，並且更將圖5(c)所作成之僅於片側施有布線電路402之兩面基板409，使其電路形成面重疊於半硬化狀態之絕緣薄片側而層疊。
在此，以半硬化狀態之絕緣薄片408而言，係適當使用將環氧樹脂浸漬於玻璃纖維的預浸材料或將二氧化矽等無機填充物混入於環氧樹脂之增層基材等。
接著，如圖6(g)所示，在使因為半硬化狀態之絕緣薄片408之層疊時之熱而熔融之樹脂所構成之第2絶縁膜410硬化形成之後，形成貫通孔且進行除膠渣處理後，藉由無電解．電解銅鍍而形成獲得表背導通之貫通鍍覆通孔411，再藉由照相法形成表背兩面的布線電路412。
接著，如圖6(h)所示，將半硬化狀態之絕緣薄片413層疊於表背上下，且藉由半加成法形成最外層的布線電路。亦即，首先，藉由雷射形成非貫通孔，全面析出無電解銅鍍，接著形成鍍覆阻劑，且僅於形成布線電路之部分曝光．顯影後，藉由電解銅鍍形成微細布線電路414，且將鍍覆阻劑去除，再將所露出的無電解銅鍍去除，最後形成最外層的阻焊劑415，並形成用以搭載於母板之焊球416。在此，焊球416形成於表背之任一面均無妨。此外，在該半導體元件405之下方部係可與前述相同搭載被動零件(未圖示)。
茲使用圖7至8說明本發明之內建半導體元件之印刷布線板之製造方法之第3實施形態。
首先，如圖7(a)所示，將半硬化狀態之熱硬化性絕緣薄片500重疊於銅箔501而層疊。接著，如圖7(b)所示藉由雷射加工形成用以安裝半導體元件502之連接開口部503。在此之半硬化狀態之熱硬化性絕緣薄片500係相當於硬化後圖3、圖5所示之保護膜303、403，而基底基板係使用銅箔等金屬箔。
在此，以半硬化狀態之熱硬化性絕緣薄片500而言’亦可使用將環氧樹脂浸漬於玻璃纖維之預浸材料或將無機填充物等填充於熱硬化性樹脂之增層基材。此外，使用RCC等之附帶樹脂之銅箔亦無妨。
接著，如圖7(c)所示，以覆晶安裝方式藉由銲錫504連接半導體元件502。接著，使用在環氧樹脂填充有無機填充物的密封材，將基底基板側，亦即半導體元件502之下面及連接端子部予以密封，形成第1絕緣膜505。另外，以半導體元件之安裝方法而言，另亦有打線接合法等。
此外，以覆晶連接法而言，例如有Au銲錫接合、銲錫接合、Au．超音波接合等。
在此第1絕緣膜505係至少將半導體元件502之下面及連接端子部加以密封，藉此以達成緩和半導體元件之線膨脹係數與有機基板之線膨脹係數之不同的功用。
接著，如圖7(d)所示，將設有與所搭載之半導體元件502對應之開口部的複數片半硬化狀態的絕緣薄片506加以重疊，並且更重疊銅指507而層疊。由於在該層疊時之熱，如圖7(e)所示，半硬化狀態之絕緣薄片506的樹脂熔融，而形成用以填埋側方之絕緣層與半導體元件之間之間隙的第2絕緣膜508。接著，藉由照相法形成表背的布線電路509。
接著，如圖8(f)所示，將半硬化狀態之絕緣薄片510層疊於上下，且於形成貫通孔及非貫通孔之後，全面進行無電解．電解銅鍍處理，而形成獲得表面導通之貫通鍍覆通孔511，更藉由照相法形成表背的布線電路512。
接著，如圖8(g)所示，更將半硬化狀態之絕緣薄片513層疊於上下，形成非貫通孔且全面進行無電解．電解銅鍍處理之後，藉由照相法形成最外層的布線電路514，接著，形成阻焊劑515，形成用以搭載於母板之焊球516。
在此，焊球114形成於表背之任一面均無妨。
此外，在該半導體元件502之下方部係可搭載被動零件(未圖示)。
依據本發明，即可以內建有半導體元件之部分為中心製造上下對象結構之內建半導體元件之印刷布線板。此外，由於在製造步驟中亦係以內建有半導體元件之部分為中心而成為上下對象結構，因此具有即使是印刷布線板狀態亦難以產生翹曲之效果。
100、150、200、600、700、800．．．內建半導體元件之印刷布線板
101、201、306、404、601．．．基底基板
102、202、307、405、502、602、701．．．半導體元件
103．．．安裝焊墊
104、305、403．．．保護膜
105、308、406．．．銲錫
106、204、309、407、505．．．第1絕緣膜
107．．．絕緣層
108、205、311、410、508．．．第2絕緣膜
109．．．增層層
110、302、304、313、402、412、509、512、514．．．布線電路
111．．．層間連接導孔
112、312、411、511．．．貫通通孔
113、316、415、515．．．阻焊劑
114、317、416、516．．．焊球
115．．．被動零件
203、603、702．．．打線接合
300、400．．．兩面銅面積層板
301、401．．．非貫通孔
303．．．增層基材
310、314、408、413、500、506、510、513．．．半硬化狀態之絕緣薄片
315、414．．．微細布線電路
409．．．兩面基板
311、501、507．．．銅箔
503．．．開口部(半導體元件安裝用)
604、703、801．．．密封材
605．．．布線層
606、705．．．剝離
704．．．間隙
802．．．凹凸
圖1(a)、(b)係表示本發明之內建半導體元件之印刷布線板之第1實施形態之概略剖面說明圖。
圖2係表示本發明之內建半導體元件之印刷布線板之第2實施形態之概略剖面說明圖。
圖3(a)至(f)係表示本發明之內建半導體元件之印刷布線板之製造方法之第1實施形態之概略剖面圖。
圖4(g)至(i)係接續圖3之概略剖面步驟說明圖。
圖5(a)至(f)係表示本發明之內建半導體元件之印刷布線板之製造方法之第2實施形態之概略剖面說明圖。
圖6(g)至(h)係接續圖5之概略剖面步驟說明圖。
圖7(a)至(e)係表示本發明之內建半導體元件之印刷布線板之第3實施例形態之概略剖面步驟說明圖。
圖8(f)、(g)係接續圖7之概略剖面步驟說明圖。
圖9(A)、(B)係表示習知之內建半導體元件之印刷布線板之概略剖面說明圖。
圖10(A)、(B)係表示另一習知之內建半導體元件之印刷布線板之概略剖面說明圖。
圖11(A)、(B)係表示再一習知之內建半導體元件之印刷布線板之概略剖面說明圖。
100,150．．．內建半導體元件之印刷布線板
101．．．基底基板
102．．．半導體元件
103．．．安裝焊墊
104．．．保護膜
105．．．銲錫
106．．．第1絕緣膜
107．．．絕緣層
108．．．第2絕緣膜
109．．．增層層
110．．．布線電路
111．．．層間連接導孔
112．．．貫通通孔
113．．．阻焊劑
114．．．焊球
115．．．被動零件

Claims (12)

  1. 一種內建半導體元件之印刷布線板，其特徵為：於內建之半導體元件所接續之基底基板之半導體元件搭載面上形成用以保護安裝焊墊以外的保護膜，且以由密封材之填充所形成之第1絕緣膜覆蓋該半導體元件之下面，同時以由配置於半導體元件之側方及上方之絕緣層之熔融樹脂所形成之第2絕緣膜覆蓋該半導體元件及第1絕緣膜之周圍。
  2. 一種內建半導體元件之印刷布線板，其特徵為：於內建之半導體元件所接續之基底基板之半導體元件搭載面上形成用以保護安裝焊墊以外的保護膜，且以由密封材之填充所形成之第1絕緣膜覆蓋該半導體元件之上面及側面，同時以由配置於半導體元件之側方及上方之絕緣層之熔融樹脂所形成之第2絕緣膜覆蓋該第1絕緣膜。
  3. 如請求項1或2之內建半導體元件之印刷布線板，其中前述側方之絕緣層包含預浸材料或增層基材。
  4. 如請求項1或2之內建半導體元件之印刷布線板，其中前述上方之絕緣層包含預浸材料或增層基材。
  5. 如請求項1或2之內建半導體元件之印刷布線板，其中前述第1絕緣膜與第2絕緣膜之線膨脹係數不同。
  6. 如請求項1或2之內建半導體元件之印刷布線板，其中在前述內建之半導體元件之下方部配置有被動零件。
  7. 如請求項6之內建半導體元件之印刷布線板，其中前述被動零件經由層間連接導孔而與內建之半導體元件連 接。
  8. 如請求項6之內建半導體元件之印刷布線板，其中前述被動零件係電阻、電容器、線圈、電感器中任一者或二者以上之組合。
  9. 一種內建半導體元件之印刷布線板之製造方法，其特徵為包含：於形成有用以保護安裝焊墊以外的保護膜之基底基板搭載半導體元件，且以由密封材之填充所形成之第1絕緣膜覆蓋該半導體元件之下面之步驟；將半硬化狀態之絕緣薄片配置且層疊於前述半導體元件之側方及上方並以該絕緣薄片之熔融樹脂所形成之第2絕緣膜覆蓋前述半導體元件及第1絕緣膜之周圍之步驟。
  10. 一種內建半導體元件之印刷布線板之製造方法，其特徵為包含：於形成有用以保護安裝焊墊以外的保護膜之基底基板搭載半導體元件，且以由密封材之填充所形成之第1絕緣膜覆蓋該半導體元件之上面及側面之步驟；將半硬化狀態之絕緣薄片配置且層疊於前述半導體元件之側方及上方並以該絕緣薄片之熔融樹脂所形成之第2絕緣膜覆蓋前述第1絕緣膜之步驟。
  11. 如請求項9或10之內建半導體元件之印刷布線板之製造方法，其中配置於前述側方之半硬化狀態之絕緣薄片包含與半導體元件對應之開口部。
  12. 如請求項9或10之內建半導體元件之印刷布線板之製造方法，其中以銲錫接合前述半導體元件。
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JP5114041B2 (ja) 2013-01-09
CN101189717A (zh) 2008-05-28
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