TWI387049B - 半導體積體電路裝置之製造方法 - Google Patents

半導體積體電路裝置之製造方法 Download PDF

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TWI387049B
TWI387049B TW095142475A TW95142475A TWI387049B TW I387049 B TWI387049 B TW I387049B TW 095142475 A TW095142475 A TW 095142475A TW 95142475 A TW95142475 A TW 95142475A TW I387049 B TWI387049 B TW I387049B
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film
insulating film
wiring
forming
integrated circuit
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TW200805563A (en
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Hiroyuki Hayashi
Takayuki Oshima
Hideo Aoki
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Hitachi Ltd
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Description

半導體積體電路裝置之製造方法
本發明係關於半導體積體電路裝置之製造方法，特別為關於具有多層埋入配線之半導體積體電路裝置之製造方法。
埋入配線構造藉由稱為鑲嵌(Damascene)技術(單一鑲嵌(Single－Damascene)技術及雙道鑲嵌(Dual－Damascene)技術)之配線形成技術，在絕緣膜上形成之如配線溝槽或連接孔等之配線開口部內埋入配線材料而形成。
近年來，該等埋入配線之間隔伴隨半導體積體電路裝置之高積體化而逐漸減小。藉此，配線間之寄生電容增大，從而產生信號延遲。因此，期待降低配線間之寄生電容。
專利文獻1中揭示了在埋入配線之間形成空洞之技術。在本文獻之圖1A~1E中，按照步驟順序顯示了1層埋入配線之製造方法。圖示之技術由於在介隔於相鄰埋入配線間之絕緣膜上包含空洞，故具有可降低相鄰之埋入配線間之寄生電容之特徵。
[專利文獻]美國專利第6,159,845號説明書
專利文獻1中，沒有記載關於具有空洞構造之多層埋入配線之製造方法。本發明人等之檢討中已了解在以專利文獻1之技術形成多層埋入配線之情形，產生起因於導孔(Via)部之金屬埋入不良之導孔部之高電阻化之問題及在空洞上金屬成膜、無法降低相鄰埋入配線間之寄生電容之問題。該等原因如圖2所示，係由於在通常之光學微影術步驟之下層埋入配線(單一鑲嵌配線)65和上層埋入配線(雙道鑲嵌配線)68之導孔部66之間之重合偏差，導孔部66與下層之埋入配線65間之空洞67相接觸，在包含導孔部66之上層之埋入配線68之金屬成膜時，產生朝空洞之金屬滲入69及導孔部之金屬填入不良70。
以下，簡單地說明在本發明所揭示之發明中具有代表性者之概要。
本發明之半導體積體電路裝置之製造方法具有以下之步驟：(a)在半導體基板上方形成第1絕緣膜之步驟；(b)在上述第1絕緣膜上形成複數之配線溝槽之步驟；(c)在包含上述複數之配線溝槽之各個內部之上述第1絕緣膜上形成第1導體膜之步驟；(d)藉由去除上述複數之配線溝槽之外部之上述第1導體膜，在上述複數之配線溝槽之各個內部形成由上述第1導體膜構成之配線之步驟；(e)在上述第1絕緣膜及上述配線上形成由與上述第1絕緣膜不同之材料構成之第2絕緣膜之步驟；(f)採用覆蓋露出在後面步驟中形成之上述配線之上面之連接孔之形成區域之掩膜，蝕刻上述第2絕緣膜，藉此在上述連接孔之形成區域形成由上述第2絕緣膜構成之犧牲膜柱之步驟；(g)選擇性地去除未以上述犧牲膜柱覆蓋之區域之上述第1絕緣膜，在上述犧牲膜柱之下部留有上述第1絕緣膜之步驟；(h)在去除上述第1絕緣膜之上述配線間之空隙區域保留空洞之同時，在上述配線及上述犧牲膜柱上形成由與上述第2絕緣膜不同之材料構成之第3絕緣膜之步驟；(i)去除上述犧牲膜柱上之上述第3絕緣膜，露出上述犧牲膜柱上面之步驟；(j)去除上述犧牲膜柱，形成露出上述配線之上面之連接孔之步驟；(k)在上述連接孔之內部形成第2導體膜之步驟。
本發明之半導體積體電路裝置之製造方法具有以下之步驟：(a)在半導體基板上方形成第1絕緣膜之步驟；(b)藉由去除上述第1絕緣膜之一部分，形成在後面步驟中形成之第1鑲嵌配線用之複數之第1配線溝槽之步驟；(c)在包含上述複數之第1配線溝槽之各個內部之上述第1絕緣膜上形成上述第1導體膜之步驟；(d)藉由去除上述複數之第1配線溝槽之外部之上述第1導體膜，在上述複數之第1配線溝槽之各個內部形成由上述第1導體膜構成之上述第1鑲嵌配線之步驟；(e)在上述第1絕緣膜及上述第1鑲嵌配線上，形成由與上述第1絕緣膜不同之材料構成之第2絕緣膜之步驟；(f)採用覆蓋在後面步驟中形成之第2鑲嵌配線之導孔部用之複數之連接孔之形成區域之掩膜，蝕刻上述第2絕緣膜，藉此，在上述複數之連接孔之形成區域，形成由上述第2絕緣膜構成之複數之犧牲膜柱之步驟；(g)選擇性地去除未以上述犧牲膜柱覆蓋之區域之上述第1絕緣膜，並在上述犧牲膜柱之下部留有上述第1絕緣膜之步驟；(h)在去除上述第1絕緣膜之上述配線間之空隙區域保留空洞之同時，在上述配線及上述犧牲膜柱上，形成由與上述第2絕緣膜不同之材料構成之第3絕緣膜之步驟；(i)去除上述犧牲膜柱上之上述第3絕緣膜，並露出上述複數之犧牲膜柱上面之步驟；(j)藉由去除上述第3絕緣膜之一部分及上述複數之犧牲膜柱之上部，形成在後面步驟中形成之上述第2鑲嵌配線之配線部用之複數之第2配線溝槽之步驟；(k)藉由去除上述複數之犧牲膜柱之下部，形成上述複數之連接孔之步驟；(l)在包含上述複數之第2配線溝槽及上述複數之連接孔之各個內部之上述第3絕緣膜上，形成第2導體膜之步驟；(m)藉由去除上述複數之第2配線溝槽及上述複數之連接孔之外部之上述第2導體膜，在上述複數之第1配線溝槽及上述複數之連接孔之各個內部，形成由上述第2導體膜構成之上述第2鑲嵌配線之步驟。
以下，簡單地說明本專利申請所揭示之發明中，藉由具有代表性者而取得之效果。
根據本發明，可形成具有高可靠性之導孔連接、藉由空洞而降低寄生電容之多層埋入配線。
以下，參照圖式詳細説明本發明之實施例。另，在用於説明實施例之全圖上，對具有相同功能之構件標示相同之符號，並省略其重複説明。並且，在以下之實施例中，除特別必要時以外，原則上不重複説明同一或同樣之部分。
[實施例1]
圖1係顯示本發明之實施例1之半導體裝置之重要部分之剖面圖。
藉由場絕緣膜2，將半導體基板1主面分離在各元件區域，在各元件區域形成源極區域、漏極區域等擴散層3，在源極區域、漏極區域3之間之半導體基板1主面上，經由閘絕緣膜(未圖示)形成由多晶矽構成之閘極4，閘極4之側面則藉由侧壁绝緣膜5而覆蓋。
在半導體基板1主面上形成之擴散層3或閘極4，連接於貫通層間絕緣膜6之插栓7之一端，而插栓7之另一端與經由層間絕緣膜6積層之單一鑲嵌配線10連接。層間絕緣膜6依次堆積P－SiN膜(50 nm)、HDP－SiO膜(400 nm)、P－SiO膜(400 nm)之後，藉由CMP技術研磨500 nm左右(大面積配線上之研磨量)，將藉由閘極4等產生之元件段差平坦化。
插栓7依次藉由濺鍍堆積鈦膜(10 nm)、氮化鈦膜(50 nm)、藉由CVD堆積鎢膜之後，藉由CMP進行加工。
單一鑲嵌配線10依次藉由濺鍍堆積氮化鉭膜(15 nm)、鉭膜(15 nm)、銅膜(80 nm)、藉由電鍍法堆積銅膜(500 nm)之後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP技術而形成。
在單一鑲嵌配線10之相鄰間空隙細小部分，貫通具有空洞(Air－Gap)17之層間絕緣膜16，雙道鑲嵌配線23連接於單一鑲嵌配線10上。此時，在位於偏離單一鑲嵌配線10處之雙道鑲嵌配線23之導孔部之下方，殘留有在形成單一鑲嵌配線10時使用之絕緣膜之一部分之膜15。
雙道鑲嵌配線23、27、30與單一鑲嵌配線10同樣，依次藉由濺鍍堆積氮化鉭膜(15 nm)、鉭膜(15 nm)、銅膜(80 nm)、藉由電鍍法堆積銅膜(500 nm)之後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP技術而形成。
在雙道鑲嵌配線23之相鄰間空隙為細小部分，貫通具有空洞25之層間絕緣膜26，雙道鑲嵌配線27與雙道鑲嵌配線23連接。此時，在位於偏離雙道鑲嵌配線23處之雙道鑲嵌配線27之導孔部之下方，殘留有層間絕緣膜16之一部分之膜24。
在雙道鑲嵌配線27之相鄰間空隙為細小部分，貫通具有空洞28之層間絕緣膜29，雙道鑲嵌配線30與雙道鑲嵌配線27連接。此時，在位於偏離雙道鑲嵌配線27處之雙道鑲嵌配線30之導孔部之下方，殘留有層間絕緣膜26之一部分之膜31。
在本實施例中，因為導孔部與空洞不接觸，故可防止因導孔部之金屬埋入不良所致之高電阻化及因金屬朝空洞滲入所致之寄生電容之增大問題。
下面，關於本實施例1之半導體裝置之製造方法，以圖3至11為例，逐步驟加以説明。
首先，將半導體基板1主面藉由場絕緣膜2分離成各元件區域後，在各元件區域形成源極區域、漏極區域等擴散層3，在源極區域、漏極區域3之間之半導體基板1主面上，經由閘極絕緣膜(未圖示)形成由多晶矽構成之閘極4之後，藉由側壁絕緣膜5覆蓋閘極4之側面。
然後，在依次堆積P－SiN膜(50 nm)、HDP－SiO膜(400 nm)、P－SiO膜(400 nm)之後，藉由CMP技術研磨500 nm左右(大面積閘極上之研磨量)，使藉由閘極4等產生之元件段差平坦化，形成層間絕緣膜6。
然後，藉由通常之光學成像及乾式成像技術使連接孔開孔後，用Ar電漿去除連接孔之底部之自然氧化膜後，依次以濺鍍堆積Ti/TiN膜7a(10/50 nm)、CVDW膜7b(300 nm)之後，藉由CMP技術去除連接孔以外之Ti/TiN膜及CVDW膜，形成插栓7。
其次，堆積SiCN/SiC膜8(25/25 nm)、為無機絕緣膜之FSG膜(第1絕緣膜)9(300 nm)後，藉由通常之光學成像及乾式成像技術形成用於形成配線10之溝槽。
然後，用Ar電漿去除露出在溝槽底部之插栓7表面之自然氧化膜之後，依次堆積障壁金屬膜即藉由濺鍍之氮化鉭/鉭膜10 a(15/15 nm)、主導體膜即濺鍍銅膜/藉由電鍍法之銅膜(第1導體膜)10b(80/500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP技術去除溝槽以外之氮化鉭/鉭/銅膜，形成單一鑲嵌配線10。該狀態如圖3所示。
其次，堆積有機絕緣膜即SiLK膜(第2絕緣膜)11(700 nm)、P－TEOS膜12(100 nm)後，形成凸形狀之抗蝕層13。抗蝕層13為柱狀，形成為覆蓋用於露出在後面步驟中形成之單一鑲嵌配線10上面之連接孔之形成區域。該狀態如圖4所示。
然後，將抗蝕層13為掩膜蝕刻加工P－TEOS膜12，連續地以抗蝕層13及P－TEOS膜12為掩膜蝕刻加工SiLK膜11，並形成由SiLK膜構成之犧牲膜柱14。在該階段，殘留有SiLK膜表面之P－TEOS膜12。
其次，各向異性地蝕刻加工單一鑲嵌配線10間之FSG膜9，去除未被犧牲膜柱覆蓋之區域之FSG膜9。此時，殘留位於犧牲膜柱14之下方之FSG膜9之一部分，形成FSG膜15。該狀態如圖5所示。
其次，形成無機絕緣膜之FSG膜(第3絕緣膜)16(1200 nm)。此時，為在單一鑲嵌配線10之相鄰間空隙為細小部分形成空洞17，FSG膜16採用CVD法以低覆蓋之成膜條件堆積。並且，利用CVD法形成FSG膜16，形成初期以低覆蓋之成膜條件進行並形成空洞17，形成空洞17之後，以高覆蓋之成膜條件進行，亦可埋入犧牲膜柱14間。另，FSG膜16有必要堆積至其表面比犧牲膜柱14之上面還高之膜厚。該狀態如圖6所示。
其次，藉由CMP使FSG膜16之表面平坦化之同時，使犧牲膜柱14之表面露出，形成由FSG膜構成之雙道鑲嵌配線形成用之層間絕緣膜18。在該階段，P－TEOS膜12不殘留於犧牲膜柱14之表面。該狀態如圖7所示。
其次，形成雙道鑲嵌配線形成用之抗蝕層圖案20。該狀態如圖8所示。
然後，以抗蝕層圖案20為掩膜，以大致相同之蝕刻條件蝕刻加工犧牲膜柱14和層間絕緣膜18，從而形成雙道鑲嵌配線之配線部用之溝槽21。該狀態如圖9所示。
然後，用NH3 電漿選擇性地去除犧牲膜柱14，從而形成雙道鑲嵌配線之導孔部用之連接孔22。該狀態如圖10所示。
然後，將蝕刻聚合物去除洗淨後，與單一鑲嵌配線10之形成同樣，用Ar電漿去除露出於連接孔22之底部之單一鑲嵌配線10表面之自然氧化膜後，依次堆積障壁金屬膜即藉由濺鍍之氮化鉭/鉭膜23a(15/15 nm)、主導體膜即濺鍍銅膜/藉由電鍍法之銅膜(第2導體膜)23b(80/500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP去除連接孔22及溝槽21以外之氮化鉭/鉭/銅膜，形成單一鑲嵌配線23。該狀態如圖11所示。
圖1所示之狀態係藉由重複以上之步驟，顯示在相鄰之雙道鑲嵌配線23間或雙道鑲嵌配線27間之空隙狹小部分亦形成空洞25、28之多層之鑲嵌配線者。
在上述之實施例，顯示作為單一鑲嵌配線10或雙道鑲嵌配線23之主導體膜使用Cu之例，但並非僅限於此，亦可將Al、W、Ag、Au之內之至少一種金屬作為主導體膜而使用。
在本實施例，由於藉由製作犧牲膜柱，可將形成於相鄰之鑲嵌配線間之空洞從導孔部分離而形成，故即使產生重疊偏差等，也因為空洞和導孔部不會接觸，所以可穩定進行向具有空洞構造之下層鑲嵌配線上之導孔連接。
在上述之實施例，形成鑲嵌配線10、23等後，作為金屬蓋膜在鑲嵌配線表面選擇性地形成CoWB合金32、33，藉此可提高鑲嵌配線10、23等之可靠性。另，作為金屬蓋膜，非僅限於上述CoWB合金，亦可使用Co、W、Ni、Cr、Au中之任意一種金屬或金屬化合物。該狀態如圖12(a)、(b)所示。
又，在上述之實施例，在圖9中，以大致相同之蝕刻條件蝕刻加工犧牲膜柱14和層間絕緣膜18，形成雙道鑲嵌配線23之配線部用之溝槽21，但是，如圖13(a)~(c)所示，僅將犧牲膜柱14之上部回蝕至溝槽深度後，亦可在層間絕緣膜18形成溝槽35。然後，選擇性地去除犧牲膜柱之下部34而形成連接孔36。該方法在難以使犧牲膜柱14與層間絕緣膜18之蝕刻速率相等之情形下有效。
此外，在圖9或圖13(b)所示之溝槽加工中，有抗蝕層20不足之情形，但此時，如圖14所示，追加P－SiN膜37而形成SiN硬掩膜38，亦可以此為掩膜加工溝槽。
[實施例2]
圖15係顯示本發明之實施例2之半導體裝置之重要部分之剖面圖。
藉由場絕緣膜2將半導體基板1主面分離成各元件區域，在各元件區域形成源極區域、漏極區域等擴散層3，在源極區域、漏極區域3之間之半導體基板1主面上，經由閘極絕緣膜(未圖示)形成由多晶矽構成之閘極4，閘極4之側面則藉由側壁絕緣膜5而覆蓋。
在半導體基板1主面形成之擴散層3或閘極4，連接於貫通層間絕緣膜6之插栓7之一端，插栓7之另一端連接於經由層間絕緣膜6積層之單一鑲嵌配線10上。層間絕緣膜6依次堆積P－SiN膜(50 nm)、HDP－SiO膜(400 nm)、P－SiO膜(400 nm)後，藉由CMP技術研磨500 nm左右(大面積配線上之研磨量)，使藉由閘極4等產生之元件段差平坦化。
插栓7依次堆積藉由濺鍍之鈦膜(10 nm)、氮化鈦膜(50 nm)、藉由CVD之鎢膜後，藉由CMP進行加工。
單一鑲嵌配線10依次堆積藉由濺鍍之氮化鉭膜(15 nm)、鉭膜(15 nm)、銅膜(80 nm)、藉由電鍍法之銅膜(500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP而形成。
在單一鑲嵌配線10之相鄰間空隙細小部分，經由貫通具有空洞(Air－Gap)45之層間絕緣膜50之導孔46，單一鑲嵌配線49與單一鑲嵌配線10相連接。此時，在位於偏離單一鑲嵌配線10處之導孔46之下部，殘留有形成單一鑲嵌配線10時使用之絕緣膜之一部分之膜43。
在本實施例，因為導孔和空洞不接觸，所以能夠防止因導孔之金屬填入不良所致之高電阻化及因金屬向空洞之滲入所致之寄生電容增大之問題。
以下，關於本實施例2之半導體裝置之製造方法，以圖16至圖18為例，逐步驟加以説明。
在實施例1之圖3所示步驟之後，堆積有機絕緣膜之SiLK膜(第2絕緣膜)39(400 nm)、P－TEOS膜40(100 nm)後，形成凸形狀之抗蝕層41。抗蝕層41成柱狀，形成為覆蓋用於露出在後面步驟中形成之單一鑲嵌配線10之上面之連接孔之形成區域。該狀態如圖16所示。
然後，以抗蝕層41為掩膜蝕刻加工P－TEOS膜40，連續地，以抗蝕層41及P－TEOS膜40為掩膜蝕刻加工SiLK膜39，並形成由SiLK膜構成之犧牲膜柱42。在該階段，殘留有SiLK膜表面之P－TEOS膜40。
其次，各向異性地蝕刻加工單一鑲嵌配線10間之FSG膜9，去除未被犧牲膜柱覆蓋之區域之FSG膜9。此時，殘留位於犧牲膜柱42之下方之FSG膜9之一部分，形成有FSG膜43。
然後，形成無機絕緣膜之FSG膜(第3絕緣膜)(800 nm)。此時，為在單一鑲嵌配線10之相鄰間空隙細小部分形成空洞45，FSG膜採用CVD法以低覆蓋之成膜條件堆積。並且，用CVD法形成FSG膜，形成初期以低覆蓋之成膜條件進行，並形成空洞45，空洞45形成後，以高覆蓋之成膜條件進行，亦可將犧牲膜柱42埋入。另，FSG膜有必要堆積至其表面比犧牲膜柱42之上面高之膜厚。
然後，藉由CMP使FSG膜之表面平坦化之同時，使犧牲膜柱42之表面露出，形成由FSG膜構成之導孔形成用之層間絕緣膜44。該狀態如圖17所示。
然後，用NH3 電漿選擇性地去除犧牲膜柱42，從而使連接孔開孔到達單一鑲嵌配線10。
然後，將蝕刻聚合物去除洗淨後，用Ar電漿去除在連接孔之底部露出之單一鑲嵌配線10表面之自然氧化膜之後，依次堆積障壁金屬膜即藉由濺鍍之氮化鉭/鉭膜(15/15 nm)、主導體膜即濺鍍銅膜/藉由電鍍法之銅膜(第2導體膜)(80/500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，並藉由CMP去除連接孔以外之氮化鉭/鉭/銅膜，形成導孔46。該狀態如圖18所示。
然後，用形成單一鑲嵌配線10之相同方法，堆積SiCN/SiC膜47和無機絕緣膜之FSG膜48後，形成溝槽，並在該溝槽內形成單一鑲嵌配線49者為上述之圖15。
另，雖然未圖示，但是藉由重複以上步驟，亦可形成3層以上之多層鑲嵌配線。
在上述之實施形態，顯示了作為單一鑲嵌配線10、49及導孔46之主導體膜採用了Cu之例，但並非僅限於此，亦可以將Al、W、Ag、Au中至少任意一種金屬作為主導體膜使用。
在本實施例，藉由製作犧牲膜柱，可將在相鄰鑲嵌配線間形成之空洞從導孔分離而形成，故即使產生重疊偏差等，因為空洞和導孔不接觸，所以可穩定實施向具有空洞構造之下層之鑲嵌配線上之導孔連接。
另，在上述之實施例，形成鑲嵌配線10、49等後，作為金屬頂蓋膜，在鑲嵌配線表面選擇性地形成CoWB合金51、52，藉此，可提高鑲嵌配線10、49等之可靠性。另，作為金屬頂蓋膜，非僅限於上述CoWB合金，亦可使用Co、W、Ni、Cr、Au中之至少任意一種金屬或金屬化合物。該狀態如圖19所示。
並且，雖然未圖示，但是在導孔46表面亦可以形成CoWB合金。
此外，如圖14所示，亦可應用採用P－SiN膜之硬掩膜加工。
[實施例3]
圖20係顯示本發明之實施例3之半導體裝置之重要部分之剖面圖。
藉由場絕緣膜2將半導體基板1主面分離成各元件區域，在各元件區域形成源極區域、漏極區域等擴散層3，在源極區域、漏極區域3之間之半導體基板1主面上，經由閘極絕緣膜(未圖示)，形成由多晶矽構成之閘極4，閘極4之侧面藉由侧壁絕緣膜5覆盖。
在半導體基板1主面形成之擴散層3或閘極4，與貫通層間絕緣膜6之插栓7之一端連接，插栓7之另一端與經由層間絕緣膜6積層之單一鑲嵌配線10連接。層間絕緣膜6依次堆積P－SiN膜(50 nm)、HDP－SiO膜(400 nm)、P－SiO膜(400 nm)之後，藉由CMP技術研磨500 nm左右(大面積配線上之研磨量)，使藉由閘極4等產生之元件段差平坦化。
插栓7依次堆積藉由濺鍍之鈦膜(10 nm)、氮化鈦膜(50 nm)、藉由CVD之鎢膜之後，藉由CMP進行加工。
單一鑲嵌配線10依次堆積藉由濺鍍之氮化鉭膜(15 nm)、鉭膜(15 nm)、銅膜(80 nm)、藉由電鍍法之銅膜(500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，藉由CMP技術而形成。
在單一鑲嵌配線10之相鄰間空隙細小部分，經由貫通具有空洞(Air－Gap)55之層間絕緣膜54之導孔56，單一鑲嵌配線59與單一鑲嵌配線10連接。此時，在位於偏離單一鑲嵌配線10處之導孔56之下部，殘留有形成單一鑲嵌配線10時使用之絕緣膜9之一部分之膜43。
並且，層間絕緣膜54和單一鑲嵌配線10及導孔56之間存在絕緣膜53。
在本實施例，因為導孔和空洞不接觸，故可以防止因導孔之金屬埋入不良而引起之高電阻化或金屬向空洞之滲入而引起之寄生電容增大之問題。
以下，關於本實施例3之半導體裝置之製造方法，以圖21至23為例，逐步驟加以説明。
在實施例2之圖16所示步驟之後，以抗蝕層41為掩膜蝕刻加工P－TEOS膜40，以抗蝕層41及P－TEOS膜40為掩膜蝕刻加工SiLK膜39，形成由SiLK膜構成之犧牲膜柱60。在該階段，殘留有SiLK膜表面之P－TEOS膜40。
然後，各向異性地蝕刻加工單一鑲嵌配線10之間之FSG膜9，去除未被犧牲膜柱覆蓋之區域之FSG膜9。此時，殘留位於犧牲膜柱60之下方之FSG膜9之一部分，形成FSG膜43。
然後，堆積SiC膜61(10 nm)及多孔SiOC膜(第3絕緣膜)62(80 nm)。該狀態如圖21所示。此時，為使在單一鑲嵌配線10之鄰接間空隙細小部分形成空洞63，多孔SiOC膜62之形成初期以低覆蓋之成膜條件堆積。並且，多孔SiOC膜62有必要堆積至其表面比犧牲膜柱60之上面高之膜厚。
其次，藉由CMP使多孔SiOC膜62及SiC膜61之表面平坦化之同時，使犧牲膜柱60之表面露出。該狀態如圖22所示。犧牲膜柱60之表面之SiC膜61之去除，亦可用CMP加工，亦可採用選擇性的蝕刻加工。
其次，用NH3 電漿選擇性地去除犧牲膜柱60，藉此，使連接孔開孔到達單一鑲嵌配線10。
然後，洗淨蝕刻聚合物後，用Ar電漿去除在連接孔之底部露出之單一鑲嵌配線10表面之自然氧化膜後，依次堆積金屬頂蓋膜即藉由濺鍍之氮化鉭/鉭膜(15/15 nm)、主導體膜即濺鍍銅膜/藉由電鍍法之銅膜(第2導體膜)(80/500 nm)後，在氫氣環境下在400℃進行2分鐘之熱處理，並藉由CMP去除連接孔以外之氮化鉭/鉭/銅膜，形成導孔64。該狀態如圖23所示。
然後，以形成單一鑲嵌配線10之相同方法，堆積SiCN/SiC膜57、無機絕緣膜之FSG膜58後，形成溝槽，並在該溝槽內形成單一鑲嵌配線59者為上述之圖20。
另，雖然未圖示，但是藉由重複以上之步驟，亦可形成3層以上之多層鑲嵌配線。
在本實施例，由於藉由製作犧牲膜柱，可將形成於相鄰之鑲嵌配線間之空洞從導孔部分離並形成，故即使產生重疊偏差等，空洞和導孔也不會接觸，所以可穩定進行向具有空洞構造之下層鑲嵌配線上之導孔連接。
此外，因為導孔64係不直接與多孔SiOC膜62接觸之結構，故可防止因從多孔SiOC膜62除氣所導致之導孔毒化不良。
另，關於向鑲嵌配線表面之金屬頂蓋膜形成及硬掩膜加工等雖未揭示，但其當然可與實施例1及實施例2同樣適用。
以上，基於上述實施例就本發明者完成之發明具體加以説明，但本發明並非僅限於上述實施例，在不脫離其要旨之範圍內，當然可進行各種變更。
例如，閘極並不僅限於多晶矽，即使使用採用Ti及Co之矽化物之閘極，本發明亦可實施。
1．．．半導體基板
2．．．場絕緣膜
3．．．擴散層
4．．．閘極
5．．．側壁絕緣膜
6,18,26,29,44,48,50,54,58．．．層間絕緣膜
7．．．插栓
8,47,57．．．SiCN/SiC膜
9,15,16,43．．．FSG膜
10,49,59,65．．．單一鑲嵌配線
11,39．．．SiLK膜
12,40．．．P－TEOS膜
13,20,41．．．抗蝕層
14,42,60．．．犧牲膜柱
17,25,28,45,55,63,67．．．空洞
21,35．．．溝槽
22,36．．．連接孔
23,27,30．．．雙道鑲嵌配線
24．．．層間絕緣膜16之一部分膜
31．．．層間絕緣膜26之一部分膜
32,33,51,52．．．CoWB合金
34．．．犧牲膜柱之下部
37．．．P－SiN膜
38．．．SiN硬掩膜
46,56,64．．．導孔
53．．．絕緣膜
61．．．SiC膜
62．．．多孔SiOC膜
66．．．導孔部
圖1係顯示本發明之實施例1之半導體裝置之主要部分之縱剖面圖。
圖2係顯示具有先前之空洞構造之多層埋入配線之問題點之縱剖面圖。
圖3係逐步驟顯示本發明之實施例1之半導體裝置之配線層形成之縱剖面圖。
圖4係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖5係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖6係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖7係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖8係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖9係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖10係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖11係逐步驟顯示本發明實施例1之半導體裝置之配線層形成之縱剖面圖。
圖12(a)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖12(b)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖13(a)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖13(b)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖13(c)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖14(a)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖14(b)係顯示本發明之實施例1之半導體裝置之重要部分之縱剖面圖。
圖15係顯示本發明之實施例2之半導體裝置之重要部分之縱剖面圖。
圖16係逐步驟顯示本發明之實施例2之半導體裝置之配線層形成之縱剖面圖。
圖17係逐步驟顯示本發明之實施例2之半導體裝置之配線層形成之縱剖面圖。
圖18係逐步驟顯示本發明之實施例2之半導體裝置之配線層形成之縱剖面圖。
圖19係顯示本發明之實施例2之半導體裝置之重要部分之縱剖面圖。
圖20係顯示本發明之實施例3之半導體裝置之重要部分之縱剖面圖。
圖21係逐步驟顯示本發明之實施例3之半導體裝置之配線層形成之縱剖面圖。
圖22係逐步驟顯示本發明之實施例3之半導體裝置之配線層形成之縱剖面圖。
圖23係逐步驟顯示本發明之實施例3之半導體裝置之配線層形成之縱剖面圖。
42．．．犧牲膜柱
43．．．FSG膜
44．．．層間絕緣膜
45．．．空洞

Claims (20)

  1. 一種半導體積體電路裝置之製造方法，其特徵為具有如下之步驟：(a)在半導體基板上方形成第1絕緣膜之步驟；(b)在上述第1絕緣膜上形成複數之配線溝槽之步驟；(c)在包含上述複數之配線溝槽各自之內部之上述第1絕緣膜上，形成第1導體膜之步驟；(d)藉由去除上述複數之配線溝槽外部之上述第1導體膜，在上述複數之配線溝槽各自之內部形成由上述第1導體膜構成之配線之步驟；(e)在上述第1絕緣膜及上述配線上，形成由與上述第1絕緣膜不同之材料構成之第2絕緣膜之步驟；(f)採用覆蓋在後面步驟中形成之露出上述配線上面之連接孔的形成區域之掩膜而蝕刻上述第2絕緣膜，藉此，在上述連接孔之形成區域形成由上述第2絕緣膜構成之犧牲膜柱之步驟；(g)選擇性地去除未以上述犧牲膜柱覆蓋之區域之上述第1絕緣膜，並在上述犧牲膜柱之下部殘留上述第1絕緣膜之步驟；(h)在去除上述第1絕緣膜之上述配線間之空隙區域保留空洞之下，在上述配線及上述犧牲膜柱上，形成由與上述第2絕緣膜不同之材料構成之第3絕緣膜之步驟；(i)去除上述犧牲膜柱上之上述第3絕緣膜，露出上述犧牲膜柱之上面之步驟；(j)去除上述犧牲膜柱，並形成露出上述配線之上面之連接孔之步驟；(k)在上述連接孔之內部形成第2導體膜之步驟。
  2. 如請求項1之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係由相同材料構成。
  3. 如請求項2之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係無機絕緣膜，上述第2絕緣膜係有機絕緣膜。
  4. 如請求項3之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係FSG膜，上述第2絕緣膜係SiLK膜。
  5. 如請求項1之半導體積體電路裝置之製造方法，其中上述第3絕緣膜係多孔SiOC膜，在上述(g)步驟與上述(h)步驟之間，還包含在上述配線及上述犧牲膜柱上形成SIC膜之步驟。
  6. 如請求項5之半導體積體電路裝置之製造方法，其中上述第1絕緣膜係FSG膜，上述第2絕緣膜係SiLK膜。
  7. 如請求項1之半導體積體電路裝置之製造方法，其中上述第1導體膜由Al、Cu、W、Ag、Au內之至少任意一種金屬構成。
  8. 如請求項1之半導體積體電路裝置之製造方法，其中上述第2導體膜由Al、Cu、W、Ag、Au內之至少任意一種金屬構成。
  9. 如請求項1之半導體積體電路裝置之製造方法，其中在上述(d)步驟與(e)步驟之間，還包含在上述配線上形成金屬頂蓋膜之步驟，上述金屬頂蓋膜由Co、W、Ni、Cr、Au內之至少任意一種金屬或金屬化合物構成。
  10. 如請求項1之半導體積體電路裝置之製造方法，其中上述(h)步驟之上述第3絕緣膜之形成，在形成初期以低覆蓋之成膜條件進行，並在形成上述空洞後，以高覆蓋之成膜條件進行。
  11. 一種半導體積體電路裝置之製造方法，其特徵為具有如下之步驟：(a)在半導體基板上方形成第1絕緣膜之步驟；(b)藉由去除上述第1絕緣膜之一部分，形成在後面步驟中形成之第1鑲嵌配線用之複數之第1配線溝槽之步驟；(c)在包含上述複數之第1配線溝槽之各個內部之上述第1絕緣膜上，形成第1導體膜之步驟；(d)藉由去除上述複數之第1配線溝槽之外部之上述第1導體膜，在上述複數之第1配線溝槽之各個內部形成由上述第1導體膜構成之上述第1鑲嵌配線之步驟；(e)在上述第1絕緣膜及上述第1鑲嵌配線上，形成由與上述第1絕緣膜不同之材料構成之第2絕緣膜之步驟；(f)用覆蓋在後面步驟中形成之第2鑲嵌配線之導孔部用複數連接孔的形成區域之掩膜，蝕刻上述第2絕緣膜，藉此，在上述複數之連接孔形成區域形成由上述第2絕緣膜構成之複數之犧牲膜柱之步驟；(g)選擇性地去除未以上述犧牲膜柱覆蓋之區域之上述第1絕緣膜，並在上述犧牲膜柱之下部殘留上述第1絕緣膜之步驟；(h)在去除上述第1絕緣膜之上述配線間之空隙區域保留空洞，並在上述配線及上述犧牲膜柱上，形成由與上述第2絕緣膜不同材料構成之第3絕緣膜之步驟；(i)去除上述犧牲膜柱上之上述第3絕緣膜，露出上述複數之犧牲膜柱上面之步驟；(j)藉由去除上述第3絕緣膜之一部分及上述複數之犧牲膜柱之上部，形成在後面步驟中形成之上述第2鑲嵌配線之配線部用之複數之第2配線溝槽之步驟；(k)藉由去除上述複數之犧牲膜柱之下部，形成上述複數之連接孔之步驟；(l)在包含上述複數之第2配線溝槽及上述複數之連接孔各自之內部之上述第3絕緣膜上形成第2導體膜之步驟；(m)藉由去除上述複數之第2配線溝槽及上述複數之連接孔之外部之上述第2導體膜，在上述複數之第2配線溝槽及上述複數之連接孔各自之內部，形成由上述第2導體膜構成之上述第2鑲嵌配線之步驟。
  12. 如請求項11之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係由相同材料構成。
  13. 如請求項12之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係無機絕緣膜，上述第2絕緣膜係有機絕緣膜。
  14. 如請求項13之半導體積體電路裝置之製造方法，其中上述第1絕緣膜和上述第3絕緣膜係FSG膜，上述第2絕緣膜係SiLK膜。
  15. 如請求項11之半導體積體電路裝置之製造方法，其中上述第1導體膜及上述第2導體膜係由Al、Cu、W、Ag、Au中之至少任意一種金屬構成。
  16. 如請求項11之半導體積體電路裝置之製造方法，其中在上述(d)步驟與(e)步驟之間及(m)步驟之後，還包含在上述第1鑲嵌配線及上述第2鑲嵌配線上形成金屬頂蓋膜之步驟，上述金屬頂蓋膜係由Co、W、Ni、Cr、Au中之至少任意一種金屬或金屬化合物構成。
  17. 如請求項11之半導體積體電路裝置之製造方法，其中上述(h)步驟之上述第3絕緣膜之形成，在形成初期以低覆蓋之成膜條件實施，在形成上述空洞後以高覆蓋之成膜條件實施。
  18. 如請求項11之半導體積體電路裝置之製造方法，其中上述(i)步驟之上述複數之第2配線溝槽之形成，在去除上述複數之犧牲膜柱之上部後，去除上述第3絕緣膜之一部分。
  19. 如請求項11之半導體積體電路裝置之製造方法，其中上述(i)步驟之上述複數之第2配線溝槽之形成，係採用由第4絕緣膜構成之硬掩膜進行。
  20. 如請求項19之半導體積體電路裝置之製造方法，其中上述第4絕緣膜係SiN膜。
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