JP2007141985A - 半導体集積回路装置の製造方法 - Google Patents
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Abstract
【解決手段】接続孔の形成領域に、選択的に除去可能な絶縁膜で犠牲膜ピラー42を形成した後に、隣接するダマシン配線間に空洞(Air−Gap)45を有する層間絶縁膜44を形成することで、ビアと空洞45を完全に分離する。
【効果】本発明によれば、信頼性の高いビア接続を有し、空洞による寄生容量の低減がなされた多層の埋込配線を形成することができる。
【選択図】図17
Description
(a)半導体基板の上方に第1の絶縁膜を形成する工程、
(b)前記第1の絶縁膜に複数の配線溝を形成する工程、
(c)前記複数の配線溝のそれぞれの内部を含む前記第1の絶縁膜上に第1の導体膜を形成する工程、
(d)前記複数の配線溝の外部の前記第1の導体膜を除去することによって、前記複数の配線溝のそれぞれの内部に前記第1の導体膜からなる配線を形成する工程、
(e)前記第1の絶縁膜及び前記配線上に、前記第1の絶縁膜と異なる材料からなる第2の絶縁膜を形成する工程、
(f)後の工程で形成される前記配線の上面を露出する接続孔の形成領域を覆うマスクを用いて前記第2の絶縁膜をエッチングすることにより、前記接続孔の形成領域に前記第2の絶縁膜からなる犠牲膜ピラーを形成する工程、
(g)前記犠牲膜ピラーで覆われていない領域の前記第1の絶縁膜を選択的に除去し、前記犠牲膜ピラーの下部に前記第1の絶縁膜を残す工程、
(h)前記第1の絶縁膜が除去された前記配線間のスペース領域に空洞を残しつつ、前記配線及び前記犠牲膜ピラー上に、前記第2の絶縁膜と異なる材料からなる第3の絶縁膜を形成する工程、
(i)前記犠牲膜ピラー上の前記第3の絶縁膜を除去し、前記犠牲膜ピラーの上面を露出する工程、
(j)前記犠牲膜ピラーを除去し、前記配線の上面を露出する接続孔を形成する工程、
(k)前記接続孔の内部に第2の導体膜を形成する工程。
(a)半導体基板の上方に第1の絶縁膜を形成する工程、
(b)前記第1の絶縁膜の一部を除去することによって、後の工程で形成される第1のダマシン配線用の複数の第1の配線溝を形成する工程、
(c)前記複数の第1の配線溝のそれぞれの内部を含む前記第1の絶縁膜上に第1の導体膜を形成する工程、
(d)前記複数の第1の配線溝の外部の前記第1の導体膜を除去することによって、前記複数の第1の配線溝のそれぞれの内部に前記第1の導体膜からなる前記第1のダマシン配線を形成する工程、
(e)前記第1の絶縁膜及び前記第1のダマシン配線上に、前記第1の絶縁膜と異なる材料からなる第2の絶縁膜を形成する工程、
(f)後の工程で形成される第2のダマシン配線のビア部用の複数の接続孔の形成領域を覆うマスクを用いて前記第2の絶縁膜をエッチングすることにより、前記複数の接続孔の形成領域に前記第2の絶縁膜からなる複数の犠牲膜ピラーを形成する工程、
(g)前記犠牲膜ピラーで覆われていない領域の前記第1の絶縁膜を選択的に除去し、前記犠牲膜ピラーの下部に前記第1の絶縁膜を残す工程、
(h)前記第1の絶縁膜が除去された前記配線間のスペース領域に空洞を残しつつ、前記配線及び前記犠牲膜ピラー上に、前記第2の絶縁膜と異なる材料からなる第3の絶縁膜を形成する工程、
(i)前記犠牲膜ピラー上の前記第3の絶縁膜を除去し、前記複数の犠牲膜ピラーの上面を露出する工程、
(j)前記第3の絶縁膜の一部及び前記複数の犠牲膜ピラーの上部を除去することによって、後の工程で形成される前記第2のダマシン配線の配線部用の複数の第2の配線溝を形成する工程、
(k)前記複数の犠牲膜ピラーの下部を除去を除去することによって、前記複数の接続孔を形成する工程、
(l)前記複数の第2の配線溝及び前記複数の接続孔のそれぞれの内部を含む前記第3の絶縁膜上に第2の導体膜を形成する工程、
(m)前記複数の第2の配線溝及び前記複数の接続孔の外部の前記第2の導体膜を除去することによって、前記複数の第1の配線溝及び前記複数の接続孔のそれぞれの内部に前記第2の導体膜からなる前記第2のダマシン配線を形成する工程。
Claims (20)
- 以下の工程を有することを特徴とする半導体集積回路装置の製造方法:
(a)半導体基板の上方に第1の絶縁膜を形成する工程、
(b)前記第1の絶縁膜に複数の配線溝を形成する工程、
(c)前記複数の配線溝のそれぞれの内部を含む前記第1の絶縁膜上に第1の導体膜を形成する工程、
(d)前記複数の配線溝の外部の前記第1の導体膜を除去することによって、前記複数の配線溝のそれぞれの内部に前記第1の導体膜からなる配線を形成する工程、
(e)前記第1の絶縁膜及び前記配線上に、前記第1の絶縁膜と異なる材料からなる第2の絶縁膜を形成する工程、
(f)後の工程で形成される前記配線の上面を露出する接続孔の形成領域を覆うマスクを用いて前記第2の絶縁膜をエッチングすることにより、前記接続孔の形成領域に前記第2の絶縁膜からなる犠牲膜ピラーを形成する工程、
(g)前記犠牲膜ピラーで覆われていない領域の前記第1の絶縁膜を選択的に除去し、前記犠牲膜ピラーの下部に前記第1の絶縁膜を残す工程、
(h)前記第1の絶縁膜が除去された前記配線間のスペース領域に空洞を残しつつ、前記配線及び前記犠牲膜ピラー上に、前記第2の絶縁膜と異なる材料からなる第3の絶縁膜を形成する工程、
(i)前記犠牲膜ピラー上の前記第3の絶縁膜を除去し、前記犠牲膜ピラーの上面を露出する工程、
(j)前記犠牲膜ピラーを除去し、前記配線の上面を露出する接続孔を形成する工程、
(k)前記接続孔の内部に第2の導体膜を形成する工程。 - 請求項1に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜が同じ材料からなることを特長とする半導体集積回路装置の製造方法。
- 請求項2に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜が無機系絶縁膜であり、前記第2の絶縁膜が有機系絶縁膜であることを特長とする半導体集積回路装置の製造方法。
- 請求項3に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜がFSG膜であり、前記第2の絶縁膜がSiLK膜であることを特長とする半導体集積回路装置の製造方法。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記第3の絶縁膜がポーラスSiOC膜であり、前記(g)工程と前記(h)工程の間に、前記配線及び前記犠牲膜ピラー上にSIC膜を形成する工程を更に有することを特長とする半導体集積回路装置の製造方法。
- 請求項5に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜がFSG膜であり、前記第2の絶縁膜がSiLK膜であることを特長とする半導体集積回路装置の製造方法。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記第1の導体膜がAl,Cu,W,Ag,Auの内の少なくともいづれか一つの金属からなることを特長とする半導体集積回路装置の製造方法。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記第2の導体膜がAl,Cu,W,Ag,Auの内の少なくともいづれか一つの金属からなることを特長とする半導体集積回路装置の製造方法。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記(d)工程と前記(e)工程の間に、前記配線上にメタルキャップ膜を形成する工程を更に有し、前記メタルキャップ膜がCo,W,Ni,Cr,Auの内の少なくともいづれか一つの金属または金属化合物からなることを特長とする半導体集積回路装置の製造方法。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記(h)工程の前記第3の絶縁膜の形成を、形成初期はカバレジの低い成膜条件で行い、前記空洞が形成された後はカバレジの高い成膜条件で行うことを特長とする半導体集積回路装置の製造方法。
- 以下の工程を有することを特徴とずる半導体集積回路装置の製造方法:
(a)半導体基板の上方に第1の絶縁膜を形成する工程、
(b)前記第1の絶縁膜の一部を除去することによって、後の工程で形成される第1のダマシン配線用の複数の第1の配線溝を形成する工程、
(c)前記複数の第1の配線溝のそれぞれの内部を含む前記第1の絶縁膜上に第1の導体膜を形成する工程、
(d)前記複数の第1の配線溝の外部の前記第1の導体膜を除去することによって、前記複数の第1の配線溝のそれぞれの内部に前記第1の導体膜からなる前記第1のダマシン配線を形成する工程、
(e)前記第1の絶縁膜及び前記第1のダマシン配線上に、前記第1の絶縁膜と異なる材料からなる第2の絶縁膜を形成する工程、
(f)後の工程で形成される第2のダマシン配線のビア部用の複数の接続孔の形成領域を覆うマスクを用いて前記第2の絶縁膜をエッチングすることにより、前記複数の接続孔の形成領域に前記第2の絶縁膜からなる複数の犠牲膜ピラーを形成する工程、
(g)前記犠牲膜ピラーで覆われていない領域の前記第1の絶縁膜を選択的に除去し、前記犠牲膜ピラーの下部に前記第1の絶縁膜を残す工程、
(h)前記第1の絶縁膜が除去された前記配線間のスペース領域に空洞を残しつつ、前記配線及び前記犠牲膜ピラー上に、前記第2の絶縁膜と異なる材料からなる第3の絶縁膜を形成する工程、
(i)前記犠牲膜ピラー上の前記第3の絶縁膜を除去し、前記複数の犠牲膜ピラーの上面を露出する工程、
(j)前記第3の絶縁膜の一部及び前記複数の犠牲膜ピラーの上部を除去することによって、後の工程で形成される前記第2のダマシン配線の配線部用の複数の第2の配線溝を形成する工程、
(k)前記複数の犠牲膜ピラーの下部を除去することによって、前記複数の接続孔を形成する工程、
(l)前記複数の第2の配線溝及び前記複数の接続孔のそれぞれの内部を含む前記第3の絶縁膜上に第2の導体膜を形成する工程、
(m)前記複数の第2の配線溝及び前記複数の接続孔の外部の前記第2の導体膜を除去することによって、前記複数の第2の配線溝及び前記複数の接続孔のそれぞれの内部に前記第2の導体膜からなる前記第2のダマシン配線を形成する工程。 - 請求項11に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜が同じ材料からなることを特長とする半導体集積回路装置の製造方法。
- 請求項12に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜が無機系絶縁膜であり、前記第2の絶縁膜が有機系絶縁膜であることを特長とする半導体集積回路装置の製造方法。
- 請求項13に記載の半導体集積回路装置の製造方法において、前記第1の絶縁膜と前記第3の絶縁膜がFSG膜であり、前記第2の絶縁膜がSiLK膜であることを特長とする半導体集積回路装置の製造方法。
- 請求項11に記載の半導体集積回路装置の製造方法において、前記第1の導体膜及び前記第2の導体膜がAl,Cu,W,Ag,Auの内の少なくともいづれか一つの金属からなることを特長とする半導体集積回路装置の製造方法。
- 請求項11に記載の半導体集積回路装置の製造方法において、前記(d)工程と前記(e)工程の間及び前記(m)工程の後に、前記第1のダマシン配線及び前記第2のダマシン配線上にメタルキャップ膜を形成する工程を更に有し、前記メタルキャップ膜がCo,W,Ni,Cr,Auの内の少なくともいづれか一つの金属または金属化合物からなることを特長とする半導体集積回路装置の製造方法。
- 請求項11に記載の半導体集積回路装置の製造方法において、前記(h)工程の前記第3の絶縁膜の形成を、形成初期はカバレジの低い成膜条件で行い、前記空洞が形成された後はカバレジの高い成膜条件で行うことを特長とする半導体集積回路装置の製造方法。
- 請求項11に記載の半導体集積回路装置の製造方法において、前記(i)工程の前記複数の第2の配線溝の形成は、前記複数の犠牲膜ピラーの上部を除去した後に前記第3の絶縁膜の一部を除去することを特徴とする半導体集積回路装置の製造方法。
- 請求項11に記載の半導体集積回路装置の製造方法において、前記(i)工程の前記複数の第2の配線溝の形成を、第4の絶縁膜からなるハードマスクを用いて行うことを特徴とする半導体集積回路装置の製造方法。
- 請求項19に記載の半導体集積回路装置の製造方法において、前記第4の絶縁膜がSiN膜であることを特徴とする半導体集積回路装置の製造方法。
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Also Published As
Publication number | Publication date |
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CN1967800A (zh) | 2007-05-23 |
TWI387049B (zh) | 2013-02-21 |
TW200805563A (en) | 2008-01-16 |
US7553756B2 (en) | 2009-06-30 |
JP4918778B2 (ja) | 2012-04-18 |
US20070111508A1 (en) | 2007-05-17 |
CN100477160C (zh) | 2009-04-08 |
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