TWI245403B - A kind of semiconductor component formed by diffusion soldering method - Google Patents
A kind of semiconductor component formed by diffusion soldering method Download PDFInfo
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- TWI245403B TWI245403B TW092105407A TW92105407A TWI245403B TW I245403 B TWI245403 B TW I245403B TW 092105407 A TW092105407 A TW 092105407A TW 92105407 A TW92105407 A TW 92105407A TW I245403 B TWI245403 B TW I245403B
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Description
1245403
月 曰 修正 ^月係有關於_種組件,且更明確 件,其具有配置於一第_曰κ卜的隻θ u禋牛等體、,且 第-盘第-日#且右 第日片’及其中該等 一弟一日日片具有一互相電氣連接。 電路片之ΐ相叠積配置及其電氣互連亦稱作「垂直 ?體整口」:在該第一晶片與第二晶片之間製作電氣連 ,一種I能,係利用打線接合。在這種連接方法中,該電 較另一者大的基礎面積。各該等晶片之 二J係位於其活性主要側上,舉例而言,在較大晶片中, 法接合於未具有接合塾的域:雷因而較小晶片無 各接合塾之間打線接合Ξΐ:域中。該電氣連接係藉由在 連接另在::;ί ΐ:JJ ”著劑或焊球來製作該電氣 相面對,使得各接觸“第—f第二晶片活性主要區係互 黏著劑或焊球來製作點接觸相::地設置。接著可藉由導電 而可對該電氣接觸造成損㊁β .、、、應力產生之剪力’將因此 1 00微在半上夕述„變型中’ 5亥等接合墊接觸區之直徑係介於,至 目ΓΛΛ。該兩接合塾或外部接觸區之間的距離係具有 不目冋於上述者之數量級。 必須對於該等第一與第二晶片之疊積配置、及各接合塾 =卜部接觸區作大幅地設計變更,才可使藉由打線接合、導 =黏著劑、或焊球達成之一電氣連接,提供額外的電氣功 用於在該等第一與第二晶片之間製作一電氣連接的另一
im 第6頁 1245403 五、發明說明 連接方法 與第二晶 於各別之 兩鍍金屬 施為,分 一電氣連 一厚度的 間。包括 焊料層的 及之連接 其微小厚 •是以 較簡單之 可藉 達成本發 出〇 ^^ 92105407 (2) 係所謂的「擴 片係配置成, 活性主要區上 層係互相面對 別具有1至5微 接,譬如由錫 一額外薄焊料 有該第一及第 總厚度,係少 方法,此處者 度而圖案化至 ,本發明之目 方式來實現額 由具有如申請 明。較佳之修 曰 i多正 散焊接方法」。在後者中,該等第_ 使該兩者之活性主要區互相相關。設 者係一第一與第二鍍金屬層,其中= 著。該第一及第二鍍金屬層可&體g 米之一厚度的一銅層型式。為了製作 製成、且具有介於0 · 5至3微米之間之 層將引入該等第一與第二鍍金屬層之 二鍍金屬層、以及位於該兩者之間之 於1 〇微米。是以,相較於引言中所提 可製作一額外的薄金屬平面,且可因 1微米範圍内。 的係具體說明一種組件,其可藉由_ 外的電氣功能。 專利範圍第1項所述特徵之一組件來 飾將自附屬項申請專利範圍中顯露 本發明係提出一種組件,特別係一種半導體組件,其具 有配置於一第二晶片上之一第一晶片,其中該等第一與第二 晶片皆在其主要區上各具有第一與第二鍍金屬層,該等第一 與第二鍍金屬層係互相面對著。該等第一及第二鍍金屬層之 第一區域係用於在該等第一與第二晶片之間製作一電氣連 接。該第一及/或第二鍍金屬層之第二區域則係作為該等第 一與第二晶片外侧之一額外的電氣功能平面。 可由「该等第一與第二晶片外側之額外的電氣功能平 面」之敘述中了解到,該電氣功能平面並非形成於該第一或
第7頁 1245403 9210R407 年 月 曰 修正 五 、發明說明(3) ' ^ 外 氣 第二晶片之基板中,而係位於其外側。在這種情況下,該額 的電亂功月b平面主要地並非用於該等第一與第二晶片之電 連接’而係構成與該第一及第二晶片獨立無關的一結構。 譬如’可包括具有線圈及延遲線路的一被動結構。 是以’該組件係利用引言中之擴散焊接方法,以在該等 與第二晶片之間製作一電氣連接。更,除了僅製作^氣 及機械連接以外,可採用目前之金屬層來實施進一步之電^ 功能。如此將允許以特別低廉之價格來實現該組件之 ^ 構,且具有高功能性。明確地,依據本發明之組件將由; 等第一及第:晶片之各別基礎面積皆可因連接技術而保持; 組件可能節省-個或更多額外的結線平面,且又在該 及第二晶片中提供-電路遮蔽。 由於一擴散焊接方法期間所使用之金屬層,可因其微小厚产 而經圖案化減小至i微米之範圍内,因 /、=厚度 平面將可能實現。在這稽柃1 2 冤軋功月b 限於微影術之選擇、將越 ::::僅又 的對正精確度、以及焊料::::-曰曰片叠積配置之工具 微另彳ft & μ挤μ丨i ^枓擠出情況。可使用一慣用之鄰近 觸微影術,甚至可使結樽5=、:構9二相同地經常使用之接 較長之對正時間來互相微米。冑若可接受以-在此亦可達成!微米的“積产地疋:/乂第一與第二晶片’則 圍内之焊料擠出情況,二度葬由原二上無法避免1至2微来範 免。譬如,塗佈有-烊;更進-步之措施而得避 _ , 了叶之第一及第二鍍金屬居$大於塗你 至其上的焊料1至5微米。枪與4 ^ 4緞隹屬層J穴趴丈师
___ 儘e攻可抵銷焊料擠出之情況,但 1245403
將 造成一較低程度的圖案化細緻程度。 地 屬 要 比 連^ ΐ彳i 或第二鍍金屬層係經由接觸材料元件而方便 連接位於一最上方鍍金屬層中之接觸方鲈今 層係位於一久則曰Η夕A k ^ 觸墊亥最方鍍金 ψΌ ^ ^ 別s曰片之基板内。其係代表最接近該活性主 二接觸% 2面,該活性主要區則代表一晶片之主要側。對 '^ 白位於最上方鍍金屬層中、亦即皆位在該晶片 Μ it#且可譬如藉由打線接合或焊球而直接地接觸連接 H置,該第一及/或第二鍍金屬層係直揍設於該第一 及/或笫一晶片之各主要區上。
1 =於習知配置,互相電氣連接之該等接觸墊無需直接 相對t汉置。結果,該第一及第二晶片外側之該額外的電氣 功能平面將提供一額外的金屬層作為一更一結線平面。 較佳地,該第一或第二晶片在相對其設置之晶片上、具 有鍍金,層第二區域的位置處,並無任何鍍金屬層,使得該 等第一區域可執行該相對設置晶片作動時所需之一電氣功 能。因此’該更一結線平面係直接地設於該等第一與第二晶 片之間。為了避免短路,可在該等互相相對設置之晶片的其 中〆主要區上保留一相對應「窗口」。
在本發明之更一修飾中,該第一晶片可具有不同大小, 在适種情况下,其允許小於、等同於、或大於該第二晶片。 該第一晶片在形成於該最小第一晶片與該第二晶片主要區之 間之一重叠區域的至少外側處,具有該第二鍍金屬層第二區 威。位於該重疊區域外側之第二鍍金屬層第二區域較優地可 用作為一編碼。 當一較大之第一晶片配置於該第二晶片上時,該等第二
第9頁 1245403 修正 五、發明說明(5) ^ 二第二區域最好藉該第一晶片之第一鍍金屬層而接觸 ' 此,該等第二鍍金屬層第二區域較佳地包括兩金屬 二和A ^ f者在初始時並未互相電氣連接。倘若該兩金屬區 j二徂^等第一與第二晶片之間的重疊區域外側,則該連接 ^、開路。然而,使一較大之第一晶片設置於該第二晶 、配置將可造成該兩金屬區連接,因此該第二晶片將可 獲取關於該第一晶片大小或型式的資訊。 y 在另—修飾中,當該第一晶片已配置於該第二晶片上之
^ ’該等第二鍍金屬層第二區域亦可藉由使導體軌道或金屬 ,中斷或著連接而達成一編碼,且該導體執道或金屬區係該 專第一區域之一部份。因此,該等第二區域必須位於該等第 一與第二晶片之間之重疊區域的外側。可藉由接績著塗佈譬 如一焊料或導電黏著劑等導電材料,而使該等第二區域中之 導體執道的電氣連接達成接觸連接。可藉由譬如一雷射來打 斷兩導體軌道之電氣連接。
較佳地,該第一及/或第二鍍金屬層之第二區域包括設 於該等第一與第二晶片之重疊區域内的複數個測試墊。只要 該等第一與第二晶片尚未互相連接,即可藉由不受阻檔之方 式來處理該等測試墊。對比地,當該等第一與第二晶片已互 相結合之後,由於該等測試墊將因此而位於該等第一與第二 曰曰片之重疊區域内,以致於不可能再觸及到。較佳地,當該 第一晶片已配置於該第二晶片上之後,該第一或第二晶片上 之測試塾將與相對設置之晶片上的鍍金屬層第二區域機械接 觸。依據製作一電氣連接之程序,該等測試墊係藉一焊料層 而連接至該相對設置晶片上的一鍍金屬層。該相對設置晶片
第10頁 -^^^92105407 1245403 土月 曰 羞正 五、發明說明(6) 上之鍍金屬層在這種情況下較佳地具有—電 將在該等第-與第二晶片 < 間允,—穩 二程序 需使用譬如-黏著劑等—更進—步之連接裝J械連接,而無 ,,二正好互相相對設置之該等第—與第二鐘金 第—區域亦用於機械式地固定該等第一與第二曰X f之 倘若可能’則該等第二區域應在該等第;曰_曰\:二 重疊區域中以平面方式具體實施。 第一曰曰片之間的 較佳地互相相對地設置且用於機械式固定的兮犛楚 環繞著該等第一與第二鍵金屬層 rdi二、、I果,設置於該環内部之該等鑛金屬層第一區域 係元全谘封地密封住且可免於濕氣之腐蝕。可 浸潰而將該,件鍍金,卩更進-步改良表面之抗腐蝕性。9 第1圖係以剖面來顯示一組件,其中尚未藉一擴散焊 方法來連接一第—晶片10與一第二晶Μ 2〇。第一晶片10與第 二晶片20分別在其活性主要區13與23上具有譬如一接觸墊i ^ 與2卜該等接觸墊皆設於晶片1〇、2〇之最上方金屬層中。 第一 ^ Η在其活性主要區13上具有―第—贫又金屬層 丄2:鍍^屬層12係分割成互相電氣隔離之複數個區域 式:’其中-該等區域係經由標示為鑛通孔14之一接 凡件而電氣連接至接觸墊U。擴散焊接方法之一重要特^ 於,連接至接觸墊11之第一鑛金屬層1 ^ ^ g . 較大之面積。 續12的一區域具有一明顯 =應地’―第二锻金屬層係形成於第二晶片2〇之活性 =要£ 23上。該第二鍍金屬層係相同地再細分成互相電氣隔 離之複數個區域。在圖式中,其中—該等區域係經由一錢通 1245403 __ 案號 92105407___年月曰 五、發明說明(7) 孔2 4而連接至接觸墊2卜 以下將連接至接合墊11、2 1且意欲在稍後互相電氣連接 的第一及第二鍍金屬層12、22之區域,稱作為各鍍金屬層之 第一區域。 第一及第二鍍金屬層12、22通常係由銅構成,且皆具有 近似於1至5微米之一厚度。由譬如錫構成、且具有介於〇. 5 至3微米之間之一厚度的一更一金屬層3〇,係一 鍍金屬層12或22。 、 通常,形成於第一及第二鍍金屬層12、22中之區域具有 相同配置,使得可在將第一晶片i 〇對正至第二晶片2〇上之期 間互相配合。如此將造成一大面積連接平面,使得第一與第 二晶片1 0、2 0可互相穩定地連接。 然而,在習知技藝已知的配置中,該等鍍金屬層僅用於 •作電氣及/或機械連接,而本發明係提供鍍金屬層之區 ^ ’作為設於該第-及第二晶片外侧之—額外的電氣功能平 =2A圖係以一平面圖來顯示一第一說明用具體實施例。 - 1 ί ί不出亦稱為底侧晶片之第二晶片20的細部設計。第 22具有一第一區域22&,其係用於在底側晶片 現& t 1二ί片或頂侧晶片1〇之間製作一電氣連接,這係顯 導譬如’第一區域呈環狀配置。設計成 域99 k型式之第二區域22b係設於第二鍍金屬層22第一區 片1 之b /刀口 2 5中。可由第2B圖中較清楚地看出,頂側晶 底#丨曰y ^域中並無鍍金屬層。是以,第二區域2 21)係代表 •側曰曰片20活性主要區23中之一額外的結線平面。緣是第
第12頁 1245403 五、發明說明 案號 92105407 (8) 年 月 曰 修正 二區域22 b將經由艘通孔2 4而連接至接觸墊21。 只有在鍍金屬層將因其微小之厚度而圖案化達1微米範 圍内時,才得利用該鍍金屬層作為一更一結線平面。在這種 配置中,為了避免短路,可方便地在相對之晶片側金屬層中 保留一相對應窗口。該窗口較有利地係具有第二鍍金屬層 22a中切口 25者之尺寸。 亦可由第2 B圖中清楚看出,接觸墊1卜2 1係互相相關地 錯置。由於經由鍍金屬層12、2 2達成之電氣連接可容許任何 位置之接觸墊11、2 1,因此無需一相對設置之配置。 第3 A圖及第3 B圖係顯示又一說明用具體實施例,其中一 鍍金屬層之第二區域係用於編碼。第3A圖係顯示依據本發明 之組件的平面圖。可將一頂側晶片1 〇 (實線)或另一選擇為將 一稍微較大頂側晶片1 0 ’(其較晶片1 〇大者係藉虛線表示之區
域)施加於底側晶片2 0上。鍍金屬層2 2之第二區域係以兩金 屬區型式實施。當以較小之頂側晶片1 〇施加於底侧晶片2 〇上 時’鏡金屬層22之該金屬區或第二區域係設於一重疊區域外 側。對比地,倘若係提供較大頂側晶片丨〇,來連接底侧晶片 2 〇時,則第二區域2 2將設於該兩晶片之重疊區域内。因此, 頂側晶片1 0 ’較佳地可在鍍金屬層1 2中具有一區域1 2,,使得 該區域在第二鍍金屬層22之兩金屬區之間產生一電氣連接。 如此,底側晶片2 0將能夠識別出,其中係包含一頂側晶片i 〇 抑或一頂側晶片1 0,。 本申請案特別著眼於,當底側晶片2 0與頂側晶片j 〇、 10具有不同型式之情況。是以,該兩晶片其中之_可為蓉 如處理器晶片,而另一個則構成一記憶體。因此,該組件^
第13頁 1245403 _案號92105407___年 L 曰__^正 五、發明說明(9) 製作將可排除在晶圓製程以外。這種程序將可排除昂貴的嵌 入製程。特別地,可能譬如製造具有不同大小之記憶體的一 處理器,而無需僅為此來改變一單一微影光罩。 具體實施為一處理器晶片的一底側晶片20,僅需藉由「探 測」該頂側晶片之面積大小,即可辨識出究竟係連接至哪一 記憶體晶片10、10’。為此’該第二鑛金屬層之第二區域係 設於最小頂側1 〇區間邊緣外侧之該底侧晶片上,該等第二區 域係藉由設置於一較大頂側晶片上之一相對應橋接(鑛金屬 層12 )而得接觸連接。這種編碼當然亦可在較小頂側晶片1 〇 之晶片區間内實施。 一般而言,藉由相對應之接觸區與橋接的組合,將可能 實現依據習知跳接器型態之一般編碼功能。在這種情況下, 可選擇性地將該等接觸區及橋接設置於該底側晶片及該頂側 晶片兩者上。 譬如’亦可藉由引出導體軌道2 6超越頂側晶片1 〇之區間 邊緣’以在完成之組件上實施編碼。為此,僅需譬如藉由雷 射來切斷相對應之連接(絕緣區域28)、或著藉由譬如一導電 黏著劑或焊料等一連接元件2 7來接觸連接相對應之導體軌道 即可。第4圖中係顯示出這種變型。 如此’譬如電阻器或電容器等離散組件,將可相同地施 加至底側晶片2 0且連接至導體軌道2 6。 第5圖係以剖面來顯示依據本發明之組件的又一說明用 具體實施例。在本說明用具體實施例中,底側晶片2 0亦大於 頂側晶片1 0。一大面積錢金屬層2 2係設於重疊區域外側且經 由一鍍通孔24而連接至一接觸墊2卜最上方鍍金屬層中之微
第U頁 1245403 ___案號 92105407_年月曰 ^ 五、發明說明(10) 小接觸墊將可因此引至一大接觸區。該接觸區在這種情況下 可具有10 Οχ 10 〇平方微米之一面積。這種可自由觸及之金屬 區係用於更進一步地接觸連接一打線接合。該可自由觸及之 鑛金屬層區2 2的表面較佳地係藉由浸潰而鍍金。 這種變型係提供,無需在某一晶片之最上方鍍金屬層的 區域中提供任何接合區的可能性。該接合區僅當欲在晶片之 主要區上預組立時實現,且係經由近似於1微米之一直徑的 微小鍍通孔而連接至積體電路。如此將可能減小晶片面積, 而提高一晶圓之產量。更,該接合鐘金屬層之面積可較一習 知方法者大幅增加。 第6圖係顯示又一說明用具體實施例,其中頂側晶片i 〇 具有一測試墊1 〇 〇,且該測試墊係經由一鍍通孔1 4而連接至 一接觸墊1 1。該測試墊僅檢查一晶片在製作期間内之功能。 一旦已確定功能正確,則不再需要觸及該測試墊。依據本發 明,測試墊1 〇 〇係連接至一鍍金屬層2 0 1,且該鍍金屬層係底 側晶片2 0第二鍍金屬層第二區域之一部份,以在該兩晶片之 間達成一穩定地固定。在一相對應之方式中,測試墊2 〇 〇係 設於底側晶片2 0之主要區上,且該測試墊係連接至頂側晶片 1〇鍍金屬層12中之一鍍金屬層1 0 1 -相同地不具有一電氣功 能。 相較於先前技藝中已知的配置,該測試墊無需額外的區 間。測試墊1 〇 〇、2 0 0係以完全相同於第5圖中接觸墊者之方 式,僅分別藉由該等第一與第二鍍金屬層實現。將該等區間 設於較小之頂側晶片丨〇的區域中時特別有利。因此,該等測 試墊在測試完成後將用於機械連接該等晶片,特別當該等鍍
1245403 案號 92105407_ 修正 五、發明說明(11) 金屬層第一區域外側之一大部分區間原本係作為僅為了機械 連接及散熱用之「虛設區」時尤然。是以,某些該等現存之 區間將可額外地預先用於該晶片之功能測試。該測試應可較 優地在塗佈及圖案化各鍍金屬層之後、於整個晶圓上實施。 測試完成後,包括譬如該第二晶片之晶圓可在無電極浸潰槽 中塗佈錫,且僅開放之鍍金屬層需要塗佈薄焊料層。如此即 可在所謂的「前段」中製作該等晶片。接著將在「預組立」 中實施製備接合墊、電路測試、及亦塗佈錫與垂直積體整 合,且該查直積體整合即係連接該等第一與第二晶片。此後
將在「後段」中安裝入外殼中。因此,可將電路測試整合於 安裝技術之製程流中。 一般而言,由於為了尋求 械接觸,因此在擴散焊接方法 地達成全區間的連接。為此, 層第二區域,將可作為虛設區 作為屏蔽之用,以使該等第— 去耦合。這特別在逐漸提高操 其必要性。 一良好的熱傳導及一良好的機 期間,試圖使該兩晶片儘可能 不具有電氣功能的該等鑛金屬 然而,該等區間亦可較優地 與第二晶片中之電路互相電氣 作頻率及切換速度之情況下有 第7 A圖係顯示一說明用呈μ企 . ,、體實施例,其中複數個鍍金屬 廣之第^一 &域係具體實;^
U久心日ΰ⑨ 成共平面之條狀、線、或相關於一或 兩個各別之晶片最上方金屬平 士 7RISI、。产德繳别〆# 屬十面而成為一垂直之條狀線(第 ί卿)。攻種變型係著眼於鉦 路。 考眼於無線電頻率電路之輸入/輸出線 在第8圖之說明用具體實 區域係環繞著鍍金屬層1 2
施例中,鍍金屬層1 2、2 2之第 2 2之第一區域呈環狀地形成-。
1245403 _案號92105407_年月曰 修正_ 五、發明說明(12) 由金屬製成之封閉環係密封住設於該等鍍金屬層第一區域中 之接觸,以完全密封地抵抗濕氣腐蝕。可在後續中藉由浸潰 而將該組件鍍金,以更進一步改良表面之抗腐蝕性。
第17頁 1245403 案號92105407 年 修正 圖式簡單說明 第1圖係說明藉由一擴散焊接方法連接一第一與第二晶片之 前的一組件之剖面圖。 第2A圖係說明利用部份之鍍金屬層作為一更一結線平面之第 二晶片之平面圖。 第2B圖係說明源自第2A圖中之配置的剖面圖。 第3A圖係說明鍍金屬層之第二區域係用作為一編碼之具體實 施例。 第3B圖係說明源自第3A圖中之配置的剖面圖。 第4圖係說明鍍金屬層之第二區域係作為一編碼之具體實施 例0 第5圖係說明鍍金屬層之第二區域係具體實施為接合墊之貫 穿該組件之剖面圖。 第6圖係說明各鍍金屬層之第二區域係具體實施為測試墊之 貫穿該組件之剖面圖。 第7A圖、第7B圖說明各鍍金屬層之第二區域係設計成一條狀 線之貫穿該組件之剖面圖。 ; 第8圖係說明鍍金屬層之第二區域係設計成一封閉環之該組 件之平面圖。 元件符號說明 11接觸墊 1 3活性主要區 2 1接合墊 22a、22b鑛金屬層 1 0、 1 0 ’晶片 12、12’鍍金屬層 2 0晶片 2 2鐘金屬層
第18頁 1245403 案號 92105407 曰 修正 圖式簡單說明 2 3活性主要層 2 5切口 2 7連接元件 3 0金屬層 1 0 1鑛金屬層 2 01鍍金屬層 24鍍通孔 2 6導體軌道 2 8絕緣區域 1 0 0測試墊 2 0 0測試墊
第19頁
Claims (1)
1245403 4 案號92105407 曰 修正 六、申請專利範圍 1 · 一種以擴散焊接法形成之半導體組件,特別係一種半導 體組件,其具有配置於一第二晶片(20)上之一第一晶片 (10),其中該等第一與第二晶片(1〇、20)皆在其主要區 (13、23)之上各具有第一與第二鍍金屬層(12、22),該等 第一與第二鍍金屬層係互相面對著,該等鍍金屬層(12、 22)之第一區域係用於在該等第一與第二晶片(1〇、2〇)之 間製作一電氣連接,及該等鍍金屬層(丨2、2 2 )之第二區域 則係作為該等第一與第二晶片(丨〇、2〇)外側之一額外的電 氣功能平面。 2:如申請專利範圍第1項之半導體組件,其中該第一及/或 第二鍍金屬層(12、22)係經由接觸材料元件(14、24)而 連接至位於一最上方鍍金屬層中之接觸墊(1} 'Η) Ο 3.如申請專利範圍第2項之半導體組件,其中該第一或 ^晶片(10、20)在相對其設置之晶片(2〇、上 等鍍金屬層(12、22)第-岡衫沾办嬰老 層,使得該等第二區1無任何鑛金屬 動時所需之-電氣功Γ執仃❹對設置晶片(2G、10)作 4 ·如申請專利範圍第1項 触 二晶片UH0)在相對員其二導二組;9’其中該第-或第 等鍍金屬層(12、22)第4日日(〇、10)上、具有該 層,使得該等第二區域置處,1無任何鑛金屬 動時所需之-電氣功能。仃该相對設置晶片(2G、10)作 5·如申請專利範圍第丨項 χ1Λλ . 半導體組件,並中該第^一曰y (ίο)具有不同大小,言亥第一干,、i亥弟日日片 日日片(10)係小於、等同於、或
第20頁 1245403 _ 案號 92105407 年 曰 六、申請專利範圍 大於该弟一晶片(20) ’及該第二晶片(20)在形成於該最小 第一晶片(10)與該第二晶片(20)主要區之間之一重叠區域 的至少外側處,具有該第二鍍金屬層(2 2 )之第二區域。 6.如申請專利範圍第5項之半導體組件,其中當一較大之 第一晶片(1 0 )配置於該第二晶片(2 〇 )上時,該等第二鑛金 屬層(22)第二區域可藉由該第一晶片(1〇)之第一鍍金^層 而接觸連接。 X 曰 7·如申請專利範圍第5項之半導體組件,其中在該第一晶 片(10)已配置於該第二晶片(20)上之後,該等第x二鑛金0曰屬 層(22)之第二區域可藉由使該等第二區域中之 斷或著連接,而達成一編碼。 守體軌道中 ?:申請專利範圍第5至7項之任一項之半導體組件,立中 士/”二鍵金屬層(12、22)之第二區域包括設於 q , . 弟一晶片(1〇、20)之重疊區域内的測試墊。 9片二申請專利範圍第8項之半導體組件,其中在該第一晶 片(10於该第二晶片(2°)上之後,該第-或第二晶 之第-墊將與相對設置之晶片上的鍍金屬層 心乐一 &域進仃機械接觸。 對設置項之半導體組件,纟中正好互相相 用於機;鍍2層(12、22)之第二區域係 比如申請專利/ΛΙίΓΛΙ二晶片(10、20)。 中正好互相相對設置之兮等項笛之一任「項之半導體組件,其 之第二巴妁禆用认μ荨苐一與第二鍍金屬層(12、22) ^域係用於機械式地固定該等第—與第二晶片 第21頁 1245403 案號 92105407 _a. 曰 修正 六、申請專利範圍 (10 、 20卜 1 2.如申請專利範圍第11項之半導體組件,其中互相相對 地設置且用於機械式固定的該等第二區域係設計成環繞著 該等第一與第二鍍金屬層(1 2、2 2)第一區域的一環狀型 式
第22頁
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DE10219353A DE10219353B4 (de) | 2002-04-30 | 2002-04-30 | Halbleiterbauelement mit zwei Halbleiterchips |
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EP (1) | EP1500142A2 (zh) |
DE (1) | DE10219353B4 (zh) |
RU (1) | RU2290718C2 (zh) |
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US20100084755A1 (en) * | 2008-10-08 | 2010-04-08 | Mark Allen Gerber | Semiconductor Chip Package System Vertical Interconnect |
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RU2006990C1 (ru) | 1991-01-22 | 1994-01-30 | Константин Иванович Баринов | Большая интегральная схема (ее варианты) |
DE19531158A1 (de) * | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Verfahren zur Erzeugung einer temperaturstabilen Verbindung |
KR100438256B1 (ko) * | 1995-12-18 | 2004-08-25 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체장치 및 그 제조방법 |
DE19632378B4 (de) * | 1996-08-10 | 2007-01-25 | Robert Bosch Gmbh | Diffusionslötverbindung und Verfahren zur Herstellung von Diffusionslötverbindungen |
US5898223A (en) * | 1997-10-08 | 1999-04-27 | Lucent Technologies Inc. | Chip-on-chip IC packages |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
JP3365743B2 (ja) * | 1999-02-03 | 2003-01-14 | ローム株式会社 | 半導体装置 |
JP4246835B2 (ja) * | 1999-03-09 | 2009-04-02 | ローム株式会社 | 半導体集積装置 |
JP3388202B2 (ja) * | 1999-05-26 | 2003-03-17 | ローム株式会社 | 半導体集積回路装置ならびに装置の組立方法 |
JP2002289768A (ja) * | 2000-07-17 | 2002-10-04 | Rohm Co Ltd | 半導体装置およびその製法 |
US6396156B1 (en) * | 2000-09-07 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Flip-chip bonding structure with stress-buffering property and method for making the same |
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US6683385B2 (en) * | 2002-04-23 | 2004-01-27 | Ultratera Corporation | Low profile stack semiconductor package |
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2002
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2003
- 2003-03-12 EP EP03714696A patent/EP1500142A2/de not_active Withdrawn
- 2003-03-12 RU RU2004134730/28A patent/RU2290718C2/ru not_active IP Right Cessation
- 2003-03-12 TW TW092105407A patent/TWI245403B/zh not_active IP Right Cessation
- 2003-03-12 WO PCT/DE2003/000787 patent/WO2003094234A2/de not_active Application Discontinuation
-
2004
- 2004-10-27 US US10/974,542 patent/US7335582B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7335582B2 (en) | 2008-02-26 |
DE10219353B4 (de) | 2007-06-21 |
TW200306660A (en) | 2003-11-16 |
EP1500142A2 (de) | 2005-01-26 |
RU2004134730A (ru) | 2005-07-20 |
WO2003094234A2 (de) | 2003-11-13 |
DE10219353A1 (de) | 2003-11-20 |
US20050121801A1 (en) | 2005-06-09 |
WO2003094234A3 (de) | 2004-02-12 |
RU2290718C2 (ru) | 2006-12-27 |
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