TW201546922A - 具有打線接合互連的低熱膨脹係數部件 - Google Patents
具有打線接合互連的低熱膨脹係數部件 Download PDFInfo
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- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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Abstract
一種部件(例如,中介層或微電子元件)可製造有打線接合結構的一組垂直延伸的互連。此種方法可包含:形成一結構,該結構具有打線接合,打線接合延伸於一元件中的一或更多個開孔的一開孔內的一軸向方向中,且每一打線接合至少部分間隔於其所延伸的該開孔的一壁部,該元件實質上包含具有熱膨脹係數(CTE)小於10ppm/℃的材料。然後可提供第一接點於該部件的第一表面處,且可提供第二接點於該部件的第二表面處,第二表面面向相反於第一表面的方向,該等第一接點透過該等打線接合而電性耦接於該等第二接點。
Description
本申請案中所述的技術內容係涉及具有打線接合通孔延伸於具有低熱膨脹係數(CTE)的元件(例如,中介層或微電子元件)的厚度方向中之部件,以及其製造方法。此種部件可組裝於微電子組件中的一或更多個其他的元件。
半導體晶片的微電子裝置通常需要許多對於其他電子部件的輸入與輸出連接。半導體晶片或其他類似裝置的輸入與輸出接點通常設置成類似格柵的型態(通常稱為「區域陣列」),其實質上覆蓋該裝置的表面,或者設置成伸長的列,其可延伸平行於該裝置的前表面的每一邊緣且相鄰於每一邊緣,或在前表面的中心中。通常,裝置(例如,晶片)必須實體安裝在基板上(例如,印刷電路板),且裝置的接點必須電連接至電路板的導電部位。
半導體晶片通常設置於封裝中,封裝促進在製造期間以及在安裝晶片於外部基板上(例如電路板或其他電路平板)的期間晶片的處理。例如,許多半導體晶片設置於適於表面安裝的封裝中。已經提出此種一般
類型的數種封裝來用於多種應用。一般而言,此種封裝包含介電質元件(通常稱為「晶片載體」),具有形成為板狀或蝕刻金屬結構的端子在該介電質上。這些端子通常藉由例如沿著晶片載體本身延伸的細線跡之特徵以及藉由延伸於晶片接點與端子或線跡之間的細引線或導線,而連接於晶片本身的接點。在表面安裝操作中,封裝係置於電路板上,使得封裝上的每一端子對準於電路板上的對應接墊。焊料或其他接合材料設置於端子與接墊之間。藉由加熱該組件來熔化或「回焊」焊料或者活化該接合材料,該封裝可永久地接合在定位。
許多封裝之焊料塊係為焊料球的形式,通常直徑為大約0.1
mm與大約0.8mm(5與30密爾)之間,附接於封裝的端子。具有焊料球陣列從其底表面突伸的封裝通常稱為球柵陣列或「BGA(ball grid array)」封裝。其他封裝(稱為平面柵格陣列或「LGA(land grid array)」封裝)藉由形成自焊料的薄層或平面而固定至基板。此種封裝可以很精小。某些封裝(通常稱為「晶片級封裝」)占據電路板的面積係等於(或僅稍微大於)該封裝中所併入的裝置的面積。這是有利的,因為它減小組件的整體尺寸,並且允許使用基板上的各種裝置之間的短互連,這接著限制了裝置之間的信號傳輸時間,且因此促成組件以高速操作。
中介層可提供作為互連元件,具有接點與其頂與底表面電連
接於其頂或底表面的一者處之一或更多個已封裝的或未封裝的半導體晶粒,並且電連接於其頂或底表面的另一者處之另一部件。另一部件在一些情況中可為封裝基板或電路平板。當另一部件為封裝基板時,在一些情況中,封裝基板可接著電連接於可為或可包含電路平板的又另一部件。
本發明提供一種方法,用於製造部件,部件可為中介層或其他裝置,例如,包含中介層的微電子元件或組件、微電子元件、或其組合。此種方法可包含形成一結構,該結構包含複數個打線接合,每一打線接合延伸於一元件中的一或更多個開孔的一開孔內的一軸向方向中,且每一打線接合至少部分間隔於其所延伸的該開孔的一壁部,該元件實質上包含具有一熱膨脹係數(CTE)小於10ppm/℃的一材料。該結構通常具有在該部件的一第一表面處的第一接點以及在該部件的一第二表面處的第二接點,該第二表面面向相反於該第一表面的一方向。該等第一接點可為該等打線接合的第一端部或者該等第一接點可耦接至該等打線接合的第一端部。該等第二接點通常電性耦接於該等打線接合。
藉由使用打線接合作為垂直互連來形成低CTE部件,低CTE部件的厚度可增加,超出使用矽通孔(TSV,through silicon via)處理所通常可能達成的厚度。這是因為打線接合互連可在被組裝於低CTE元件的開孔內之前形成,消除了TSV處理中藉由沉積(例如,電鍍)來在低CTE元件的孔中填充金屬之需求。利用TSV處理,在小孔內電鍍的成本會隨著孔的深度增加而以指數方式增加。因此,具有TSV的半導體元件與主動晶片通常需要薄化至100微米或更小的厚度,以允許藉由填充沉積的金屬來形成TSV。此要求已經導致產業進入另外的困境,最顯著的困境就是薄晶圓的處理。
本文實施例中,其所教示的低CTE部件或中介層的厚度可遠大於形成有TSV的薄晶圓的厚度。例如,低CTE部件可形成自實質上包含低
CTE材料的元件或區塊,其中其厚度可大於50微米,或者在一範例中可為0.5毫米至2毫米。在一具體範例中,該厚度可為大約一毫米。如同本文將進一步敘述的,在處理期間低CTE部件的薄化可能一點也不需要,因為打線接合(其延伸於垂直方向中)可形成為等於低CTE部件的厚度。
此外,當較薄的低CTE中介層或晶片結合於具有較高CTE的其他元件時,此種低CTE部件併入於微電子組件中可協助解決可能的翹曲問題。這至少部分是由於低CTE部件的較大的厚度(例如,高達一毫米),這可使用本文所揭示的結構與方法來達成。
根據本發明的構想,在該元件中的該等開孔可未被該元件的任何部分覆蓋,且可未被具有小於10ppm/℃的CTE的任何其他元件覆蓋。
根據本發明的構想,形成該結構包含:提供一第一元件,該第一元件具有複數個打線接合係向上延伸離開該第一元件。可將該等打線接合***至具有小於10ppm/℃的CTE的該元件中的一或更多個開孔中。
根據本發明的構想,該方法可另包含形成下述至少一者:電性耦接於該等打線接合與該等第一接點之間的一第一再分佈層,或電性耦接於該等打線接合與該等第二接點之間的一第二再分佈層。
根據本發明的構想,形成該結構可另包含:形成該等打線接合,使得該等打線接合的第一端部形成於一第一再分佈層的金屬元件上,且然後將每一打線接合***至該一或更多個開孔的一開孔中。
根據本發明的構想,形成該結構可包含:將該複數個打線接合的個別打線接合***至該元件中的個別開孔中,使得每一打線接合可藉由該元件的材料而彼此分隔。
根據本發明的構想,當該等個別的打線接合***於該等開孔中時,該等開孔可為盲開孔,且該方法另包含:在該***之後,減少該元件的一厚度,以提供對於該等打線接合的端部的使用。
根據本發明的構想,該***可包含:將該複數個打線接合的一些打線接合***該複數個開孔的同一開孔中。
根據本發明的構想,可在接觸於該等打線接合的該等開孔內提供一電性絕緣材料。
根據本發明的構想,該元件可包含複數個主動裝置,該第一或第二接點的至少一些係電性耦接於該複數個主動裝置。
根據本發明的構想,該元件可包含一單晶半導體區域,且至少一些該等主動裝置可至少部分設置於該單晶半導體區域內,該等開孔至少部分延伸通過該單晶半導體區域。
根據本發明的構想,提供一種部件,其包含:複數個打線接合,每一打線接合延伸於一元件中的一或更多個開孔的一開孔內的一軸向方向中,該元件具有小於10ppm/℃的一熱膨脹係數(CTE)。每一打線接合可至少部分間隔於其所延伸的該開孔的一壁部。該部件可另包含:在該部件的一第一表面處的第一接點以及在該部件的一第二表面處的第二接點,該第二表面面向相反於該第一表面的一方向。該等第一接點可為該等打線接合的第一端部或者該等第一接點可耦接至該等打線接合的第一端部。該等第二接點可電性耦接於該等打線接合。
根據本發明的構想,下述至少一者成立:該等第一接點或該等第二接點可透過一再分佈層而電性耦接於該等打線接合。該再分佈層在
該等打線接合之上且在該元件的一表面之上,該元件的該表面界定橫越該等開孔的該軸向方向之一平面。在一具體範例中,該複數個打線接合的個別打線接合可設置在該元件中的個別開孔內,使得每一打線接合可藉由該元件的材料而彼此分隔。在一範例中,該複數個打線接合的一些打線接合可設置在該複數個開孔的同一開孔內。在一具體範例中,一開孔可不具有一打線接合設置在其中。在一範例中,一電性絕緣材料可在接觸於該等打線接合的該等開孔內。在一範例中,該電性絕緣材料可僅接觸或圍繞與該等打線接合的該等第一端部相鄰之該等打線接合的部分,或者可僅接觸或圍繞與該等打線接合的該等第二端部(其相對於該等第一端部)相鄰之該等打線接合的部分,或者可僅接觸或圍繞該等打線接合的該等第一與第二端部。
根據本發明的構想,該元件可包含複數個主動裝置,其中該
等第一與第二接點可電性耦接於彼此並且電性耦接於該複數個主動裝置的至少一些主動裝置。
根據本發明的構想,該元件可包含一單晶半導體區域,至少
一些該等主動裝置係至少部分設置於該單晶半導體區域內,且該等開孔至少部分延伸通過該單晶半導體區域。
根據本發明的構想,該等第一接點與該等第二接點可離該等
打線接合小於50微米的一軸向距離內。
根據本發明的構想,該等打線接合可僅部分延伸通過該元件
的一厚度,且該部件可另包含導電連接器,該等導電連接器從該等打線接合延伸於一軸向方向中、至少部分通過該元件的該厚度的其餘部分,該等
連接器由沉積的導電材料形成。
根據本發明的構想,下述至少一者成立:該等第一接點或該
等第二接點可不透過一再分佈層電性耦接於該等打線接合。該再分佈層在該等打線接合之上且在該元件的一表面之上,該元件的該表面界定橫越該等開孔的該軸向方向之一平面。
根據本發明的構想,該等打線接合可包含具有不同直徑的導
線,且一打線接合的直徑可大於其他打線接合的直徑,在一範例中,達至少3%,或在另一範例中,達至少10%。
根據本發明的構想,至少一打線接合的長度可短於其他打線
接合的長度達該等其他打線接合的長度的20%以下。
根據本發明的構想,該複數個打線接合的個別打線接合可設
置在該元件中的個別開孔內,使得該等打線接合的至少一或更多者可不藉由該元件的材料彼此分隔。
根據本發明的構想,該複數個打線接合的個別打線接合可設
置在該元件中的個別開孔內。在一些實施例中,該元件中的該一或更多個開孔可不包含一打線接合。
根據本發明的構想,該複數個打線接合的個別打線接合可設
置在該元件中的個別開孔內,且該元件中的至少一或更多個開孔包含介電質材料。
10‧‧‧微電子部件
11‧‧‧部件
12、12A、12B、12C、12D、52、112A、112B、112C‧‧‧微電子元件
13‧‧‧面
16、16B‧‧‧第一接點
17‧‧‧接合元件
19‧‧‧低CTE元件
20‧‧‧封裝基板
31‧‧‧軸部
32、35‧‧‧打線接合
33‧‧‧第一端部
34‧‧‧基部
37‧‧‧邊緣表面
38‧‧‧開孔
39‧‧‧第二端部
40‧‧‧介電質材料
42‧‧‧金屬片
43‧‧‧載體
45‧‧‧處理中的元件
46‧‧‧第二接點
48‧‧‧部分
49‧‧‧黏著劑
50‧‧‧電路平板
51‧‧‧接點
53‧‧‧表面
54‧‧‧線跡
55‧‧‧處理中的元件
60‧‧‧第一方向
61‧‧‧第二方向
100‧‧‧微電子組件
102‧‧‧微電子組件
110‧‧‧部件
113‧‧‧上表面
114‧‧‧第二表面
118‧‧‧介電質層
119‧‧‧低CTE元件
121‧‧‧表面
132‧‧‧打線接合
138‧‧‧開孔
140‧‧‧介電質材料
144‧‧‧第一表面
148‧‧‧互連結構
149‧‧‧金屬連接器
152‧‧‧介電質層
155‧‧‧處理中的元件
157‧‧‧處理中的元件
159‧‧‧處理中的元件
210‧‧‧部件
310‧‧‧部件
410‧‧‧部件
419‧‧‧半導體區域
421‧‧‧主動裝置
438‧‧‧開孔
440‧‧‧介電質填充材料
443‧‧‧載體
458‧‧‧前表面開孔
465‧‧‧處理中的元件
470‧‧‧微電子元件
471‧‧‧後表面
472‧‧‧前表面
第1A圖為本案較佳實施例之部件(例如,中介層)的剖面視圖,其互連於微電子組件內。
第1B圖為本案較佳實施例之替代的部件(例如,中介層)的剖面視圖,其互連於微電子組件內。
第2A圖為第1A或1B圖中所見的實施例的變化型,為部件(例如,中介層)的剖面視圖,其互連於微電子組件內。
第2B圖為本案較佳實施例之微電子組件內的部件(例如,中介層)的對應平面視圖。
第2C圖為第2A與2B圖進一步變化型,為中介層的剖面視圖,其互連於微電子組件內。
第3圖為本案較佳實施例之部件的剖面視圖。
第4圖為本案較佳實施例之中介層的平面視圖。
第5圖為本案較佳實施例之處理中的元件的剖面視圖,用於在製造方法中併入於部件中。
第6圖為本案較佳實施例之低CTE元件的平面視圖。
第7圖為本案較佳實施例之低CTE元件的對應剖面視圖,其用於在製造方法中併入於部件中。
第8、9、10與11圖為本案較佳實施例之剖面視圖,例示製造如同第3圖中所見的部件之方法中的階段。
第12、13、14與15圖為本案較佳實施例之變化型之剖面視圖,例示製造部件之方法中的階段。
第16、17與18圖為本案較佳實施例之變化型之剖面視圖,例示製造部
件之方法中的階段。
第19與20圖為第16、17與18圖之變化型之剖面視圖,例示製造部件之方法中的階段。
第21、22與23圖為第16、17與18圖之變化型之剖面視圖,例示製造部件之方法中的階段。
第24、25、26、27與28圖為本案較佳實施例之剖面視圖,例示製造微電子元件之方法中的階段。
本文敘述部件,例如,中介層、微電子元件、與包含此種部件的微電子組件,其包含由具有小於10ppm/℃的熱膨脹係數的材料(「低CTE材料」)所製成的元件,通常為固體單塊的半導體材料,例如矽、III-V族半導體化合物(例如,GaAs、InP等)、或介電質材料(例如,玻璃、石英、氧化鋁(例如,Al2O3)或其他陶瓷材料等。複數個打線接合互連係延伸於一或更多個開孔內的軸向方向中,一或更多個開孔延伸通過低CTE元件的厚度。具有低CTE的部件可有利地用於多種應用中,其中當低CTE部件組裝緊鄰於具有較高CTE的另一部件並且受到高的熱應力時,不同的熱膨脹通常會是一個問題。
在此種部件中,部件的第一表面處的第一接點係藉由打線接合而互連於在部件的第二表面處的第二接點。使用打線接合作為延伸通過元件厚度的垂直互連可在一些情況中導致製造成本與工具成本的減少。打線接合可製成突伸至其所接合的下方結構的表面之上數十至數百微米或更
大的實質距離,且因此可製成提供通過元件中的較深開孔之垂直互連。因此,使用此種打線接合垂直互連可協助避免與薄化元件(例如,薄化的半導體晶圓等)的處理及薄化相關的成本,且使用此種打線接合垂直互連可協助避免與利用沉積金屬來形成垂直互連之高縱橫比的開孔的形成與填充相關的成本。
每一打線接合互連具有不超過一個端部接合至在第一表面
附近的位置處的下方的金屬表面,且每一打線接合的另一端部遠離此種端部,未接合於並且靠近第二表面。
藉由上下文,第1A圖為根據本文敘述的實施例來建構之微
電子部件10,其進一步組裝於具有其他部件的微電子組件100中。在隨後的說明與圖式中,相同的元件符號係用於表示相同的特徵,且相似的元件符號係用於表示相似的特徵。如第1A圖,第一與第二接點46、16分別設置在部件10的第一與第二相對表面處。接點46、16可接著電連接於面向那些接點46、16的微電子組件的第一與第二部件的對應接點。本文所述的部件(例如,中介層、基板、電路平板、微電子元件等)通常具有在其外部表面上的介電質結構。因此,當在本揭示案中使用時,導電元件在部件的介電質結構的表面「處」的陳述係表示:當部件未組裝於任何其他元件時,導電元件可用於接觸於一理論點,該理論點移動於垂直於部件的表面的方向中、從部件的外部朝向部件的表面。因此,在部件的表面處的端子、接點、或其他導電元件可從此種表面突伸;可齊平於此種表面;或可相對於此種表面,凹陷於部件中的孔或凹部中。
如第1A圖所示,具有低CTE元件的部件10可電連接於第一
部件12,第一部件上具有主動電路元件(例如,微電子元件),例如已封裝或未封裝的半導體晶粒,其具有面向部件10的第一表面144之面13並且已封裝或未封裝為連接至中介層的第一接點46。如同第1A圖中進一步所示,中介層的第二接點16可電連接於該組件的另一部件的對應接點(其面向接點16),如第1A圖所示的封裝基板20的接點。第一與第二接點46、16可透過打線接合32而電性耦接,打線接合32作用為垂直互連,延伸於部件10的低CTE元件19的厚度方向中,每一打線接合延伸於低CTE元件19中的一或更多個開孔的一開孔中。當在本文使用時,元件19的厚度方向係界定為部件10的軸向方向,且軸向方向中的距離為軸向距離。在一範例中,低CTE元件19在軸向方向中的厚度可大於50微米。在一具體範例中,該厚度可為50微米至1毫米之間。在一具體範例中,該厚度可為0.5毫米至2毫米的範圍內。
在一些情況中,第一接點或第二接點或者第一接點與第二接
點兩者可為打線接合的端部。在一些情況中,打線接合的端部可為球接合,其在製造處理之後至少部分保留。在一些情況中,一些打線接合32的端部可為接點或可機械地耦接至此種接點,但是此種打線接合可能並非全部都透過在第一表面144處的接點46與在第二表面處的接點16而電性耦接於另一部件。在具體的實施例中,部件10中可僅有一個打線接合。
因為可組裝於組件100中的其他部件,部件10可為中介層,
用於電性耦接中介層之上的第一部件(像是例如,微電子元件12)於第二部件(例如,封裝基板20)。作為第1A圖所示的配置的替代或者除了該配置之外,一些或所有的第二接點16可連接於具有面向部件的第二表面114之表面的第二未封裝或已封裝的半導體晶粒。封裝基板20或互連於部件10的其
他部件可接著安裝至電路平板50的接點51,如同第1A圖所示。或者,在一些情況中,封裝基板20可從微電子組件100省略,且部件10的接點16可電性耦接於電路平板50的對應接點51。
在一範例中,部件10的區域與邊緣可對準於微電子元件12的區域與邊緣,使得表面114佔據微電子元件的表面13的突伸區域之區域。在此種範例中,部件10與接合至其的微電子元件12可形成「晶片級封裝」或「CSP(chip-scale package)」。
第1B圖為另一範例,例示微電子組件102,其中第一與第二微電子元件12、52可透過在部件11的第一表面144處的第一接點46而電性互連於部件11。微電子元件(其可為已封裝或未封裝的半導體晶粒)可透過設置在部件11上的導電結構(例如,其上的線跡54)而電性互連於彼此,線跡54可延伸於平行於部件的第一與第二表面114之方向中。
第2A-2B圖為一種替代方式,其中微電子元件12A、12B可電性耦接於部件10(例如,中介層)。如同其中所見的,微電子元件12A、12B經由打線接合35而耦接於在中介層的上表面處的接點46。接點46可在一些情況中為打線接合32的端部,打線接合32延伸於低CTE元件19的軸向方向中。或者,再分佈結構可設置在打線接合32的端部與接點46之間,或者在打線接合32的端部與接點16之間,或者在打線接合的端部與接點46及16兩者之間。如同第2B圖進一步所見的,額外的微電子元件12C與12D可設置在中介層的頂部上,一些或全部的微電子元件12C與12D可電性耦接於中介層的導電元件。
第2C圖為進一步的變化,其中微電子元件112A與112B具有
接點承載面,其面向部件10的上表面。在此情況中,微電子元件112A與112B的至少一些接點面向部件10的對應接點46並且藉由覆晶接合而電性耦接於其,覆晶接合例如(但不限於)可包含導電材料或擴散接合之接合,其將微電子元件112A與112B的接點耦接於與其並置的對應接點46。第2C圖另外例示額外的微電子元件112C,其可電性耦接於部件10,例如以面向上的配置,其中一或更多個打線接合35耦接於微電子元件112C的面向上表面113上的接點與部件10的一或更多個接點46。第2C圖另外例示另外包含基板20的組件,基板20電性耦接於在部件10的下表面處的接點16。
參見第3圖,其為部分剖視圖,進一步例示部件10,例如上
面參見第1圖或第2圖所示與所述的。如同其中所見的,複數個打線接合32延伸作為通過至少一開孔38的垂直互連,開孔38延伸通過低CTE元件19的厚度。低CTE元件通常可包含固體單塊元件,實質上包含低CTE材料,開孔38延伸通過低CTE材料。在具體的範例中,低CTE元件可實質上包含半導體材料,例如矽、鍺、III-V族半導體化合物、或介電質材料的固體塊(例如,玻璃、石英、或陶瓷材料(像是例如,Al2O3)等。選擇性地,如同下面將進一步敘述的,介電質材料40可設置在開孔38內,且可接觸於打線接合32的個別一者的邊緣表面37。在第3圖所見的範例中,介電質材料40可充填開孔;然而,在本文提供的其他實施例中,特定打線接合或每一打線接合的邊緣表面37的一些部分或全部可不接觸於介電質材料。導電再分佈層可由介電質層118絕緣及/或支撐,導電再分佈層可電性耦接打線接合32的第一端部33於接點16。再分佈層可由介電質層152絕緣及/或支撐,再分佈層可電性耦接打線接合的第二端部39於接點46。在一範例中,再分佈層可根據一般
用於形成現有部件(例如,中介層或半導體晶片)的表面上的再分佈層之處理來形成,其中「層」可表示:通常在「晶圓廠」中形成包含半導體晶片(具有主動裝置在其上)的晶圓之後,藉由「後晶圓廠(post-fab)」的處理所形成的結構,該結構包含可延伸平行於其表面之一或更多個層的介電質材料與一或更多個金屬層。在一具體範例中,複數個金屬層可藉由延伸於延伸通過至少一金屬層的厚度之垂直方向中的互連而互連於彼此。在另一範例中,再分佈層可為「後段製程」或「BEOL(back end of line)」結構,藉由通常在「晶圓廠」中使用的製造方法來形成。在又另一範例中,再分佈層可包含BEOL結構與形成於其上或電性耦接於其的後晶圓廠部分。接合元件17(例如,焊球或其他接合金屬塊或導電材料)可附接或形成於接點16上。類似的塊或焊球可附接或形成於接點46上。
在具體的實施例中,打線接合32可由銅、金或鋁製成,且可
在一些情況中具有不同金屬的加工層曝露於打線接合的外表面處。每一打線接合的直徑可例示性地為1至500微米(microns)之間的直徑。處理中的元件中的相鄰導線的最小間距的範圍可最小為導線的最小直徑的大約兩倍,而當導線直徑較大時,則可為導線直徑的較小倍數之數值。在一範例中,第一與第二接點46、16可為離其所電性耦接的打線接合32小於50微米(microns)的軸向距離內。
第4圖為對應的平面視圖,面向頂表面144或替代地部件10
的底表面114之任一者。如同第3與4圖中所見的,第一與第二接點46、16可製成延伸於平行於頂或底表面144、114的橫向方向中、超出個別的打線接合32的邊緣表面37,如同接點46A與16A的實例中所見的。部件10的製造可
如同下面進一步敘述的。現在參見第5圖,現在將敘述製造部件10(例如,中介層)的方法。如同第5圖中所見的,處理中的元件45可包含未端接的打線接合32的陣列,其形成為從打線接合所接合的一或更多個金屬表面向上延伸。此打線接合陣列可藉由形成打線接合來接合金屬導線至其不同位置處的一或更多個表面而形成,表面可為陣列的位置,且可為一或更多個金屬表面或打線接合之下的金屬片的表面。在一範例中,打線接合32可藉由接合導線至一或更多個表面(例如,接點的表面)或至金屬片42的表面而形成。在例如第5圖所示的範例中,金屬片42不需要為自己或打線接合32提供完全的力學支撐,因為該功能可由支撐載體43來執行,支撐載體43可釋放地附接或夾設至金屬片。在一具體範例中,接合工具可接合金屬導線至層狀結構的曝露表面,層狀結構包含未圖案化的或已圖案化的金屬片,且層狀結構可包含一或更多個加工金屬層在其上。因此,在一範例中,打線接合可形成在具有鋁、銅或其合金等的金屬層之基部上,且在一範例中,加工層可包含「ENIG」加工,例如藉由無電沉積而沉積在基部金屬上的鎳層,接著藉由浸漬處理而沉積在鎳層上的金層。在另一範例中,基部金屬層可具有「ENEPIG」加工,例如可為下述的組合:沉積於基部金屬上的無電沉積鎳層,接著於其上沉積無電沉積鈀層,且接著藉由浸漬處理而在鈀上沉積金層。
藉由前面提及的共同擁有與併入的一或更多個美國申請案
中所前述的技術,打線接合可藉由接合金屬導線至表面而形成。在一範例中,打線接合可藉由球接合金屬導線至表面而形成,例如藉由在導線的尖端處加熱導線,以形成熔化的金屬球並且利用該球來接觸該表面,以形成
球接合,來形成導線的球狀部分作為打線接合的第一端部33或基部,例如如同第3圖所示。在此種範例中,當基部藉由球接合而形成時,打線接合的基部可具有類似於球或球的部分之形狀。具有藉由球接合而形成的基部之打線接合可具有如同例如美國專利申請案第13/462,158號中所述的形狀並且如同該申請案所述地形成,其揭示內容以引用之方式併入本文。或者,打線接合可藉由其他技術而形成,例如針腳式接合(stitch bonding)或楔形接合(wedge bonding),其中導線的邊緣表面的一部分接合至一表面,且可具有大體上如同例如美國專利申請案第13/404,408、13/404,458、13/405,125號中所見的形狀,其揭示內容以引用之方式併入本文。在此種配置中,基部34可具有稍微平坦的圓柱形形狀,其可以以實質的角度(例如,15至90度)延伸遠離該軸。打線接合的向上延伸軸部31不需要相對於接合的基部34垂直延伸,但是反而可以以實質的角度(例如,15至90度)從其延伸。
以此方式形成的打線接合的具體範例可如同這些併入的申請案中所述的。
第6與7圖分別為低CTE元件19的平面視圖與橫剖面視圖,如同上述具有複數個開孔38在其中,其中相鄰開孔之間的低CTE元件19的部分48延伸至更大的厚度。開孔可以還是盲開孔,因為每一開孔可不完全延伸通過低CTE元件的厚度,如同第7圖所示。開孔38通常藉由光學或機械燒蝕來形成,例如藉由雷射、機械研磨、乾式與濕式蝕刻方法。在第6與7圖中所見的範例中,每一開孔的尺寸可設計成容納複數個相鄰的打線接合32,該等打線接合32可延伸於第一方向60中、成一列,且在一些情況中,也可延伸於橫越第一方向的第二方向61中、成一行。因此,每一開孔38可具有延伸於第一與第二方向60、61的一或更多者中的尺寸,在每一方向中的尺
寸為數十微米至數百微米。
在第8圖所見的處理階段中,處理中的元件45與低CTE元件
19黏合而形成處理中的元件47。例如,低CTE元件19相對於第7圖所示的定向反轉,且然後黏合於處理中的元件45。在一實施例中,黏著劑49可提供於打線接合32的基部34的頂部上,黏著劑接合開孔38之間的低CTE元件19的部分48。在一具體範例中,低CTE元件19可放置成靠近處理中的元件45或放置在處理中的元件45的頂部上,且然後底層填料可水平流動至處理中的元件45與低CTE元件之間的間隙,以形成第8圖所示的結構。或者,黏著劑49可為沖壓黏著膜或圖案化分配的黏著劑,其接合低CTE元件19的部分48於金屬片42的頂表面。如同第8圖中所見的,黏著劑49可接觸或流動至打線接合32。或者,黏著劑49可不接觸或流動至打線接合32。
之後,如同第9圖中所示,低CTE元件可從頂部薄化,像是
例如藉由研磨、研磨的化學品、拋光或離子處理、或其組合,直到開孔38在頂部處曝露出。在一範例中,研磨、精研或拋光可用於薄化低CTE元件。
在另一範例中,可使用蝕刻,例如反應離子蝕刻或電漿蝕刻處理。在一範例中,研磨、精研或拋光可用於低CTE元件的粗糙薄化,其可隨後藉由選擇性反應離子蝕刻介電質填充40,以使打線接合32的端部39突伸於開孔38之間的低CTE元件的部分48的表面之上。
開孔38可隨後填充有合適的介電質材料40。可選擇介電質材
料,以避免干擾部件10的操作,部件10在一些情況中會需要在經歷快速或極端的溫度波動的環境中使用。因此,有利的是,在一些情況中,提供低CTE介電質材料40於開孔內,開孔可具有較低的CTE(例如,具有小於12
ppm/℃的CTE),或者開孔的CTE可相同或相近於低CTE元件的CTE。低CTE材料往往相當硬,因為它們的楊氏模數(彈性的度量)往往遠遠高於聚合材料;因此,發現到,當使用此方法時,會需要具有CTE較相近於低CTE元件19的CTE之填料材料。因此,針對此目的,熔化的玻璃為一種可能的低CTE填料材料,其可使用作為填料介電質材料40。或者,開孔38可填充有具有較高CTE的材料,但是,其可為順應式材料,例如聚合材料,此種材料具有低的楊氏模數。在一些實施例中,介電質填充40可包含多孔聚合物,例如多孔的聚酰亞胺。在一些實施例中,介電質材料40可包含多於一種的介電質材料。例如,主要的介電質可為一層多孔的聚酰亞胺或其他介電質材料,且此種層可覆蓋有氧化物,其在一範例中可為沉積自原矽酸四乙酯(TEOS)前驅物的氧化物。TEOS層可包含打線接合表面39的端部39之上的RDL。
接著,如同第10圖中進一步所見的,將延伸於低CTE元件的
部分48之上的填料介電質材料40的部分移除,且打線接合的端部39可藉由露出處理而曝露。再分佈層或後段製程(BEOL)互連層可形成於打線接合32的端部39的頂部上,其中接點46與選擇性的線跡54可設置於此。載體43可之後移除,且金屬片42(如果存在的話)可移除,以產生部件10,像是例如第11圖中所見的,或者如同上面參照第3圖所示與所述的。在一些實施例中,金屬片可圖案化,以製造再分佈層或形成電性接點,例如第一接點46或第二接點16。
第12圖為相關於第5-11圖所上述的實施例的變化型,例示製
造階段。在此情況中,處理中的元件55可包含形成於具有線跡54與接點46
預先形成在其中的BEOL或再分佈層的頂部上的打線接合32,再分佈層設置於載體43的頂部上。在一些實施例中,載體43可包含晶片、封裝或未封裝裝置。在一些實施例中,打線接合32可包含不同直徑的導線。在此種範例中,一或更多條導線的直徑可大於其他導線的直徑至少3%。另外,一或更多條導線的直徑可大於其他導線的直徑至少10%。
第12圖為相關於第5-11圖所上述的實施例的變化型,例示製
造階段。在此情況中,處理中的元件55可包含形成於具有線跡54與接點46預先形成在其中的再分佈層的頂部上的打線接合32,再分佈層設置於載體43的頂部上。第13-14圖為製造階段,其中處理中的元件55黏合於低CTE元件19,且介電質材料係附加至其,以類似於相關於第8與9圖所上述的介電質材料的方式。第15圖為進一步的處理階段,其中接點16或16B可形成為電性連通於打線接合32。例如,接點16可形成於介電質填充40的頂部上,且接點16B可形成於從介電質填充的表面53延伸至打線接合32之凹部中。在一範例中,介電質填充40可延伸至低CTE元件19的表面121的高度之上的高度,例如,當接點以16B所示的方式形成時。或者,介電質填充40的頂表面可對準於低CTE元件19的表面121。在一些實施例中,一或更多個打線接合32較短於其他打線接合。例如,一或更多個打線接合32較短於其他打線接合達其他打線接合的長度的20%以下。在一些應用中,一或更多個打線接合32較短於其他打線接合達其他打線接合的長度的10%以上。
第16-18圖為相關於第3-11圖所上述的實施例的變化型,其
中低CTE元件119中的每一開孔138的尺寸係設計成容納單一打線接合。例如,處理中的元件155的每一打線接合32的圓柱軸可垂直延伸於低CTE元件
中的單一開孔138內。當低CTE元件由半導體材料製成時,每一開孔138在黏合於其中的處理中的元件之前可利用介電質材料作為襯裡。例如,此種介電質襯裡可藉由數種可能的處理而沉積或形成於其上,其可包含化學氣相沉積、局部氧化或氮化等。第17與18圖例示製造處理的階段,其類似於第13與14圖中所示的那些,其中在低CTE元件已經黏合於處理中的元件155之後,介電質填充可形成在開孔138中。第18圖進一步顯示以此方式形成的範例性部件110,例如中介層。在一些實施例中(未圖示),一或更多個開孔138可不包含打線接合。在此種實施例中,缺少打線接合在其中的開孔138可包含介電質材料。此種開孔138可部分或完全填充有介電質材料。
在上述處理的變化型中,在打線接合32***其中之前,未固
化的介電質材料140(例如,液體材料)可存在於開孔138中。以此種方式,在薄化低CTE元件119之後,可避免或可進一步促進或藉此協助介電質材料的沉積或填充。
在另一變化型中,開孔可不填充有介電質材料,但是取代
地,每一開孔的軸向尺寸可允許維持部分或實質上完全未由介電質材料填充。例如,每一開孔只有頂部與底部端部可被***。在此種情況中,最終的部件中的每一開孔內留下的空氣或空隙可作用為介電質,其具有甚至更低的介電常數,相較於可使用的固體聚合或無機介電質材料來說。
第19與20圖例示進一步的變化型,其中在低CTE元件119與
對應的處理中的元件157黏合之後,包含線跡54與接點46的再分佈層可形成於打線接合32的頂部上。完成的部件210(例如,中介層)例示在第20圖中。
第21-23圖例示上述處理的另一變化型。如同第21圖所見
的,具有打線接合32從其延伸的處理中的元件159係並置於低CTE元件119,使得兩者之間存在有間隙,其可容納介電質材料以流體形式流動,用於填充每一開孔138的目的。之後,如同第22圖所見的,介電質材料140可流入每一開孔中。如同第23圖進一步所見的,低CTE元件之後可薄化,且接點與導電塊(例如,焊料塊)可附加至其,以形成部件310,例如中介層。介電質填充材料的範例可為無機或聚合材料,如同上述。在一些情況中,該流動可為氣體形式,例如用於沉積介電質塗層於開孔內,例如聚對二甲苯等。
根據第21-23圖中所見的變化型來形成介電質填充層之處理可在任何或所有上述實施例中執行。
上述處理的進一步變化型係顯示於第24-28圖中,其中產生
的部件410(第28圖)為微電子元件,其可包含半導體晶片,打線接合132可延伸於其厚度方向中、通過半導體晶片,用於提供電性互連於部件410的第一表面144處所設置的接點46與部件的第二表面114(相對於第一表面)處所設置的接點16之間的目的。如同第28圖所見的,微電子元件可包含半導體區域419,打線接合132延伸通過半導體區域419,半導體區域通常由單晶半導體材料形成,但是在適當的情況下其可具有不同的結晶結構。複數個主動裝置421至少部分設置在半導體區域419中,其可為電晶體、二極體、或者可包含與利用半導體區域作為其部分功能結構的任何各種主動裝置。
如同第28圖中進一步所見的,水平與垂直的互連結構148可包含多個互連層,例如後段製程(BEOL)佈線結構或再分佈結構,互連結構形成於半導體區域419的頂部上。導電(例如,金屬的)連接器149可電性耦接於打線接合132與部件410的互連結構148,且可設置在打線接合與互連結構之間。
如同在上述實施例及其變化型中,介電質填充材料440可設置在圍繞每一打線接合的開孔438內。或者,介電填充材料可省略,或者介電質材料可僅***開孔438的頂部或底部端部或兩端部。在一些情況中,開孔438可僅利用介電質材料來作為襯裡但未填充,如同上述。
製造部件的處理(例如,第28圖中所見的)可包含黏合處理
中的元件465(第24圖)於具有複數個主動裝置已經形成在其中的微電子元件470(第25圖)。該處理可視為「經由中間」的處理,因為藉由打線接合132所形成的垂直互連係形成在半導體區域中的主動裝置的高溫製造完成之後,但是在互連結構148(第28圖)已經形成之前。如同第25圖中所見的,一組開孔438已經形成,從微電子元件470的後表面471朝向其前表面472延伸,每一開孔的尺寸係設計成容納單一打線接合或複數個打線接合以及相鄰的打線接合之間的間距。開孔可藉由任何數量的技術來形成,其可包含機械、化學或光學(例如,雷射燒蝕)的技術等。因此,開孔438部分延伸通過半導體區域419的厚度。載體443可附接至半導體區域的前表面472,同時開孔正形成。
第26圖為後續的製造階段,其中處理中的元件465黏合於微
電子元件470,且選擇性的介電質填充材料440可提供在開孔內。載體也可移除。
如第27圖所示,前表面開孔458可之後形成,從微電子元件
的前表面471延伸並且對準於打線接合132。介電質襯裡可然後形成於前表面開孔內,之後,導電材料可然後沉積至開孔中,以形成金屬連接器149,如同第28圖中所見的。在一些範例中,金屬連接器可藉由各種氣相沉積或
電鍍處理或其組合來形成。
在上面見到的每一實施例中,部件可包含實質長度的打線接
合,其中其圓柱軸部分可延伸數十至數百微米。在具體的範例中,每一打線接合的軸可具有50微米至一毫米的長度。
在一些範例中,根據本發明的實施例所製造的微電子元件
410可在晶粒堆疊中堆疊在彼此的頂部上,其中打線接合132與連接器149與互連結構148可作用為矽通孔(TSV)。在一範例中,以此方式製造的微電子元件410的表面114可佔據與原本的半導體晶片的表面相同的面積,且具有包圍該區域的周邊邊緣,其對應於其所製造自的原本的半導體晶片的邊緣。在此種範例中,部件410或已處理的微電子元件可稱為「晶片級封裝」或「CSP」。
在相關於第3至28圖所上述的任何或全部的實施例的變化型
中,取代形成打線接合32於金屬片42上,打線接合可形成於電路平板或微電子元件(例如,半導體晶片)的頂部上。在一具體實施例中,取代移除支撐打線接合的下方結構(例如,金屬片42、電路平板或半導體晶片),可允許電路平板或半導體晶片維持在微電子組件中,微電子組件包含中介層元件與下方的電路平板或半導體晶片。
在相關於第3至28圖所上述的任何或全部的實施例的變化型
中,一或更多個額外部件(其可為主動部件、被動部件、或其組合)可預先安裝在下方的結構上(例如,金屬片、微電子元件或電路平板),且此種額外部件可之後變成嵌入於完成的部件或中介層中的開孔內部的介電質填充內。在上述實施例的變化型中,在打線接合***其中之前,低CTE元件中
的開孔可延伸通過低CTE元件的整個厚度,使得在打線接合的軸向方向中沒有低CTE元件的材料在打線接合之上。在此種情況中,上述將低CTE元件薄化以從低CTE元件的頂部曝露開孔38(例如,第9圖所示的元件19的薄化)可省略。
將理解到,相關於本發明的一態樣、實施例、佈置或配置所
討論與所示的特徵可聯合使用於本發明的任何其他態樣、實施例、佈置或配置。例如,雖然一些圖式與其對應的敘述例示了垂直延伸的打線接合,但是將理解到,根據所示或所述的任何實施例,也可使用延伸在垂直方向以外的方向中之打線接合,例如其他圖式中所示的。
雖然本發明在此已經參照具體實施例來敘述,將瞭解到,這
些實施例僅是本發明的應用與原理的例示。因此,可瞭解到,可對例示的實施例做出各種修改,且藉由本應用,可設想出本文提供的實施例的組合與其他配置。可設想出進一步的補強,而未偏離本文所敘述的實施例中所界定之本發明的範圍與精神。
10‧‧‧微電子部件
12‧‧‧微電子元件
13‧‧‧面
16‧‧‧接點
19‧‧‧低CTE元件
20‧‧‧封裝基板
32‧‧‧打線接合
46‧‧‧接點
50‧‧‧電路平板
51‧‧‧接點
100‧‧‧微電子組件
114‧‧‧第二表面
144‧‧‧第一表面
Claims (20)
- 一種製造一部件的方法,包含:形成一結構,該結構包含複數個打線接合,每一打線接合延伸於一元件中的一或更多個開孔的一開孔內的一軸向方向中,且每一打線接合至少部分間隔於其所延伸的該開孔的一壁部,該元件實質包含具有一熱膨脹係數(CTE)小於10ppm/℃的一材料;該結構具有在該部件的一第一表面處的第一接點以及在該部件的一第二表面處的第二接點,該第二表面以一方向對立面向於該第一表面,該等第一接點為該等打線接合的第一端部,或者該等第一接點耦接至該等打線接合的第一端部,且該等第二接點電性耦接於該等打線接合。
- 如申請專利範圍第1項之方法,其中在該元件中的該等開孔未被該元件的任何部分覆蓋。
- 如申請專利範圍第1項之方法,其中形成該結構包含:提供一第一元件,該第一元件之複數個打線接合係向上延伸離開該第一元件;及將該等打線接合***至具有小於10ppm/℃的CTE的該元件中的一或更多個開孔中。
- 如申請專利範圍第1項之方法,另包含形成下述至少一者:電性耦接於該等打線接合與該等第一接點之間的一第一再分佈層,或電性耦接於該等打 線接合與該等第二接點之間的一第二再分佈層。
- 如申請專利範圍第1項之方法,其中形成該結構包含:形成該等打線接合,使得該等打線接合的第一端部形成於一第一再分佈層的金屬元件上,之後將每一打線接合***至該一或更多個開孔的一開孔中。
- 如申請專利範圍第1項之方法,其中形成該結構包含:將該複數個打線接合的個別打線接合***至該元件中的個別開孔中,使得每一打線接合藉由該元件的材料而彼此分隔。
- 如申請專利範圍第6項之方法,其中當該等個別的打線接合***於該等開孔中時,該等開孔為盲開孔(Blind Openings),且該方法另包含:在該***之後,減少該元件的一厚度,以提供接取(Access)給該等打線接合的端部使用。
- 如申請專利範圍第6項之方法,其中該***可包含:將該複數個打線接合的一些打線接合***該複數個開孔的同一開孔中。
- 如申請專利範圍第1項之方法,另包含:在接觸於該等打線接合的該等開孔內提供一電性絕緣材料。
- 如申請專利範圍第1項之方法,其中該元件包含複數個主動裝置,其中 該第一或第二接點的至少一些係電性耦接於該複數個主動裝置。
- 如申請專利範圍第10項之方法,其中該元件包含一單晶半導體區域(Monocrystalline semiconductor),至少一些該等主動裝置係至少部分設置於該單晶半導體區域內,且該等開孔至少部分延伸通過該單晶半導體區域。
- 一種部件,包含:複數個打線接合,每一打線接合延伸於一元件中的一或更多個開孔的一開孔內的一軸向方向中,該元件之一熱膨脹係數(CTE)小於10ppm/℃,且每一打線接合至少部分間隔於其所延伸的該開孔的一壁部;在該部件的一第一表面處的第一接點以及在該部件的一第二表面處的第二接點,該第二表面以一方向對立面向於該第一表面,該等第一接點為該等打線接合的第一端部,或者該等第一接點耦接至該等打線接合的第一端部,且該等第二接點電性耦接於該等打線接合。
- 如申請專利範圍第12項之部件,其中該等第一接點或該等第二接點的至少一者係透過一再分佈層而電性耦接於該等打線接合,該再分佈層在該等打線接合之上且在該元件的一表面之上,該元件的該表面界定橫越該等開孔的該軸向方向之一平面。
- 如申請專利範圍第12項之部件,其中該複數個打線接合的個別打線接合係設置在該元件中的個別開孔內,使得每一打線接合藉由該元件的材料而 彼此分隔。
- 如申請專利範圍第12項之部件,其中該複數個打線接合的一些打線接合係設置在該複數個開孔的同一開孔中。
- 如申請專利範圍第12項之部件,另包含在接觸於該等打線接合的該等開孔內的一電性絕緣材料。
- 如申請專利範圍第12項之部件,其中該元件包含複數個主動裝置,其中該等第一與第二接點係電性耦接於彼此,並且電性耦接於該複數個主動裝置的至少一些主動裝置。
- 如申請專利範圍第17項之部件,其中該元件包含一單晶半導體區域,至少一些該等主動裝置係至少部分設置於該單晶半導體區域內,且該等開孔至少部分延伸通過該單晶半導體區域。
- 如申請專利範圍第12項之部件,其中該等第一接點與該等第二接點距離該等打線接合,係小於50微米的一軸向距離內。
- 如申請專利範圍第17項之部件,其中該等打線接合僅部分延伸通過該元件的一厚度;另包含導電連接器,該等導電連接器從該等打線接合延伸於一軸向方向中、至少部分通過該元件的該厚度的剩餘部分,該等連接器由 沉積的導電材料形成。
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2014
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2017
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI791881B (zh) * | 2019-08-16 | 2023-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其組合式基板與製法 |
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US9646917B2 (en) | 2017-05-09 |
WO2015184153A1 (en) | 2015-12-03 |
US20170243761A1 (en) | 2017-08-24 |
US10032647B2 (en) | 2018-07-24 |
US20180366392A1 (en) | 2018-12-20 |
US20150348873A1 (en) | 2015-12-03 |
US10475726B2 (en) | 2019-11-12 |
TWI596680B (zh) | 2017-08-21 |
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