TW200302685A - Circuit component built-in module and method of manufacturing the same - Google Patents

Circuit component built-in module and method of manufacturing the same Download PDF

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Publication number
TW200302685A
TW200302685A TW92100863A TW92100863A TW200302685A TW 200302685 A TW200302685 A TW 200302685A TW 92100863 A TW92100863 A TW 92100863A TW 92100863 A TW92100863 A TW 92100863A TW 200302685 A TW200302685 A TW 200302685A
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TW
Taiwan
Prior art keywords
module
built
circuit element
electrically insulating
insulating substrate
Prior art date
Application number
TW92100863A
Other languages
English (en)
Inventor
Satoru Yuhaku
Toshiyuki Asahi
Shingo Komatsu
Kazuo Ohtani
Yasuhiro Sugaya
Kazuo Otani
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200302685A publication Critical patent/TW200302685A/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2924/30107—Inductance

Description

200302685 玖、發明說明 【發明所屬之技術領域】 本發明係關於電路元件內藏模組及其製造方法，詳言 之，係關於藉由內藏半導體晶片於電氣絕緣性基板來謀求 薄型化，藉由形成多層積層模組，以實現高密度構裝化的 電路元件內藏模組及其製造方法。 【先前技術】 對應近年來資訊產業顯著發展所伴隨的各種電子資訊 機器之高性能化、小型化，要求使用於此種電子資訊機器 的電路元件之高密度化、高機能化、及短配線化，爲實現 此等特性，對內藏電路元件或電子元件之模組，亦即電路 元件內藏模組極薄化的要求越來越強烈。 爲謀求電路元件之極薄化，由於將電路元件構裝於基 板表層之技術有其限度，因此提出了一種藉由在基板設置 凹部，於其中配置半導體晶片使基板薄型化以謀求電路元 件之高密度構裝化的技術（日本專利特開平5 — 259372號公 報、特開平Π — 103147號公報、特開平11 一 163249號公報 )。該技術，係將半導體晶片等主動元件構裝於基板後，爲 保護半導體晶片與基板之連接部及半導體晶片，塗布樹脂 於前述凹部加以密封。 又，亦提出了一種藉由使電路基板多層化來謀求高密 度構裝化的技術。習知之玻璃一環氧基板（在玻璃纖維布含 浸環氧樹脂之基板）等以鑽頭形成貫通孔構造的技術，由於 對高密度化之要求有其限度，故產生LSI(large scale 200302685 integrated circuit)間或元件間之配線圖案不能以最短距離連 接的問題。然而，爲解決此種問題，提出了一種內通孔 (inner via hole)連接技術（特開昭63 — 47991號公報、特開平 6 - 268345號公報）。如前述之內通孔連接技術，僅能在特 定之積層層間連接，半導體晶片之構裝性亦非常優異。 再者，在特開平11 - 220262號公報中，作爲電路元件 內藏模組之一例，提出了一種在具備局熱傳導性之電路基 板中內藏半導體晶片，將前述電路基板積層爲多層之高散 熱性能的模組。 作爲其他之公知例，亦有ICEP Proceeding Stacking Semiconductor Packages, 2001，P16—21。使用圖 12A 及圖 12B說明其一例。將玻璃一環氧基板1002(圖12A，構裝有 具可撓性之50〜ΙΟΟμηι半導體晶片1001)積層來形成謀求高 密度構裝化的多層積層記憶體封裝體1〇〇3(圖12Β)。圖12Α 中，1004係半導體晶片1001之突起電極，1005係玻璃一環 氧基板1002之表面電極，1006係密封樹脂，1007係玻璃-環氧基板，1008係導孔（via)，1009係配線，1010係凹部空 間。 然而，在電路基板中設置凹部空間1010,於其中配置 半導體晶片的技術，無論使用陶瓷基板、或樹脂系列基板 之任一者，其在基板加工出凹部之製程皆需相當成本，並 且有生產良率低的問題。又，在玻璃-環氧基板使用密封 樹脂配置半導體晶片之技術中，雖使用貫通孔（through hole) 電鑛通孔（via hole)連接技術，但是由於基板所使用之材料 200302685 通常係玻璃-環氧樹脂等樹脂，故基板本身之熱傳導度低 ，招致模組之散熱性能不足，而影響可靠性。 再者，將電路基板積層爲多層之電路元件內藏模組中 ，若係將複數個半導體晶片積層於縱方向之形態時，模組 全體之厚度過大，而使高密度構裝化有其限度。SRAM (static random access memory)，快閃記憶體（flash memory)等 ，將種類相異之記憶體半導體晶片積層於縱方向的記憶體 模組，爲謀求薄型化，對半導體晶片厚度有其限制，模組 全體之積層數，最多僅爲3〜4層而致高密度構裝化不充分 〇 另一方面，將半導體晶片在晶圓上磨削後，切割而構 裝於基板的技術雖多有開發，但由於此種薄型半導體晶片 之操作性不佳，生產效率（作爲對基板之構裝性的指標）低。 又，如圖12A〜B所示，積層了薄型半導體晶片之多層 積層記憶體封裝體1003中，基板1002之厚度爲決定性因 素，欲在特定模組厚度範圍內設置例如8層程度之堆疊 (stack)是非常困難。又，該多層積層模組，一般係使用以電 鍍構成之導孔作爲層間連接方法，爲提高層間之黏著性需 要複雜之製程。並且，要將半導體晶片內藏於基板1002非 常困難，而會在半導體晶片周邊產生空隙，例如，在吸濕 時之熔焊（reflow)製程有水蒸氣***之危險性等，而降低所 得模組的可靠性。 此種薄型多層積層模組，爲提高基板1002之強度，例 如使用玻璃-環氧基板時，在基板1002內藏半導體晶片非 200302685 常困難，例如圖13所示，需要將L(電感）、C(電容）、R(電 阻）等晶片元件1104構裝於模組最表層，在電路基板之構造 設計上（包含以高密度構裝化爲目標之電路元件的最適當配 置）受限制。 【發明內容】 本發明之目的在於，解決習知技術之如上述問題點， 提供厚度薄，且使用於高性能化、小型化之各種電子資訊 機器之高密度構裝化的電路元件內藏模組及其製造方法。 爲達成前述目的，本發明之電路元件內藏模組，包含 由含無機塡料與熱硬化性樹脂之混合物所組成的電氣絕緣 性基板，形成於電氣絕緣性基板之至少主面的複數個配線 圖案，內藏於電氣絕緣性基板、且與配線圖案電氣連接的 半導體晶片，以及貫通電氣絕緣性基板以電氣連接複數個 配線圖案所形成的內導孔，其特徵在於： 前述半導體晶片之厚度爲30μηι〜ΙΟΟμιη，且非配線面 爲磨削面， 前述電路元件內藏模組之厚度在80μηι〜200μπι之範圍。 其次，本發明之電路元件內藏模組之製造方法中，該 電路元件內藏模組，包含由含無機塡料與熱硬化性樹脂之 混合物所組成的電氣絕緣性基板，形成於電氣絕緣性基板 之至少主面的複數個配線圖案，內藏於電氣絕緣性基板、 且與配線圖案電氣連接的半導體晶片，以及貫通電氣絕緣 性基板以電氣連接複數個配線圖案所形成的內導孔，其特 徵在於： 10 200302685 準備板狀體的製程，該板狀體，係在前述電氣絕緣性 基板開設貫通孔，於其中塡充有熱硬化性之導電性物質； 將半導體晶片構裝於脫膜載體上所形成之配線圖案的 製程； 將前述半導體晶片之非配線面磨削成30μπΐ〜ΙΟΟμπί之 厚度的製程； 在形成前述脫膜載體之配線圖案的面，以前述配線圖 案與前述貫通孔中塡充有導電性物質之部分一致的方式， 將前述板狀體對準位置而重疊，一致於藉由加壓使前述半 導體晶片埋設於前述板狀體中的製程； 藉由加熱前述埋設體，使前述混合物與前述導電性物 質同時硬化，而獲得厚度80μηι〜200μιη之電路元件內藏模 組的製程；以及 剝離前述脫膜載體的製程。 本發明之電路元件內藏模組，其特徵爲：將半導體晶 片構裝於脫膜載體上所形成之配線圖案，將半導體晶片埋 入電氣絕緣性基板內，藉由貫通前述電氣絕緣性基板所形 成之內導孔，將從前述半導體晶片拉出之配線圖案與前述 內導孔作電氣連接。據此，能實現電路元件內藏模組之薄 型化，獲得高性能化且小型化之高密度構裝化的多層積層 模組。 本發明方法，係在構裝半導體晶片後，將前述半導體 晶片磨削加工成30μηι〜ΙΟΟμηι之厚度。若具有前述範圍之 厚度，則適合於取得薄型化且小型化之多層積層模組。又 11 200302685 ，半導體晶片之非配線面，即使磨削成前述範圍之厚度， 亦沒有性能上之問題。 又，前述電路元件內藏模組之厚度只要是在80〜 200μηι的話，就適合於薄型化且小型化。 前述半導體晶片，最好是晶圓級晶片尺寸封裝（CSP = chip scale package)半導體。因爲除薄型化且小型化外，亦 能保證品質之故。 將前述半導體晶片埋設於板狀體中之製程，最好是能 使用2片形成有前述配線圖案之脫膜載體，挾住前述板狀 體對準位置而重疊、加熱，將半導體晶片以其上面彼此相 對之狀態沿厚度方向埋設2個於前述板狀體中。如此，不 致產生無謂之空間，適於薄型化且小型化之故。 前述配線圖案，亦最好進一步形成於前述電氣絕緣性 基板之其他主面，在前述電氣絕緣性基板，以其上面彼此 對向之狀態沿前述電氣絕緣性基板厚度方向內藏2個前述 半導體晶片，前述2個半導體晶片之一方與前述電氣絕緣 性基板之主面形成之配線圖案電氣連接，另一方與前述電 氣絕緣性基板之其他主面形成之配線圖案電氣連接。其理 由，亦係因此方法不致產生無謂之空間，適於薄型化且小 型化之故。 形成於前述電氣絕緣性基板之至少主面的配線圖案， 最好是積層於前述電氣絕緣性基板之多層配線基板表層之 配線圖案的一部分。藉由多層配線基板之使用，不但能高 積體化及高性能化，且能亦增加強度，提高操作性。 12 200302685 又，最好是能進一步於前述電氣絕緣性基板內藏被動 元件，將前述被動元件與前述複數之配線圖案中之任一個 作電氣連接。若同時內藏被動元件，就能高性能化。前述 被動元件，係例如從電感、電容及電阻（以下，亦稱爲LCR) 所選出之至少一項。 又，最好是能將前述半導體晶片與前述配線圖案之連 接部以底塡（underfill)樹脂，電氣絕緣性薄膜（NCF : Non Conductive Film)，或含導電粒子之異方性導電膜（ACF : Anisotropic Conductive Film)來補強。此處，所謂底塡 (underfUl)樹脂係指密封樹脂，例如由無機塡料與環氧樹脂 構成，以當作液狀樹脂組成物注入的方法使用。 又，亦能將前述電路元件內藏模組積層4〜8層來形成 多層積層模組。此時，最好是能將相鄰電路元件內藏模組 藉由前述內導孔作電氣連接。如此構成就能積層任意層數 〇 又，最好是能在前述相鄰電路元件內藏模組間，配置 具備內導孔之電氣絕緣性基板，前述電氣絕緣性基板，與 構成前述電路元件內藏模組之電氣絕緣性基板係相同組成 物。若係相同組成物，即使形成多層積層模組，能將各層 間之物理特性保持爲相同。 又，將前述電路元件內藏模組積層4〜8層來形成多層 積層模組時，亦可在相鄰電路元件內藏模組間，配置具備 內導孔之電氣絕緣性基板，並在前述電氣絕緣性基板上配 置薄膜狀之被動元件。 13 200302685 前述脫膜載體，以金屬片或樹脂片較佳。 又，前述樹脂片，最好是選自聚醯亞胺（polyimido)、聚 對苯二甲酸乙醇二酯（polyethylene terephthalate)、聚對萘二 甲酸乙醇二酯（polyethylene naphthalate)、聚苯硫 (polyphenylene sulfide)、聚乙烯（polyethylene)、聚丙烯 (polypropyrene)、及氟樹脂中之至少一種樹脂薄膜。脫膜載 體之較佳厚度，係30〜ΙΟΟμιη。氟樹脂，例如係聚四氟乙 烯（PTFE)、四氟乙烯一全氟烷基乙烯基醚共聚體（PFA)、四 氟乙烯-六氟丙烯共聚體（FEP)、聚氟乙烯、聚雙氟亞乙烯 等。 前述金屬片亦可以是銅箔。又，前述脫膜載體爲銅箔 ，金屬配線圖案爲銅箔，前述脫膜載體與前述配線圖案間 之剝離層以鍍鉻層來形成亦可。 又’若要在脫膜載體使用具有30μιη以上厚度的金屬箔 ’例如銅箔等時，亦可透過金屬電鑛層，例如，Cr電鍍層 、Ni電鑛層來形成銅箔配線圖案。配線圖案，例如，可在 將銅箔黏著於脫膜載體後，經過微影製程及蝕刻製程來形 成。如此’與使用樹脂薄膜於載體之情形相較，能使載體 片剝離後之銅箔表面更潔淨。亦即，由於係直接露出電解 鍍界面’因此能能使未被氧化之具光澤之未處理銅箔界面 更爲露出。 前述半導體晶片及前述被動元件，最好是能在埋入第 一板狀體之前先作導通檢查。如此，能提高製品良率。當 然，在電路元件內藏模組製造後進行檢查亦佳。 14 200302685 【實施方式】 以下，參照圖式說明本發明之實施形態。 實施形態1 圖1，係本實施形態之電路元件內藏模組112的截面圖 。電路兀件內藏模組112，係半導體晶片103內藏於電氣絕 緣性基板101之構成。102b與102c，係形成於電氣絕緣性 基板101主面之配線圖案，102a，係形成於電氣絕緣性基 板101其他主面之配線圖案。各配線圖案係由銅箔或導電 性樹脂組成物所形成。配線圖案l〇2a與102b，係透過貫通 電氣絕緣性基板101而形成之內導孔104作電氣連接。半 導體晶片103，係透過凸塊105與配線圖案102c作電氣連 接。半導體晶片103與配線圖案102c之連接部係以電氣絕 緣性薄片106加以密封、補強。前述連接部，除電氣絕緣 性薄片106外，亦可使用底塡（underfill)材料等之密封樹脂 、電氣絕緣性薄膜（NCF : Non Conductive Film)、或含導電 粒子之異方性導電膜（ACF: Anisotropic Conductive Film)來 加以補強。 電路元件內藏模組112內之半導體晶片103厚度，需 要30〜ΙΟΟμηι，較佳者爲30〜50μπι。若超過ΙΟΟμιη即無法 謀求電路元件內藏模組之薄型化，在作爲多層積層模組時 或許不能實現充分之高密度構裝化。又，電路元件內藏模 組112之厚度爲80〜200μιη。 本實施形態中，除主動元件，亦即，除電晶體、 IC(integrated circuit)、LSI(large scale integrated circuit)等半 15 200302685 導體晶片以外，亦可將被動元件，亦即，具有1005、0603 型之各種L(電感）、C(電容）、R(電阻）機能之晶片元件、表 面彈性波（SAW)元件、或以印刷形成之電容，具有電阻機能 之薄膜狀元件，連接於配線圖案l〇2c，而內藏於電路元件 內藏模組Π2。 電氣絕緣性基板101，係由含無機塡料與熱硬化性樹脂 之混合物組成。無機塡料，例如，可使用A1203、MgO、BN 、AIN、Si02等。又，熱硬化性樹脂，可使用環氧樹脂、酚 醛樹脂、氰酸酯（cyanate)樹脂、或聚苯醚樹脂。又，環氧樹 脂因耐熱性高，故特別適合。 混合物中之無機塡料含有量，以70〜95重量％較佳。 又，爲提高電氣絕緣性基板之熱傳導性等，最好是能將無 機塡料塡充成高密度。例如，爲降低基板之介電率，使用 SiOJ二氧化矽塡料），使其含有量爲80重量％以上，熱傳導 度即成爲IW/m · K以上。又，爲提高基板之熱傳導性，無 機塡料使用A1N(氮化鋁）塡料，使其含有量爲95重量％，熱 傳導度即約爲l〇W/m · K。又，使Al2〇3爲88重量％，熱傳 導度即約爲3〜4W/m · K。 無機塡料之平均粒子直徑，以0.1〜ΙΟΟμηι較佳。又， 在混合物，除無機塡料外，視必要亦可含有分散劑、染色 劑、結合劑、脫膜劑等。 內導孔104，係由導電性樹脂組成物之硬化物構成。該 導電性樹脂組成物，宜由金屬粒子85〜92重量％與熱硬化 性樹脂8〜15重量％之混合物組成。金屬粒子，例如，能使 16 200302685 用導電性高之金、銀、銅、鎳等或此等金屬之混合物。其 中，銅由於原子移動少較爲適合。熱硬化性樹脂，能使用 環氧樹脂、酚醛樹脂、氰酸酯樹脂、或聚苯醚樹脂。其中 ，環氧樹脂因耐熱性高，故較適合。 凸塊105，雖可使用電鍍凸塊，柱凸塊之任一種凸塊， 但是站在要提高與配線圖案102之連接可靠性的觀點，較 佳者爲柱凸塊。 依該構成，由於係將30〜ΙΟΟμηι之半導體晶片內藏於 電氣絕緣性基板，且將模組之配線圖案藉由塡充於基板貫 通孔之內導孔連接，故能使電路元件內藏模組充分薄型化 。又，半導體晶片因內藏於電氣絕緣性基板而與外氣阻隔 ，故能防止濕氣所造成之劣化，提高電路元件內藏模組之 可靠性。並且，再配線或品質檢查亦容易，可減輕電路基 板構造設計上的限制，製造多樣構成之LGA(land grid array)電極。 以下，參照圖2A〜圖2E說明本實施形態之電路元件 內藏模組112之製造方法的一例。 首先，如圖2A所示，使用形成有配線圖案202c之脫 膜載體207，將厚度200〜400μιη之半導體晶片203，透過 凸塊205在配線圖案202c上作覆晶構裝。脫膜載體207， 可使用聚酯薄膜，聚對苯二甲酸乙二酯、對聚苯硫、氟樹 脂等之有機樹脂薄膜，亦能使用銅箔或鋁箔等各種金屬箔 。又，在脫膜載體207，亦可藉由塗布適當之有機膜，來形 成剝離層。 17 200302685 配線圖案202c，能在脫膜載體207表面電解鑛厚度9〜 35μιη程度之銅來形成。又，亦能在脫膜載體207表面黏著 銅箔後，經微影製程與蝕刻製程來形成。配線圖案202c， 爲提高與複合片201之黏著性，最好是能在其表面析出微 細金屬粒子等而使之粗糙。配線圖案202c，亦可係無防鏽 層之未處理Cu箔，或爲提高黏著性或耐氧化性，亦可在其 表面施加偶合處理。又，配線圖案202c，除銅以外，可電 解鍍錫、鋅、鎳、金等來形成，亦可在其表面施加錫-鉛 合金所組成之焊料電鍍或錫-鉍系列等之無給之焊料電鑛 〇 本實施形態中，進行覆晶構裝時，於半導體晶片203 與配線圖案202c之間設置電氣絕緣性薄片206,來補強半 導體晶片203與配線圖案202c之連接部。然後，進行加熱 、加壓，如圖2B所示，透過凸塊205完成半導體晶片203 與配線圖案202c之連接。替代凸塊205，亦可使用導電性 黏著劑。該導電性黏著劑，例如，能使用將金、銀、銅、 或銀-鈀合金等，與熱硬化性樹脂混合攪拌者。替代導電 性黏著劑，亦可形成金凸塊（以金打線法所製造）或焊料凸塊 於半導體晶片203，藉由熱處理而溶解此等凸塊來連接。亦 可倂用導電性黏著劑與焊料凸塊。 替代使用電氣絕緣性薄片206，亦可將底塡（underHll) 材料等之密封樹脂注入半導體晶片203與配線圖案202c之 間。若以密封樹脂補強連接部，就能以密封樹脂全體吸收 由半導體晶片203與複合片201之熱膨脹率差所產生的應 18 200302685 力，而能有效地抑制應力集中，當將半導體晶片203埋設 於複合片201中時，亦能防止半導體晶片203與配線圖案 202c之間產生間隙。除密封樹脂外，亦能視需要使用電氣 絕緣性薄膜（NCF)，或含導電粒子之異方性導電膜（ACF)。 其次，如圖2C所示，將半導體晶片203，使用磨機（以 鑽石磨粒構成表層）等磨削至圖中之磨削線，加工爲厚度30 〜ΙΟΟμηι，較佳者爲30〜50μηι。此處，雖使用磨削法，但 是亦可使用其他拋光等之磨削法，放電加工法來加工。不 過，以高速加工時，最好是能將脫膜載體固定於模具治具 等，以磨削法進行。依此方法，能容易地將厚度爲200〜 400μηι程度之半導體晶片，毫無損傷地以高速加工至50〜 ΙΟΟμηι 程度。 接著，如圖2D所示，將構裝半導體晶片203之脫膜載 體207，與具有貫通孔204之複合片201，以貫通孔204之 位置或形狀不產生偏差之方式，細心對準位置而加以重疊 。複合片201，係將無機塡料與未硬化狀態之熱硬化性樹脂 混合而組成糊狀混合物，藉由將該混合物成形爲一定厚度 之板狀體來加以製造。又，在貫通孔204中，塡充含金屬 粒子與未硬化之熱硬化性樹脂的導電性樹脂組成物。 其次，進行加壓，如圖2Ε所示，將半導體晶片203埋 設於複合片201中後，以使複合片201之混合物與貫通孔 204中之導電性樹脂硬化之溫度以上的溫度（例如150〜260 °C)進行加熱。藉此，複合片201即形成爲電氣絕緣性基板 201a，貫通孔204則形成爲內導孔204a。又，此時，配線 19 200302685 圖案202a、202b與電氣絕緣性基板201a即會強固地黏著。 又，加熱時藉由10〜20kg/cm2;i加壓，即能提高所得之電路 元件內藏模組212配線圖案之轉印性或導孔連接之可靠性 〇 其後，如圖2F所示，以機械方式將脫膜載體207從電 氣絕緣性基板201a剝離，使配線圖案202b、202c轉印至電 氣絕緣性基板201a上而獲得電路元件內藏模組212。 又，之後，可將光阻印刷於電路元件內藏模組212之 主面及其他主面，使配線圖案202a、202b固定於電路元件 內藏模組212，或是藉由將底塡（underfill)樹脂注入配線圖 案部，或將未硬化樹脂片積層於電路元件內藏模組212，來 密封配線圖案202a、202b亦可。 依此製造方法，由於能將構裝於脫膜載體上之半導體 晶片加工成薄型，故能安定地製造厚度80〜200μηι之薄型 電路元件內藏模組。 又，由於電氣絕緣性基板係使用無機塡料與熱硬化性 樹脂之混合物’故不需要如陶瓷基板以局溫燒成’使基板 之製造容易。 再者，由於在電氣絕緣性基板中含有無機塡料，故在 半導體晶片所發生之熱能迅速散至外部，而提高電路元件 內藏模組之可靠性。並且，藉由變更該無機塡料之種類或 基板中之含有率，能改變基板之線膨脹係數、熱傳導度、 介電率等，而容易製造具有多樣特性之電路元件內藏模組 。例如，藉由使基板之線膨脹係數接近半導體晶片之線膨 200302685 脹係數，即能有效防止溫度變化所引起之裂痕發生等，又 ，藉由降低基板之介電率，能製造介電損失小之高頻電路 用模組。 又再者，裸半導體晶片，一般來說，由於需在構裝於 基板前進行品質檢查，故操作性低，於成本面有其限制， 但依此製造方法，由於能將半導體晶片內藏於基板之狀態 視爲初期封裝形態，來檢查半導體晶片之品質，因此作爲 模組，能解決所謂KGD(known good die)問題。此處，所謂 KGD，係指進行含加熱狀態之導通檢查等的檢查（老化檢查) ，而僅將合格品作爲封裝品而言。 實施形態2 圖3A，係本實施形態之電路元件內藏模組312的截面 圖。電路元件內藏模組312，係將半導體晶片303，以晶片 厚度非常薄之晶圓級晶片尺寸封裝體（晶圓級CSP)之狀態內 藏於電氣絕緣性基板301的構成。另外，多層基板303a亦 一體化裝配。302a，係形成於電氣絕緣性基板301主面之 配線圖案，302b，係形成於電氣絕緣性基板301其他主面 之配線圖案。配線圖案302a與302b，係透過貫通電氣絕緣 性基板301而形成之內導孔304作電氣連接。 圖3B，係顯示將晶圓級CSP303a，構裝於再配線用之 多層基板306的構成例。電路元件內藏模組312，係透過金 屬凸塊305連接於多層基板306。 半導體晶片303之厚度，需爲30〜ΙΟΟμηι，較佳者爲 30〜50μηι。若超過ΙΟΟμηι則無法使電路元件內藏模組312 21 200302685 薄型化，當要實現高密度構裝化時或許會發生障礙。又， 電路元件內藏模組312之厚度爲300〜600μηι。 依圖3Α所示之構成，若使用銷數少之晶圓級CSP303a 時，由於係覆晶構裝晶圓級CSP303a，同時形成含再配線之 配線圖案，因此不需要再配線用之多層基板，能省去該部 分之空間，使模組更有效地薄型化。另一方面，如圖3B所 示，若需要再配線用之多層基板306時，能明顯地顯現使 電路元件內藏模組312薄型化之效果，對高密度構裝化有 非常大的幫助。 又，根據此構成，由於係將半導體晶片303以CSP之 狀態，即保證品質之狀態，內藏於電路元件內藏模組312， 故亦能根本解決KGD問題。 圖3C與圖3D中，顯示了將其他半導體晶片307構裝 、積層於多層基板306或電氣絕緣性基板301的例。 如此，若使形成於電氣絕緣性基板301之至少主面的 配線圖案，與多層基板306第1層之配線圖案一致之構成 的話，即能擴大電路元件內藏模組312之適用範圍。例如 ，將具有CPU機能之半導體晶片303加工成薄型，內藏於 電氣絕緣性基板後，構裝、積層具有記憶機能之半導體封 裝體307(記憶體封裝體），即能構成薄型且省空間之機能組 〇 以下，參照圖4A〜圖4C，說明本實施形態之電路元件 內藏模組312的製造方法之一例。 首先，如圖4A所示，將晶圓級CSP403a，以回流處理 22 200302685 覆晶構裝於多層基板406上，使用磨機等磨削至圖中之磨 削線，加工成厚度30〜ΙΟΟμιη，較佳者爲30〜50μιη。此處 ，雖使用磨削法，但是亦可使用其他拋光等之磨削法、放 電加工法來加工。然不過，以高速加工時，最好是能將多 層基板306固定於模具治具等，以磨削法進行。依此方法 ，能將厚度爲200〜400μιη程度之半導體晶片，毫無損傷地 以高速容易加工爲50〜ΙΟΟμιη程度。 接著，如圖4Β所示，將已構裝晶圓級CSP403a之多層 基板406與複合片401重疊、加壓，使晶圓級CSP403a埋 設於複合片401中。其次，以使複合片401之混合物硬化 之溫度以上的溫度（例如150〜260°C)進行加熱。藉此，複 合片401，即形成爲電氣絕緣性基板401 a(圖4C)。412係電 路元件內藏模組。 之後，如圖4C所示，亦能將記憶體封裝407構裝於多 層基板406而加以積層。依此製造方法，即使將記憶體封 裝407予以積層，亦能安定地製造全厚度T爲1〜2mm之 薄型電路元件內藏模組412。又，由於係使用晶圓級CSP 藉由回流處理構裝的多層基板，故能提高生產效率。 實施形態3 圖5，係本實施形態之電路元件內藏模組512的截面圖 。對應實施形態1之電路元件內藏模組112的構件，係由 施加相同處理之相同種類的材料構成。電路元件內藏模組 512，係以半導體晶片503a與503b其上面彼此相對之狀態 ，內藏於電氣絕緣性基板501的構成。502b與502c，係形 23 200302685 成於電氣絕緣性基板501主面的配線圖案，502a與502d， 係形成於電氣絕緣性基板501其他主面的配線圖案。配線 圖案502a與502b，係透過貫通電氣絕緣性基板501而形成 之內導孔504作電氣連接。半導體晶片503a與503b，係透 過凸塊505，分別與配線圖案502d、配線圖案502c作電氣 連接。在半導體晶片503a與503b之間，形成由無機塡料與 熱硬化性樹脂所組成之厚度50〜ΙΟΟμιη的緩衝層507。506 係電氣絕緣性薄片之層。 依此構成，能將半導體晶片更高密度構裝於電路元件 內藏模組。藉由積層電路元件內藏模組而構成多層積層模 組，此效果將更爲顯著。 就本實施形態之電路元件內藏模組512的製造方法之 一例，參照圖6Α〜Ε說明如下。 首先，如圖6Α所示，使用脫膜載體607a(預先在配線 圖案602b、602c上，以電解鑛形成N!及Au層），將厚度 200〜400μιη之半導體晶片603a，透過凸塊607a覆晶構裝 於配線圖案602c上。其次，將半導體晶片603a，使用磨機 等磨削至圖中之磨削線，加工成厚度30〜ΙΟΟμιη，較佳者 爲 30〜50μιη。 其次，如圖6Β所示，在脫膜載體607a上之配線圖案 602b，構裝0603型之晶片電容603c。以底塡材料等之密封 樹脂補強半導體晶片603a與配線圖案602c之連接部時，若 設與晶片電容603c之相隔距離爲0.5mm以內來覆晶構裝半 導體晶片603a時，由於密封樹脂會突出約0.5mm程度而造 24 200302685 成妨礙，因此，最好是能取代密封樹脂，使用與半導體晶 片603a之占有面積大致相同面積的電氣絕緣性薄膜（NCF) 〇 其次，如圖6C所示，將具有貫通孔604之複合片601 ，構裝了半導體晶片603a與晶片電容603c之脫膜載體 607a，及構裝了半導體晶片603b之脫膜載體607b，以貫通 孔604之位置或形狀不產生偏差之方式，仔細對準位置加 以重疊。605a係脫膜載體607a上之凸塊。 其次，進行加壓，如圖6D所示，將半導體晶片603a、 6〇3b埋設於複合片601中後，以使複合片601之混合物與 貫通孔604中之導電性樹脂硬化之溫度以上的溫度（例如 150〜260°C)進行加熱。藉此，複合片601即形成爲電氣絕 緣性基板601a，貫通孔604形成爲內導孔604a。 之後，如圖6E所示，以機械方式將脫膜載體607a、 607b分別從電氣絕緣性基板601a剝離，將配線圖案602a、 602b轉印至電氣絕緣性基板601a上而獲得電路元件內藏模 組612。此處，係將半導體晶片沿電氣絕緣性基板601a厚 度方向內藏2個而使單體模組相對地變厚，因此脫膜載體 之剝離容易。 依此製造方法，由於第二板狀體（電氣絕緣性基板 601a)含有無機塡料與熱硬化性樹脂成分，不會使半導體晶 片或被動元件損傷，因此能製造內藏半導體晶片與被動元 件之模組。因此，亦能將例如0603型之晶片電容等大容積 之被動元件或薄膜狀之被動元件內藏於模組。依此製造方 25 200302685 法，由於能使半導體晶片與被動元件接近而配置等，故能 解除電路基板之構造設計上（包含電路元件之最適當配置）的 限制。 實施形態4 圖7B，係本實施形態之多層積層模組712的截面圖。 多層積層模組712,係將實施形態1之電路元件內藏模組 112積層多層而構成。 就本實施形態之多層積層模組712的製造方法之一例 ，參照圖7A—B說明。 首先，除了使加熱溫度爲100〜130°C之範圍，將複合 片701之混合物與貫通孔704中之導電性樹脂組成物以半 硬化或部分硬化之狀態（B階層狀態）加以保持外，其餘部分 以和實施形態1相同之方式來製造電路元件內藏模組701a 〜701d(圖 7A)。 其次，一邊控制壓力一邊將各電路元件內藏模組予以 積層，形成4層構造之多層積層模組712(圖7B)。圖7A- B 中，702a〜702b係形成於內導孔704兩表面之配線，703a 〜703d係半導體晶片，705係形成於半導體晶片表面之凸 塊，707a、707b係脫膜載體。 又，多層積層模組712，既可依順序積層，亦可總括積 層。總括積層時，因省略轉印配線圖案之製程等，故能使 製程簡單化。 根據本實施形態，例如，構成4層時，能獲得厚度400 〜600μιη之薄型多層積層模組。 26 200302685 實施形態5 圖9B，係本實施形態之多層積層模組813的截面圖。 多層積層模組813，係將實施形態2之電路元件內藏模 組512，以在相鄰電路元件內藏模組間配設樹脂片811之狀 態積層多層而構成。 依此構成，能使內藏於電路元件內藏模組之半導體晶 片端子的再配線部沿厚度方向2層化來構成，能使配線圖 案立體交叉，而提高電路基板之構造設計上的自由度。例 如，若係構成8層之多層積層模組，則成爲厚度1mm程度 之薄型，而能擴大適用範圍。例如，在構裝於主基板之狀 態能獲得全部厚度爲1.5mm以下的多層積層模組。 就本實施形態之多層積層模組813的製造方法之一例 ，參照圖8A - D及圖9A— B說明如下。 首先，除了使加熱溫度爲100〜130°C之範圍，將複合 片801之混合物與貫通孔804中之導電性樹脂組成物以半 硬化或部分硬化之狀態（B階層狀態）加以保持外，其餘部分 以和實施形態2相同之方式來製造電路元件內藏模組810。 其次，如圖8A所示，以機械方式將電路元件內藏模組 810單面之脫膜載體807a剝離。803a、803b係半導體晶片 ，807b係裏面之脫膜載體。 其次，如圖8B所示，將具有內導孔804b之樹脂片 811(B階層狀態）配置於相鄰電路元件內藏模組810a、810b 間，並從剝離電路元件內藏模組之脫膜載體的黏著面側仔 細對準位置加重疊。 27 200302685 其次，進行加壓，而成爲如圖8C所示之積層狀態後， 以使複合片801、樹脂片811、與貫通孔804中之熱硬化性 樹脂硬化之溫度以上的溫度（例如150〜260°C )來加熱積層 物。此處，亦可抑制加熱溫度於130°C程度而維持B階層 狀態。樹脂片811之材料，只要是能成爲B階層狀態者即 無特別限定，但是宜使用與使用於複合片801之混合物相 同組成的混合物，較佳者爲無機塡料之含有量與使用於複 合片801之混合物相等的混合物。 然後，如圖8D所示，以機械方式剝離多層積層模組 812上下面之脫膜載體807a、807b。 之後，如圖9A所示，將樹脂片811b(B階層狀態）配置 於相鄰多層積層模組812a與812b之間，再將樹脂片811a 與811c (B階層狀態）分別配置於積層物之上下，仔細對準 位置加以重疊，加壓積層後，以使複合片801、樹脂片811 、以及貫通孔804中之未硬化之熱硬化性樹脂硬化之溫度 以上的溫度（例如150〜260°C)進行加熱，而獲得如圖9B所 示之構成8層的多層積層模組813。 依此製造方法，藉由將脫膜載體僅從電路元件內藏模 組之單面剝離並積層，藉由脫膜載體，加壓時保護配線圖 案，防止配線圖案之空氣氧化。又，樹脂片811，具有避免 接觸單體模組之緩衝層的作用，能有效地防止積層加壓時 半導體晶片的損傷。 又、藉由將多層積層模組上下主面之脫膜載體剝離而 使端子電極露出，能在積層成多層前，更完全進行導通檢 28 200302685 查等之品質檢查。 實施形態6 圖10D，係本實施形態之多層積層模組912的截面圖 。多層積層模組912，係在實施形態5之多層積層模組813 ，取代樹脂片811，使用配置薄膜狀電容914與薄膜狀電阻 913之連接用片915的構成。 依此構成，能以較半導體晶片與模組厚度分之相隔距 離更接近之方式配置薄膜狀電容，能有效地使電容具備旁 路電容之功能。又，亦能使電容大容量化。 就本實施形態之多層積層模組的製造方法之一例，參 照圖10A- D及圖11A— C說明如下。 首先，與實施形態5相同的，製造電路元件內藏模組 910。之後，如圖10A所示，以機械方式剝離電路元件內藏 模組910單面之脫膜載體907a。901係複合片，903a、903b 係半導體晶片，904係內導孔，905係凸塊，907b係裏面之 脫膜載體。 另外，如圖11A—C所示，製作連接用片915。首先， 如圖11A所示，將印刷有薄膜狀電容914之脫膜載體907a ，印刷有薄膜狀電阻913之脫膜載體907b，及具有貫通孔 904之樹脂片911對準位置加以重疊，形成如圖11B之積層 狀態。此處，在脫膜載體907a 、907b上，形成既定之配 線圖案。又，電容914或電阻913，係用蒸鑛、噴鍍、 M〇CVD(metal—organic chemical vapor)等之薄膜形成法，或 網印等方式形成於脫膜載體907a 、907b上。又，樹脂片 29 200302685 911之材料，只要是能成爲B階狀態者並無特別限定’但 是宜使用與使用於複合片901之混合物相同組成的混合物 ，較佳者爲無機塡料之含有量與使用於複合片901之混合 物相等的混合物。然後，如圖11C所示，以機械方式將脫 膜載體907a、907b從樹脂片911上下面剝離，將電阻913 與電容914轉印至樹脂片911後，埋設於其中，來製作連 接用片915。 以下，與實施形態5相同的，如圖10B所示，將連接 用片915配置於相鄰電路元件內藏模組910、910之間，對 準位置加以重疊、加壓，成爲如圖10C所示之積層狀態， 如圖10D所示，以機械方式將脫膜載體907a、907b從多層 積層模組912上下面剝離。 藉此，能獲得積層半導體晶片4層之多層積層模組912。 依本實施形態，由能在裸半導體端子電極之最附近配 置旁路電容，故能發揮雜訊特性高之特性。 【圖式簡單說明】 (一）圖式部分 圖1，係顯示本發明實施形態1之電路元件內藏模組的 截面圖。 圖2A〜F，係顯示本發明實施形態1之電路元件內藏 模組之製造方法的製程截面圖。 圖3A〜D，係顯示本發明實施形態2之電路元件內藏 模組的截面圖。 圖4A〜C，係顯示本發明實施形態2之電路元件內藏 30 200302685 模組之製造方法的製程截面圖。 圖5，係顯示本發明實施形態3之電路元件內藏模組的 截面圖。 圖6A〜E，係顯示本發明實施形態3之電路元件內藏 模組之製造方法的製程截面圖。 圖7A〜B，係顯示本發明實施形態4之多層積層模組 之製造方法的製程截面圖。 圖8A〜D，係顯示本發明實施形態5之多層積層模組 之製造方法的製程截面圖。 圖9A〜B，係顯示本發明實施形態5之多層積層模組 之製造方法的製程截面圖。 圖10A〜D，係顯示本發明實施形態6之多層積層模組 之製造方法的製程截面圖。 圖11A〜C，係顯示本發明實施形態6之多層積層模組 之製造方法的製程截面圖。 圖12A〜B，係顯示習知技術之多層積層模組的截面圖。 圖13，係顯示習知技術之其他多層積層模組的截面圖。 (二）元件代表符號 101，201a，301, 401a，501，601a 電氣絕緣性基板 102, 102a, 102c, 202a, 202b, 202c, 302a, 502a, 502c, 5〇2d，602a, 602b，602c 配線圖案 103，203，303，403，503a，503b，603，603a, 603b，1001， 1104 半導體晶片 104, 204a, 304, 504, 604a，804b 內導孔 31 200302685 105, 205, 505, 605b 凸塊 106, 206, 506 電氣絕緣性薄片 112, 212, 312, 412, 512, 612, 701a，810, 910 電路元件內藏模組 201, 401，601，701, 801，901 複合片 2〇4, 604, 704, 804, 904， 貫通孔 207, 607a, 707a, 707b, 807a, 907a? 907b 脫膜載體 305 金屬凸塊 306, 406 多層基板 307 半導體封裝體 407 記憶體封裝體 507 緩衝層 603c 晶片電容 712, 812, 812a，813, 912 多層積層模組 811， 81l£ 1, 811b, 911 樹脂片 913 電阻 914 電容 915 連接用片 1002 玻璃-環氧基板 1003 多層積層記憶體封裝體
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Claims (1)

  1. 200302685 拾、申請專利範匯 1. 一種電路元件內藏模組，包含，由含無機塡料與熱 硬化性樹脂之混合物所組成的電氣絕緣性基板，形成於電 氣絕緣性基板之至少主面的複數個配線圖案，內藏於電氣 絕緣性基板、且與配線圖案電氣連接的半導體晶片，以及 貫通電氣絕緣性基板以電氣連接複數個配線圖案所形成的 內導孔，其特徵在於： 前述半導體晶片之厚度爲30μιη〜ΙΟΟμιη，且非配線面 爲磨削面； 前述電路元件內藏模組之厚度在80μιη〜200μιη之範圍 〇 2. 如申請專利範圍第1項之電路元件內藏模組，其中 ，前述半導體晶片，係晶圓級晶片尺寸封裝（CSP : chip scale package)半導體。 3. 如申請專利範圍第1項之電路元件內藏模組，其中 ，前述半導體晶片，係以其上面彼此相對之狀態沿厚度方 向埋設2個。 4. 如申請專利範圍第1項之電路元件內藏模組，其中 ，前述配線圖案，進一步亦形成於前述電氣絕緣性基板之 其他主面； 於前述電氣絕緣性基板，以其上面彼此對向之狀態沿 前述電氣絕緣性基板之厚度方向內藏2個前述半導體晶片 ， 前述2個半導體晶片之一方，係與前述電氣絕緣性基 33 200302685 板主面形成之配線圖案電氣連接，另一方與前述電氣絕緣 性基板其他主面形成之配線圖案作電氣連接。 5. 如申請專利範圍第1項之電路元件內藏模組，其中 ，形成於前述電氣絕緣性基板之至少主面的配線圖案，係 積層於前述電氣絕緣性基板之多層配線基板表層之配線圖 案的一部分。 6. 如申請專利範圍第1項之電路元件內藏模組，其中 ，進一步內藏被動元件於前述電氣絕緣性基板，前述被動 元件係與前述複數個配線圖案中之任一個作電氣連接。 7. 如申請專利範圍第6項之電路元件內藏模組，其中 ，前述被動元件係選自電感、電容及電阻中之至少一種。 8. 如申請專利範圍第1項之電路元件內藏模組，其中 ，前述半導體晶片與前述配線圖案之連接部，係以底塡樹 脂、電氣絕緣性薄膜（NCF)、或含導電粒子之異方性導電膜 (ACF)來補強。 9. 如申請專利範圍第1項之電路元件內藏模組，其中 ，將前述電路元件內藏模組積層4〜8層來形成多層積層模 組，相鄰電路元件內藏模組係藉由前述內導孔作電氣連接 〇 10. 如申請專利範圍第1項之電路元件內藏模組’其 中，在前述相鄰電路元件內藏模組間，配置具備內導孔之 電氣絕緣性基板，前述電氣絕緣性基板，係與構成前述電 路元件內藏模組之電氣絕緣性基板爲相同組成物。 11. 如申請專利範圍第9項之電路元件內藏模組’其 34 200302685 中，將前述電路元件內藏模組積層4〜8層來形成多層積層 模組，在相鄰電路元件內藏模組間，配置具備內導孔之電 氣絕緣性基板，在前述電氣絕緣性基板上配置薄膜狀之被 動元件。 12. 如申請專利範圍第1項之電路元件內藏模組，其 中，前述電路元件內藏模組之厚度爲100〜150μιη。 13. —種電路元件內藏模組之製造方法，該電路元件 內藏模組，包含由含無機塡料與熱硬化性樹脂之混合物所 組成的電氣絕緣性基板，形成於電氣絕緣性基板之至少主 面的複數個配線圖案，內藏於電氣絕緣性基板、且與配線 圖案電氣連接的半導體晶片，以及貫通電氣絕緣性基板以 電氣連接複數個配線圖案所形成的內導孔，其特徵在於包 含： 準備板狀體的製程，該板狀體，係在前述電氣絕緣性 基板開設貫通孔，於其中塡充有熱硬化性之導電性物質； 將半導體晶片構裝於脫膜載體上所形成之配線圖案的 製程； 將前述半導體晶片之非配線面磨削成30μηι〜ΙΟΟμιη之 厚度的製程； 在前述脫膜載體之配線圖案形成面上，以前述配線圖 案與前述貫通孔中塡充有導電性物質之部分一致的方式， 將前述板狀體對準位置而重疊，藉由加壓使前述半導體晶 片埋設於前述板狀體中的製程； 藉由加熱前述埋設體，使前述混合物與前述導電性物 35 200302685 質同時硬化，而獲得厚度80μιη〜200μηι之電路元件內藏模 組的製程；以及 剝離前述脫膜載體的製程。 14·如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，將前述半導體晶片埋設於前述板狀體中的 製程’係藉由使用2片形成有前述配線圖案之脫膜載體， 挾住前述板狀體對準位置而重疊、加熱，將半導體晶片以 其上面彼此相對之狀態沿厚度方向埋設2個於前述板狀體 中的製程。 15. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，前述配線圖案，進一步亦形成於前述電氣 絕緣性基板之其他主面； 於前述電氣絕緣性基板，以其上面彼此對向之狀態沿 前述電氣絕緣性基板之厚度方向內藏2個前述半導體晶片 前述2個半導體晶片之一方，係與前述電氣絕緣性基 板主面形成之配線圖案電氣連接，另一方與前述電氣絕緣 性基板其他主面形成之配線圖案作電氣連接。 16. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，形成於前述電氣絕緣性基板之至少主面的 配線圖案，係積層於前述電氣絕緣性基板之多層配線基板 表層之配線圖案的一部分。 17. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，進一步內藏被動元件於前述電氣絕緣性基 36 200302685 板’前述被動元件與前述複數個配線圖案中之任一個作電 氣連接。 18. 如申請專利範圍第π項之電路元件內藏模組之製 造方法，其中，前述被動元件係選自電感、電容及電阻中 之至少一種。 19. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，前述半導體晶片與前述配線圖案之連接部 ，係以底塡樹脂，電氣絕緣性薄膜（NCF)，或含導電粒子之 異方性導電膜（ACF)來補強。 20. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，在將前述電路元件內藏模組積層4〜8層來 形成多層積層模組時，係將相鄰電路元件內藏模組藉由前 述內通作電氣連接。 21. 如申請專利範圍第20項之電路元件內藏模組之製 造方法，其中，在前述相鄰電路元件內藏模組間，配置具 備內導孔之第2電氣絕緣性基板，前述第2電氣絕緣性基 板，係與構成前述電路元件內藏模組之第1電氣絕緣性基 板爲相同組成物。 22. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，將前述電路元件內藏模組積層4〜8層來形 成多層積層模組時，在相鄰電路元件內藏模組間，配置具 備內導孔之電氣絕緣性基板，在前述電氣絕緣性基板上配 置薄膜狀之被動元件。 23. 如申請專利範圍第13項之電路元件內藏模組之製 37 200302685 造方法，其中，前述電路元件內藏模組之厚度爲100〜 150μηι 0 24. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，前述脫膜載體，係金屬片或樹脂片。 25. 如申請專利範圍第24項之電路元件內藏模組之製 造方法，其中，前述樹脂片，係選自聚醯亞胺、聚對苯二 甲酸乙醇二酯、聚對萘二甲酸乙二酯、聚苯硫、聚乙烯、 聚丙烯、及氟樹脂中之至少一種樹脂薄膜。 26. 如申請專利範圍第24項之電路元件內藏模組之製 造方法，其中，前述金屬片係銅箔_。 27. 如申請專利範圍第13項之電路元件內藏模組之製 造方法，其中，前述脫膜載體係銅箔，前述配線圖案係銅 箔，前述脫膜載體與前述配線圖案間之剝離層係以鑛鉻層 形成。 拾壹、圖式 如次頁。 38
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI552271B (zh) * 2013-12-26 2016-10-01 英特爾股份有限公司 用於可撓式電子通訊裝置之方法與設備

Families Citing this family (231)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5643801A (en) * 1992-11-06 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Laser processing method and alignment
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US8455994B2 (en) * 2002-01-31 2013-06-04 Imbera Electronics Oy Electronic module with feed through conductor between wiring patterns
FI119215B (fi) * 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
FI115285B (fi) * 2002-01-31 2005-03-31 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7485489B2 (en) * 2002-06-19 2009-02-03 Bjoersell Sten Electronics circuit manufacture
US7349225B1 (en) 2002-10-22 2008-03-25 Odyssian Technology, Llc Multifunctional composite sandwich element with embedded electronics
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
KR100621991B1 (ko) * 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
JP3740469B2 (ja) * 2003-01-31 2006-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
FI20030293A (fi) * 2003-02-26 2004-08-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
FI119583B (fi) 2003-02-26 2008-12-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
US6838351B2 (en) * 2003-03-31 2005-01-04 Canon Kabushiki Kaisha Manufacturing method of circuit board, circuit board, and liquid discharging apparatus
JP2004327920A (ja) * 2003-04-28 2004-11-18 Sharp Corp 半導体装置の製造方法、フレキシブル基板及び半導体装置
US7371607B2 (en) * 2003-05-02 2008-05-13 Seiko Epson Corporation Method of manufacturing semiconductor device and method of manufacturing electronic device
JP3912318B2 (ja) * 2003-05-02 2007-05-09 セイコーエプソン株式会社 半導体装置の製造方法および電子デバイスの製造方法
DE10320646A1 (de) * 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
US7414505B2 (en) * 2003-05-13 2008-08-19 Samsung Electronics Co., Ltd. High frequency inductor having low inductance and low inductance variation and method of manufacturing the same
EP1627437B1 (en) * 2003-05-26 2016-03-30 Panasonic Intellectual Property Management Co., Ltd. Light-emitting device
EP1627430B1 (en) * 2003-05-28 2008-10-01 Infineon Technologies AG An integrated circuit package employing a flexible substrate
TW200507131A (en) * 2003-07-02 2005-02-16 North Corp Multi-layer circuit board for electronic device
CN1577819A (zh) * 2003-07-09 2005-02-09 松下电器产业株式会社 带内置电子部件的电路板及其制造方法
DE10334576B4 (de) * 2003-07-28 2007-04-05 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse
US7456035B2 (en) * 2003-07-29 2008-11-25 Lumination Llc Flip chip light emitting diode devices having thinned or removed substrates
US7547975B2 (en) * 2003-07-30 2009-06-16 Tdk Corporation Module with embedded semiconductor IC and method of fabricating the module
FI20031201A (fi) * 2003-08-26 2005-02-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
FI20031341A (fi) 2003-09-18 2005-03-19 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
JP2005101356A (ja) * 2003-09-25 2005-04-14 Toshiba Corp 無線カード
JP4340517B2 (ja) 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US6943294B2 (en) * 2003-12-22 2005-09-13 Intel Corporation Integrating passive components on spacer in stacked dies
JP4954712B2 (ja) * 2003-12-24 2012-06-20 ジーイー ライティング ソリューションズ エルエルシー 窒化物フリップチップからのサファイヤのレーザ・リフトオフ
JP2005203674A (ja) * 2004-01-19 2005-07-28 Nitto Denko Corp 電子部品内蔵基板の製造方法
DE102004003784B4 (de) 2004-01-23 2011-01-13 Ormecon Gmbh Dispersion intrinsisch leitfähigen Polyanilins und deren Verwendung
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
CA2558147A1 (en) * 2004-03-18 2005-09-29 Ormecon Gmbh A composition comprising a conductive polymer in colloidal form and carbon
US20050205951A1 (en) * 2004-03-18 2005-09-22 Honeywell Internatioanl, Inc. Flip chip bonded micro-electromechanical system (MEMS) device
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US7067910B2 (en) * 2004-04-13 2006-06-27 Sun Microsystems, Inc. Method and apparatus for using capacitively coupled communication within stacks of laminated chips
JP4541753B2 (ja) * 2004-05-10 2010-09-08 新光電気工業株式会社 電子部品実装構造の製造方法
US20050258533A1 (en) * 2004-05-21 2005-11-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device mounting structure
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
DE102004030388A1 (de) * 2004-06-23 2006-01-26 Ormecon Gmbh Artikel mit einer Beschichtung von elektrisch leitfähigem Polymer und Verfahren zu deren Herstellung
DE102004030930A1 (de) * 2004-06-25 2006-02-23 Ormecon Gmbh Zinnbeschichtete Leiterplatten mit geringer Neigung zur Whiskerbildung
JP3961537B2 (ja) * 2004-07-07 2007-08-22 日本電気株式会社 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法
WO2006006343A1 (ja) * 2004-07-14 2006-01-19 Murata Manufacturing Co., Ltd. 圧電デバイス
WO2006011508A1 (ja) * 2004-07-30 2006-02-02 Murata Manufacturing Co., Ltd. 複合型電子部品及びその製造方法
WO2006011320A1 (ja) * 2004-07-30 2006-02-02 Murata Manufacturing Co., Ltd. 複合型電子部品及びその製造方法
US7351608B1 (en) * 2004-08-19 2008-04-01 The United States Of America As Represented By The Director Of The National Security Agency Method of precisely aligning components in flexible integrated circuit module
CN100539135C (zh) * 2004-09-08 2009-09-09 松下电器产业株式会社 立体电路装置、使用它的电子机器及其制造方法
TW200618705A (en) * 2004-09-16 2006-06-01 Tdk Corp Multilayer substrate and manufacturing method thereof
DE102004046227B3 (de) * 2004-09-22 2006-04-20 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten durch eine Kunststoffgehäusemasse und entsprechendes Halbleiterbauteil
DE102004049663B3 (de) * 2004-10-11 2006-04-13 Infineon Technologies Ag Kunststoffgehäuse und Halbleiterbauteil mit derartigem Kunststoffgehäuse sowie Verfahren zur Herstellung derselben
US7432596B1 (en) * 2004-10-12 2008-10-07 Energy Innovations, Inc. Apparatus and method for bonding silicon wafer to conductive substrate
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP2006203086A (ja) * 2005-01-24 2006-08-03 Citizen Electronics Co Ltd 電子部品パッケージ及びその製造方法
DE102005010162B4 (de) * 2005-03-02 2007-06-14 Ormecon Gmbh Leitfähige Polymere aus Teilchen mit anisotroper Morphologie
JP4688526B2 (ja) * 2005-03-03 2011-05-25 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7286366B2 (en) * 2005-03-24 2007-10-23 Motorola, Inc. Multilayer circuit board with embedded components and method of manufacture
KR100716826B1 (ko) * 2005-05-10 2007-05-09 삼성전기주식회사 전자부품이 내장된 기판의 제조방법
JP2006324568A (ja) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 多層モジュールとその製造方法
DE102005025543B4 (de) * 2005-06-01 2007-07-12 Infineon Technologies Ag Halbleiterbaumodul und Verfahren zur Herstellung desselben
US7675151B1 (en) * 2005-06-01 2010-03-09 Rockwell Collins, Inc. Silicon-based packaging for electronic devices
JP4322844B2 (ja) * 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
FI119714B (fi) * 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
JP2008544512A (ja) * 2005-06-16 2008-12-04 イムベラ エレクトロニクス オサケユキチュア 回路基板構造体およびその製造方法
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
DE102005039608A1 (de) * 2005-08-19 2007-03-01 Ormecon Gmbh Zusammensetzung mit intrinsisch leitfähigem Polymer
JP2007059821A (ja) * 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP4566866B2 (ja) * 2005-09-07 2010-10-20 新光電気工業株式会社 半導体パッケージ、半導体パッケージの実装構造、半導体パッケージの製造方法
JP4535002B2 (ja) 2005-09-28 2010-09-01 Ｔｄｋ株式会社 半導体ｉｃ内蔵基板及びその製造方法
WO2007043639A1 (ja) * 2005-10-14 2007-04-19 Fujikura Ltd. プリント配線基板及びプリント配線基板の製造方法
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
US7420817B2 (en) * 2006-01-09 2008-09-02 Honeywell International Inc. MEMS device seal using liquid crystal polymer
TW200727370A (en) * 2006-01-12 2007-07-16 Touch Micro System Tech Integrated die packaging structure and manufacturing process thereof
US20070212865A1 (en) * 2006-03-08 2007-09-13 Craig Amrine Method for planarizing vias formed in a substrate
US8367465B2 (en) * 2006-03-17 2013-02-05 Stats Chippac Ltd. Integrated circuit package on package system
JP4849926B2 (ja) * 2006-03-27 2012-01-11 富士通株式会社 半導体装置及び半導体装置の製造方法
US20070262435A1 (en) * 2006-04-27 2007-11-15 Atmel Corporation Three-dimensional packaging scheme for package types utilizing a sacrificial metal base
US7564137B2 (en) * 2006-04-27 2009-07-21 Atmel Corporation Stackable integrated circuit structures and systems devices and methods related thereto
KR100790990B1 (ko) * 2006-05-22 2008-01-03 삼성전자주식회사 냉각통로를 갖는 적층형 반도체 소자
TWI307946B (en) * 2006-05-24 2009-03-21 Phoenix Prec Technology Corp Stack structure of circuit board having embedded with semicondutor component
KR100734403B1 (ko) * 2006-06-02 2007-07-02 삼성전기주식회사 전자소자 패키지 및 그 제조방법
TWI292947B (en) * 2006-06-20 2008-01-21 Unimicron Technology Corp The structure of embedded chip packaging and the fabricating method thereof
US8293584B2 (en) * 2006-08-04 2012-10-23 Stats Chippac Ltd. Integrated circuit package system with filled wafer recess
MY147793A (en) * 2006-09-13 2013-01-31 Enthone Article with a coating of electrically conductive polymer and precious/semiprecious metal and process for production thereof
JP2008103503A (ja) * 2006-10-18 2008-05-01 Shinwa Frontech Corp 回路基板の製造方法
TWI328865B (en) * 2006-10-31 2010-08-11 Ind Tech Res Inst Structure of chip stacked packaging, structure of embedded chip packaging and fabricating method thereof
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
JP4862641B2 (ja) * 2006-12-06 2012-01-25 株式会社デンソー 多層基板及び多層基板の製造方法
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
US20080142996A1 (en) * 2006-12-19 2008-06-19 Gopalakrishnan Subramanian Controlling flow of underfill using polymer coating and resulting devices
US7875503B2 (en) * 2006-12-28 2011-01-25 Intel Corporation Reducing underfill keep out zone on substrate used in electronic device processing
EP1956652A1 (en) * 2007-02-08 2008-08-13 Nederlandse Organisatie voor Toegepast-Natuuurwetenschappelijk Onderzoek TNO Sealed ball grid array package
JP2008198916A (ja) * 2007-02-15 2008-08-28 Spansion Llc 半導体装置及びその製造方法
US7960210B2 (en) * 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US7863088B2 (en) * 2007-05-16 2011-01-04 Infineon Technologies Ag Semiconductor device including covering a semiconductor with a molding compound and forming a through hole in the molding compound
DE102007024189A1 (de) * 2007-05-24 2008-11-27 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
JP2008294381A (ja) * 2007-05-28 2008-12-04 Panasonic Corp 電子部品モジュール及び電子部品モジュールの製造方法
US8106496B2 (en) * 2007-06-04 2012-01-31 Stats Chippac, Inc. Semiconductor packaging system with stacking and method of manufacturing thereof
JP2008305937A (ja) * 2007-06-07 2008-12-18 Panasonic Corp 電子部品内蔵モジュールおよびその製造方法
JP5012896B2 (ja) * 2007-06-26 2012-08-29 株式会社村田製作所 部品内蔵基板の製造方法
US8471375B2 (en) * 2007-06-30 2013-06-25 Kinsus Interconnect Technology Corp. High-density fine line structure and method of manufacturing the same
US8829663B2 (en) * 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
TWI368956B (en) * 2007-08-10 2012-07-21 Siliconware Precision Industries Co Ltd Multichip stack structure and method for fabricating the same
KR100881400B1 (ko) 2007-09-10 2009-02-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
JP5690466B2 (ja) * 2008-01-31 2015-03-25 インヴェンサス・コーポレイション 半導体チップパッケージの製造方法
US7968378B2 (en) * 2008-02-06 2011-06-28 Infineon Technologies Ag Electronic device
US8225503B2 (en) * 2008-02-11 2012-07-24 Ibiden Co., Ltd. Method for manufacturing board with built-in electronic elements
EP2244288A4 (en) * 2008-02-14 2011-11-02 Mitsubishi Heavy Ind Ltd SEMICONDUCTOR ELEMENT MODULE AND METHOD FOR THE PRODUCTION THEREOF
JP5064278B2 (ja) * 2008-03-25 2012-10-31 日東電工株式会社 光半導体素子封止用樹脂シートおよび光半導体装置
JPWO2009118925A1 (ja) * 2008-03-27 2011-07-21 イビデン株式会社 電子部品内蔵配線板及びその製造方法
DE102008002532A1 (de) * 2008-06-19 2009-12-24 Robert Bosch Gmbh Verfahren zur Herstellung einer elektronischen Baugruppe
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
JP5344394B2 (ja) * 2008-07-10 2013-11-20 山栄化学株式会社 硬化性樹脂組成物、並びにハロゲンフリー樹脂基板及びハロゲンフリービルドアッププリント配線板
KR100997199B1 (ko) * 2008-07-21 2010-11-29 삼성전기주식회사 전자소자 내장형 인쇄회로기판 제조방법
US8076587B2 (en) 2008-09-26 2011-12-13 Siemens Energy, Inc. Printed circuit board for harsh environments
US8704350B2 (en) * 2008-11-13 2014-04-22 Samsung Electro-Mechanics Co., Ltd. Stacked wafer level package and method of manufacturing the same
US9059050B2 (en) 2008-11-17 2015-06-16 Advanpack Solutions Pte. Ltd. Manufacturing methods of semiconductor substrate, package and device
CN102144291B (zh) * 2008-11-17 2015-11-25 先进封装技术私人有限公司 半导体基板、封装与装置
US20100127407A1 (en) * 2008-11-25 2010-05-27 Leblanc John Two-sided substrateless multichip module and method of manufacturing same
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US9293401B2 (en) 2008-12-12 2016-03-22 Stats Chippac, Ltd. Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9082806B2 (en) 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9064936B2 (en) 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP5058144B2 (ja) * 2008-12-25 2012-10-24 新光電気工業株式会社 半導体素子の樹脂封止方法
JP2010238941A (ja) * 2009-03-31 2010-10-21 Sanyo Electric Co Ltd 発光デバイス
JP4760930B2 (ja) * 2009-02-27 2011-08-31 株式会社デンソー Ｉｃ搭載基板、多層プリント配線板、及び製造方法
US8003445B2 (en) * 2009-03-26 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
US7960827B1 (en) 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8623753B1 (en) 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
US8222538B1 (en) 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8106499B2 (en) * 2009-06-20 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual substrate package and method of manufacture thereof
US20100327406A1 (en) 2009-06-26 2010-12-30 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
KR101067199B1 (ko) * 2009-07-07 2011-09-22 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component
US8471154B1 (en) 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
FR2951019B1 (fr) * 2009-10-07 2012-06-08 Valeo Etudes Electroniques Module de puissance pour vehicule automobile
TWI501376B (zh) * 2009-10-07 2015-09-21 Xintec Inc 晶片封裝體及其製造方法
KR101095094B1 (ko) * 2009-10-26 2011-12-16 삼성전기주식회사 웨이퍼 레벨 패키지의 제조방법
KR20110054348A (ko) * 2009-11-17 2011-05-25 삼성전기주식회사 전자소자 내장형 인쇄회로기판 및 그 제조방법
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8476775B2 (en) * 2009-12-17 2013-07-02 Stats Chippac Ltd. Integrated circuit packaging system with embedded interconnect and method of manufacture thereof
DE102009060480A1 (de) * 2009-12-18 2011-06-22 Schweizer Electronic AG, 78713 Leiterstrukturelement und Verfahren zum Herstellen eines Leiterstrukturelements
US8536462B1 (en) 2010-01-22 2013-09-17 Amkor Technology, Inc. Flex circuit package and method
CN102222625A (zh) * 2010-04-16 2011-10-19 展晶科技(深圳)有限公司 发光二极管封装结构及其基座的制造方法
US8300423B1 (en) 2010-05-25 2012-10-30 Amkor Technology, Inc. Stackable treated via package and method
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8105872B2 (en) 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
US8236617B2 (en) * 2010-06-04 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
DE102010026843A1 (de) * 2010-07-12 2012-01-12 Epcos Ag Modul-Package und Herstellungsverfahren
US8338229B1 (en) 2010-07-30 2012-12-25 Amkor Technology, Inc. Stackable plasma cleaned via package and method
US8717775B1 (en) 2010-08-02 2014-05-06 Amkor Technology, Inc. Fingerprint sensor package and method
US8378477B2 (en) 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof
EP2448378A1 (en) * 2010-10-26 2012-05-02 ATOTECH Deutschland GmbH Composite build-up materials for embedding of active components
US8337657B1 (en) 2010-10-27 2012-12-25 Amkor Technology, Inc. Mechanical tape separation package and method
US8482134B1 (en) 2010-11-01 2013-07-09 Amkor Technology, Inc. Stackable package and method
US8546193B2 (en) 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
US9748154B1 (en) 2010-11-04 2017-08-29 Amkor Technology, Inc. Wafer level fan out semiconductor device and manufacturing method thereof
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8415684B2 (en) * 2010-11-12 2013-04-09 Tsmc Solid State Lighting Ltd. LED device with improved thermal performance
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
US8557629B1 (en) 2010-12-03 2013-10-15 Amkor Technology, Inc. Semiconductor device having overlapped via apertures
US8535961B1 (en) 2010-12-09 2013-09-17 Amkor Technology, Inc. Light emitting diode (LED) package and method
CN102157392B (zh) * 2011-01-31 2012-06-13 江阴长电先进封装有限公司 低成本芯片扇出结构的封装方法
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9013011B1 (en) 2011-03-11 2015-04-21 Amkor Technology, Inc. Stacked and staggered die MEMS package and method
US9406580B2 (en) * 2011-03-16 2016-08-02 Synaptics Incorporated Packaging for fingerprint sensors and methods of manufacture
CN102157502B (zh) * 2011-03-23 2014-05-07 南通富士通微电子股份有限公司 ***级封装结构
US9543269B2 (en) 2011-03-22 2017-01-10 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
WO2012126377A1 (en) 2011-03-22 2012-09-27 Nantong Fujitsu Microelectronics Co., Ltd. System-level packaging methods and structures
KR101140113B1 (ko) 2011-04-26 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
KR20120131530A (ko) 2011-05-25 2012-12-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8653674B1 (en) 2011-09-15 2014-02-18 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8633598B1 (en) 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US9029962B1 (en) 2011-10-12 2015-05-12 Amkor Technology, Inc. Molded cavity substrate MEMS package fabrication method and structure
WO2013078609A1 (zh) * 2011-11-29 2013-06-06 中国科学院微电子研究所 有源芯片封装基板及制备该基板的方法
US8962392B2 (en) * 2012-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill curing method using carrier
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US9281242B2 (en) 2012-10-25 2016-03-08 Nanya Technology Corp. Through silicon via stacked structure and a method of manufacturing the same
KR101419597B1 (ko) * 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
CN102905478B (zh) * 2012-11-14 2016-12-28 江苏普诺威电子股份有限公司 多层印刷板内埋元器件工艺
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR20140067359A (ko) * 2012-11-26 2014-06-05 삼성전기주식회사 적층형 반도체 패키지
US9161454B2 (en) * 2012-12-24 2015-10-13 Unimicron Technology Corp. Electrical device package structure and method of fabricating the same
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
KR101488590B1 (ko) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20140374151A1 (en) * 2013-06-24 2014-12-25 Jia Lin Yap Wire bonding method for flexible substrates
CN103390563B (zh) * 2013-08-06 2016-03-30 江苏长电科技股份有限公司 先封后蚀芯片倒装三维***级金属线路板结构及工艺方法
CN103489792B (zh) * 2013-08-06 2016-02-03 江苏长电科技股份有限公司 先封后蚀三维***级芯片倒装封装结构及工艺方法
CN105518824A (zh) * 2013-09-06 2016-04-20 张于纯 液态玻璃的应用
CN103646880A (zh) * 2013-09-29 2014-03-19 华进半导体封装先导技术研发中心有限公司 一种基于板级功能基板的封装工艺及封装结构
KR102084540B1 (ko) * 2013-10-16 2020-03-04 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
TWI529906B (zh) * 2013-12-09 2016-04-11 矽品精密工業股份有限公司 半導體封裝件之製法
AT515443B1 (de) * 2014-02-28 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte
TWI548043B (zh) * 2014-11-17 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI581690B (zh) * 2014-12-30 2017-05-01 恆勁科技股份有限公司 封裝裝置及其製作方法
US20160240457A1 (en) * 2015-02-18 2016-08-18 Altera Corporation Integrated circuit packages with dual-sided stacking structure
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
US10256173B2 (en) * 2016-02-22 2019-04-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US10504827B2 (en) 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
CN110301041B (zh) * 2017-02-17 2023-07-04 株式会社村田制作所 电路模块以及电路模块的制造方法
US10257925B2 (en) * 2017-04-10 2019-04-09 Tactotek Oy Method for manufacturing an electronic assembly
DE102017209249A1 (de) * 2017-05-31 2018-12-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur herstellung eines packages und package
US10206286B2 (en) 2017-06-26 2019-02-12 Infineon Technologies Austria Ag Embedding into printed circuit board with drilling
US10685934B2 (en) * 2017-07-10 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
DE102019208093A1 (de) * 2019-06-04 2020-12-10 Robert Bosch Gmbh Verfahren zum Herstellen einer dreidimensionalen Schaltung sowie dreidimensionale Schaltung
US11289468B2 (en) * 2019-06-12 2022-03-29 Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd. Package structure and method for manufacturing the same
DE102020206769B3 (de) * 2020-05-29 2021-06-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Mikroelektronische anordnung und verfahren zur herstellung derselben
CN112908868A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 存储器三维封装方法及结构

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6347991A (ja) 1986-08-18 1988-02-29 古河電気工業株式会社 プリント回路基板の製造方法
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
JPH05259372A (ja) 1992-01-14 1993-10-08 Sony Corp ハイブリッドｉｃ
JP2601128B2 (ja) 1992-05-06 1997-04-16 松下電器産業株式会社 回路形成用基板の製造方法および回路形成用基板
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
TW256013B (en) * 1994-03-18 1995-09-01 Hitachi Seisakusyo Kk Installation board
KR960030189A (ko) * 1995-01-30 1996-08-17 다까노 야스아끼 매체 기록을 위한 기록 및 재생 장치와 기록 방법
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
JP2987101B2 (ja) 1996-04-15 1999-12-06 株式会社ニッシン 半導体装置の接続方法並びに半導体装置の接続器
US5821456A (en) * 1996-05-01 1998-10-13 Motorola, Inc. Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same
JP3322575B2 (ja) * 1996-07-31 2002-09-09 太陽誘電株式会社 ハイブリッドモジュールとその製造方法
US5874770A (en) * 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
JPH11103147A (ja) 1997-09-26 1999-04-13 Toshiba Corp 回路モジュール及び回路モジュールを内蔵した電子機器
JP3375555B2 (ja) 1997-11-25 2003-02-10 松下電器産業株式会社 回路部品内蔵モジュールおよびその製造方法
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JP2870533B1 (ja) 1997-11-27 1999-03-17 日本電気株式会社 半導体装置およびその製造方法
JPH11186462A (ja) * 1997-12-19 1999-07-09 Sony Corp 半導体装置と電子機器
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
JP3500995B2 (ja) 1998-12-18 2004-02-23 株式会社デンソー 積層型回路モジュールの製造方法
US6387734B1 (en) * 1999-06-11 2002-05-14 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
TW472330B (en) 1999-08-26 2002-01-11 Toshiba Corp Semiconductor device and the manufacturing method thereof
KR100842389B1 (ko) * 1999-09-02 2008-07-01 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
JP3450236B2 (ja) * 1999-09-22 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6559531B1 (en) * 1999-10-14 2003-05-06 Sun Microsystems, Inc. Face to face chips
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
JP3598060B2 (ja) 1999-12-20 2004-12-08 松下電器産業株式会社 回路部品内蔵モジュール及びその製造方法並びに無線装置
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP3537400B2 (ja) 2000-03-17 2004-06-14 松下電器産業株式会社 半導体内蔵モジュール及びその製造方法
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
JP4392157B2 (ja) * 2001-10-26 2009-12-24 パナソニック電工株式会社 配線板用シート材及びその製造方法、並びに多層板及びその製造方法
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI552271B (zh) * 2013-12-26 2016-10-01 英特爾股份有限公司 用於可撓式電子通訊裝置之方法與設備

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US7018866B2 (en) 2006-03-28
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US20040145044A1 (en) 2004-07-29
US6784530B2 (en) 2004-08-31

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