KR920007186A - 테스트모드기능 내장 다이내믹 랜덤 액세스 메모리장치 - Google Patents

테스트모드기능 내장 다이내믹 랜덤 액세스 메모리장치 Download PDF

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Publication number
KR920007186A
KR920007186A KR1019910015461A KR910015461A KR920007186A KR 920007186 A KR920007186 A KR 920007186A KR 1019910015461 A KR1019910015461 A KR 1019910015461A KR 910015461 A KR910015461 A KR 910015461A KR 920007186 A KR920007186 A KR 920007186A
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KR
South Korea
Prior art keywords
test mode
memory device
random access
access memory
dynamic random
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KR1019910015461A
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English (en)
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KR960001327B1 (ko
Inventor
히사시 이와모도
마사기 구마노야
가쯔고 다까사까
야스히로 고니시
아끼라 야마자끼
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR920007186A publication Critical patent/KR920007186A/ko
Application granted granted Critical
Publication of KR960001327B1 publication Critical patent/KR960001327B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/46—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using thermoplastic elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음.

Description

테스트모드기능 내장 다이내믹 랜덤 액세스 메모리장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 한 실시예를 표시하는 전기회로도.
제2도는 제1도의 회로의 동작을 설명하기 위한 타이밍도.
제3도는 제1도에 표시하는 2진(進) 카운터회로의 동작을 표시하는 신호파형도.
제4도는 테스트모드에 들어가기 위한 신호파형도.
제5도는 제4도의 신호파형을 검지하기 위한 한 실시예의 표시도.
제6도는 테스트모드에 들어가고 말 가능성이 있는 신호파형도.
제7도는 종내의신호를 발생하기 위한 한 실시예를 표시하는 전기회로도.
제8도는 제7도의 회로의 동작을 설명하기 위한 타이밍도.
제9도는 제5도의 회로를 파워온 리세트 하기 위한 회로.
제10도는 종래의신호 발생회로에서는 테스트모드에 들어가고 말 가능성이 있는 신호파형도.
* 도면의 주요부분에 대한 부호의 설명
1a,1b : 인버터 2a, 2b : NOR 게이트
3 : NAND 게이트 4 : 2진 카운터회로
또한 각 도면중 동일 또는 상당부분을 표시한다.

Claims (1)

  1. 전원전압 인가 후 동작시키기 전에 8회의 행어드레스 스트로브 신호의 사이클, 혹은 8회의 행어드레스 스트로브 신호와 열어드레스 스트로브 신호의 사이클을 행하고 다시금 이 사이클을 행하고 있을 때는 기록제어 신호는「H」상태로 유지(아래 더미 사이클이라고 칭함)하는 것을 행하는 다이내믹 랜덤 액세스 메모리 장치에 있어서, 전원전압 인가동작시키는 더미 사이클을 이용하여 파워온 리세트시키는 것을 특징으로 하는 테스트모드 기능내장 다이내믹 랜덤 액세스 메모리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910015461A 1990-09-10 1991-09-04 테스트모드기능 내장 다이내믹 랜덤 액세스 메모리장치 KR960001327B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-240952 1990-09-10
JP2240952A JPH04119600A (ja) 1990-09-10 1990-09-10 テストモード機能内蔵ダイナミックランダムアクセスメモリ装置

Publications (2)

Publication Number Publication Date
KR920007186A true KR920007186A (ko) 1992-04-28
KR960001327B1 KR960001327B1 (ko) 1996-01-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015461A KR960001327B1 (ko) 1990-09-10 1991-09-04 테스트모드기능 내장 다이내믹 랜덤 액세스 메모리장치

Country Status (4)

Country Link
US (2) US5270977A (ko)
JP (1) JPH04119600A (ko)
KR (1) KR960001327B1 (ko)
DE (1) DE4129875A1 (ko)

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JP2527835B2 (ja) * 1990-07-31 1996-08-28 三菱電機株式会社 半導体装置
JPH0636593A (ja) * 1992-07-14 1994-02-10 Mitsubishi Electric Corp 半導体記憶装置
US6204701B1 (en) 1994-05-31 2001-03-20 Texas Instruments Incorporated Power up detection circuit
JPH08153400A (ja) * 1994-11-29 1996-06-11 Mitsubishi Electric Corp Ｄｒａｍ
DE19524874C1 (de) * 1995-07-07 1997-03-06 Siemens Ag Verfahren zum Versetzen einer integrierten Schaltung von einer ersten in eine zweite Betriebsart
JPH10125742A (ja) * 1996-10-22 1998-05-15 Mitsubishi Electric Corp 半導体集積回路の良否判定方法及び半導体集積回路
US5745430A (en) * 1996-12-30 1998-04-28 Siemens Aktiengesellschaft Circuit and method to externally adjust internal circuit timing
US6115307A (en) * 1997-05-19 2000-09-05 Micron Technology, Inc. Method and structure for rapid enablement
JPH1116395A (ja) * 1997-06-25 1999-01-22 Mitsubishi Electric Corp 半導体記憶装置
US5901095A (en) * 1997-12-23 1999-05-04 Lsi Logic Corporation Reprogrammable address selector for an embedded DRAM
US5896331A (en) * 1997-12-23 1999-04-20 Lsi Logic Corporation Reprogrammable addressing process for embedded DRAM
US5907511A (en) * 1997-12-23 1999-05-25 Lsi Logic Corporation Electrically selectable redundant components for an embedded DRAM
US6064588A (en) * 1998-03-30 2000-05-16 Lsi Logic Corporation Embedded dram with noise-protected differential capacitor memory cells
US5999440A (en) * 1998-03-30 1999-12-07 Lsi Logic Corporation Embedded DRAM with noise-protecting substrate isolation well
US6005824A (en) * 1998-06-30 1999-12-21 Lsi Logic Corporation Inherently compensated clocking circuit for dynamic random access memory
US5978304A (en) * 1998-06-30 1999-11-02 Lsi Logic Corporation Hierarchical, adaptable-configuration dynamic random access memory
JP2000021173A (ja) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp 半導体装置
JP2001155485A (ja) * 1999-11-29 2001-06-08 Mitsubishi Electric Corp 半導体記憶装置
US6137738A (en) * 1999-11-30 2000-10-24 Lucent Technologies, Inc. Method for in-system programming of serially configured EEPROMS using a JTAG interface of a field programmable gate array
JP2001202797A (ja) * 2000-01-20 2001-07-27 Mitsubishi Electric Corp 半導体記憶装置および半導体テスト方法
US6320812B1 (en) * 2000-09-20 2001-11-20 Agilent Technologies, Inc. Error catch RAM for memory tester has SDRAM memory sets configurable for size and speed
JP4263374B2 (ja) 2001-01-22 2009-05-13 株式会社ルネサステクノロジ 半導体集積回路

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JPS60113392A (ja) * 1983-11-25 1985-06-19 Fujitsu Ltd 半導体メモリ装置
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JPH0799619B2 (ja) * 1989-12-28 1995-10-25 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPH04119600A (ja) 1992-04-21
DE4129875A1 (de) 1992-03-19
DE4129875C2 (ko) 1993-09-02
KR960001327B1 (ko) 1996-01-25
US5270977A (en) 1993-12-14
USRE36875E (en) 2000-09-19

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