KR910008730A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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Publication number
KR910008730A
KR910008730A KR1019900016100A KR900016100A KR910008730A KR 910008730 A KR910008730 A KR 910008730A KR 1019900016100 A KR1019900016100 A KR 1019900016100A KR 900016100 A KR900016100 A KR 900016100A KR 910008730 A KR910008730 A KR 910008730A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
bits
terminals
memory device
circuit blocks
Prior art date
Application number
KR1019900016100A
Other languages
Korean (ko)
Other versions
KR970000331B1 (en
Inventor
히데유끼 오자끼
Original Assignee
시기 모리야
미쯔비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쯔비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910008730A publication Critical patent/KR910008730A/en
Application granted granted Critical
Publication of KR970000331B1 publication Critical patent/KR970000331B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

반도체 기억장치Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 이 발명의 한 실시예에 의한 DRAM의 전체의 구성을 표시하는 블록도.1 is a block diagram showing the overall configuration of a DRAM according to one embodiment of the present invention;

제2도는 제1도의 DRAM의 주요부를 상세히 표시하는 회로도.FIG. 2 is a circuit diagram showing details of main parts of the DRAM of FIG.

Claims (1)

복수 비트로 이루어지는 데이타를 기억하는 반도체 기억장치에 있어서 상기 복수 비트의 데이타를 입력 또는 출력 하기 위한 복수의 단자, 상기 복수의 단자에 대응하여 설치된 복수의 기능회로 블록, 및 상기 복수의 기능회로 블록중 어느 것인가를 고정적으로 비활성 상태에 설정하기 위한 설정 수단을 구비한 반도체 기억장치.In a semiconductor memory device for storing data comprising a plurality of bits, any of a plurality of terminals for inputting or outputting the plurality of bits of data, a plurality of functional circuit blocks provided corresponding to the plurality of terminals, and the plurality of functional circuit blocks. A semiconductor memory device having setting means for fixedly setting whether or not to be in an inactive state. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900016100A 1989-10-11 1990-10-11 Semiconductor memory device KR970000331B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-264149 1989-10-11
JP1264149A JPH0778994B2 (en) 1989-10-11 1989-10-11 Semiconductor memory device

Publications (2)

Publication Number Publication Date
KR910008730A true KR910008730A (en) 1991-05-31
KR970000331B1 KR970000331B1 (en) 1997-01-08

Family

ID=17399145

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016100A KR970000331B1 (en) 1989-10-11 1990-10-11 Semiconductor memory device

Country Status (4)

Country Link
US (1) US5875132A (en)
JP (1) JPH0778994B2 (en)
KR (1) KR970000331B1 (en)
DE (1) DE4020895C2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260103B1 (en) * 1998-01-05 2001-07-10 Intel Corporation Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers
KR100306965B1 (en) * 1998-08-07 2001-11-30 윤종용 Data Transmission Circuit of Synchronous Semiconductor Memory Device
US6141286A (en) * 1998-08-21 2000-10-31 Micron Technology, Inc. Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
US6320811B1 (en) * 1998-12-10 2001-11-20 Cypress Semiconductor Corp. Multiport memory scheme
JP4597470B2 (en) * 2002-07-25 2010-12-15 富士通セミコンダクター株式会社 Semiconductor memory
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7660183B2 (en) * 2005-08-01 2010-02-09 Rambus Inc. Low power memory device
US7906982B1 (en) 2006-02-28 2011-03-15 Cypress Semiconductor Corporation Interface apparatus and methods of testing integrated circuits using the same
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US10776233B2 (en) 2011-10-28 2020-09-15 Teradyne, Inc. Programmable test instrument
US9759772B2 (en) 2011-10-28 2017-09-12 Teradyne, Inc. Programmable test instrument
US10453544B2 (en) 2014-12-10 2019-10-22 Nxp Usa, Inc. Memory array with read only cells having multiple states and method of programming thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427785A (en) * 1977-08-04 1979-03-02 Nec Corp Integrated circuit
JPS56124929A (en) * 1980-03-06 1981-09-30 Toshiba Corp Integrated circuit device
FR2528613B1 (en) * 1982-06-09 1991-09-20 Hitachi Ltd SEMICONDUCTOR MEMORY
DE3276399D1 (en) * 1982-09-22 1987-06-25 Itt Ind Gmbh Deutsche Electrically programmable memory matrix
JPS62112292A (en) * 1985-11-11 1987-05-23 Nec Corp Memory circuit
JPS62120700A (en) * 1985-11-20 1987-06-01 Fujitsu Ltd Semiconductor memory device
JPS62188090A (en) * 1986-02-13 1987-08-17 Mitsubishi Electric Corp Voltage detection circuit
JPS6326892A (en) * 1986-07-18 1988-02-04 Nec Corp Memory device
JPS6337894A (en) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp Random access memory
JPS6349812A (en) * 1986-08-19 1988-03-02 Fujitsu Ltd Memory control system
JP2569538B2 (en) * 1987-03-17 1997-01-08 ソニー株式会社 Memory device
US4891795A (en) * 1987-05-21 1990-01-02 Texas Instruments Incorporated Dual-port memory having pipelined serial output
US4894770A (en) * 1987-06-01 1990-01-16 Massachusetts Institute Of Technology Set associative memory
JPS6451512A (en) * 1987-08-22 1989-02-27 Fuji Photo Film Co Ltd Power saving type memory device
JP2645417B2 (en) * 1987-09-19 1997-08-25 富士通株式会社 Non-volatile memory device

Also Published As

Publication number Publication date
JPH03125393A (en) 1991-05-28
DE4020895A1 (en) 1991-04-25
JPH0778994B2 (en) 1995-08-23
US5875132A (en) 1999-02-23
KR970000331B1 (en) 1997-01-08
DE4020895C2 (en) 1994-01-20

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