KR900017202A - 반도체장치와 그 제조방법 - Google Patents

반도체장치와 그 제조방법 Download PDF

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KR900017202A
KR900017202A KR1019890005546A KR890005546A KR900017202A KR 900017202 A KR900017202 A KR 900017202A KR 1019890005546 A KR1019890005546 A KR 1019890005546A KR 890005546 A KR890005546 A KR 890005546A KR 900017202 A KR900017202 A KR 900017202A
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다케오 마에다
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아오이 죠이치
가부시키가이샤 도시바
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Priority claimed from JP63170683A external-priority patent/JP2573319B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
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  • Manufacturing & Machinery (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체장치와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 종래 바이폴라 트랜지스터와 CMOS트랜지스터가 혼재된 LSI의 단면도.
제2도는 바이폴라 트랜지스터와 PMOS트랜지스터에 형성된 N웰영역의 불순물농도 프로우파일을 나타낸 도면.
제3도는 NMOS트랜지스터에 형성된 P웰영역의 불순물농도 프로우파일을 나타낸 도면.
* 도면의 주요부분에 대한 부호의 설명
10 : 반도체기판(P형 실리콘) 11 : 절연막
12 : 개구부(開口部 ; 구멍트인부)
13, 13a : N+매립영역(N+매립 콜렉터영역)
14 : N형 에피택셜층 (제1N웰영역) 15 : N웰영역
16 : P웰영역 16a : P+매립영역
17 : 필드산화막 18 : 이온주입영역
19 : 더미게이트 산화막 20,21 : 챈널이온주입영역
22 : 이온주입영역 23 : 게이트 산화막
24 : 다결정 실리콘층 25 : 소오스영역
26 : 드레인영역 27 : 외부 베이스영역
28 : 소오스영역 29 : 드레인영역
30 : CVD-SiO2막 31 : 소오스영역
32 : 드레인영역 33 : 후산화막
34 : 드레인영역 35 : CVD-SiO2막
36,37,44,45,46 : 접촉구멍 38,39 : 다결정 실리콘층
43 : 층간절연막 47,48,49 : 알루미늄배선

Claims (11)

  1. 바이폴라 트랜지스터와 CMOS트랜지스터를 갖춘 반도체장치에 있어서, 제1도전형 반도체기판(10)과 ; 이 반도체기판(10)상에 형성된 펀치드로우 방지 및 소프트에러 방지용 제1도전용 제1매립영역(16a) ; 이 제1매립영역(16a)의 양측에 각각 인접되면서 상기 반도체기판(10)상에 형성된 제2도전형 제2, 제3매립영역(13a, 13) ; 이 제2도전형 제3매립영역(13)상에 형성되면서 그 표면부에 바이폴라 트랜지스터가 형성되는 제2도전형 제1웰영역(14) ; 상기 제2도전형 제2매립영역(13a)상에 형성되면서 그 표면부에 제1챈널형 MOS트랜지스터가 형성됨과 더불어 상기 제1웰영역(14)의 불순물농도보다 불순물농도가 높은 제2도전형 제2웰영역(15) 및 ; 상기 제1도전형 제1매립영역(16a)상에 형성되면서 그 표면부에 제1챈널형 MOS트랜지스터가 형성되는 제1도전형 제3웰영역(16)을 구비하여 구성된 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 제1웰영역(14)은 상기 제1, 제2, 제3고농도 매립영역(13a, 13, 16a)상에 형성된 에피택셜층을 형성한 다음 불순물을 도입하지 않고서 형성되도록 된 것을 특징으로 하는 반도체장치.
  3. 제2항에 있어서, 상기 에피택셜층은 N형 불순물이 5×1015㎝-3~2×1016㎝-3의 범위로 설정되도록 된 것을 특징으로 하는 반도체장치.
  4. 제3항에 있어서, 상기 N형 불순물로서 인(P)이 사용되는 것을 특징으로 하는 반도체장치.
  5. CMOS트랜지스터 및 바이폴라 트랜지스터를 구비한 주변회로부와 메모리셀부를 갖춘 반도체장치에 있어서, 제1도전형 반도체기판(10)과 ; 이 반도체기판(10)의 주변회로부로 되는 부분상에 형성된 펀치드로우 방지용 제1도전형 제1고농도 매립영역(9a) ; 상기 반도체기판(10)의 메모리셀부로 되는 부분상에 형성되면서 상기 제1고농도 매립영역(9a)의 불순물농도보다도 불순물농도가 높은 소프트에러 방지용 제1도전형 제2고농도 매립영역(8) ; 상기 제1고농도 매립영역(9a)의 양측에 각각 인접되면서 상기 반도체기판(10)상에 형성된 제2도전형 제3, 제4고농도 매립영역(13a, 13b) ; 이 제4고농도 매립영역(13b)상에 형성되면서 그 표면부에 바이폴라 트랜지스터가 형성되는 제2도전형 제1웰영역(14) ; 상기 제3고농도 매립영역(13a)상에 형성되면서 그 표면부에 제1챈널형 MOS트랜지스터가 형성됨과 더불어 상기 제1웰영역(14)의 불순물농도보다도 불순물농도가 높은 제2도전형 제2웰영역(15a, 15b) 및 ; 상기 제1, 제2고농도 매립영역(9a, 8)상에 각각 형성되면서 각 표면부에 제2챈널형 MOS트랜지스터가 형성되는 제1도전형 제3, 제4웰영역(16a, 16b)을 구비하여 구성된 것을 특징으로 하는 반도체장치.
  6. 제5항에 있어서, 상기 제1웰영역(14)은 상기 제1, 제2, 제3, 제4 고농도 매립영역(9a, 8, 13a, 13b)상에 형성되는 에피택셜층을 형성한 다음 불순물을 도입하지 않고서 형성되도록 한 것을 특징으로 하는 반도체장치.
  7. 제6항에 있어서, 상기 에피택셜층은 N형 불순물이 5×1015㎝-3~2×1016㎝-3의 범위로 설정되도록 된 것을 특징으로 하는 반도체장치.
  8. 제6항에 있어서, 상기 N형 불순물로서 인(P)이 사용되는 것을 특징으로 하는 반도체장치.
  9. 제5항에 있어서, 상기 제2고농도 매립영역(8)은 근접되는 제1도전형 매립영역(13c)으로부터 2㎛이상 떨어져 형성되는 것을 특징으로 하는 반도체장치.
  10. 바이폴라 트랜지스터와 CMOS트랜지스터를 갖춘 반도체장치의 제조방법에 있어서, 제1도전형 반도체기판(10)을 준비하는 단계와, 이 반도체기판(10)상에 제1도전형 제1매립영역(16a)과, 이 제1매립영역(16a)의 양측에 제2도전형 제2, 제3매립영역(13a, 13)을 형성하는 단계, 상기 제1, 제2, 제3 매립영역(16a, 13a, 13)상에 제2도전형 에피택셜층을 형성하는 단계, 이 에피택셜층내의 상기 제2고농도 매립영역(13a)상의 부분에 제2도 전형 불순물을 도입시키고, 상기 에피택셜층내의 상기 제1고농도 매립영역(16a)상의 부분에 제1도전형 불순물을 도입시키며, 상기 제3매립영역(13)상의 상기 에피택셜층부분을 제1웰영역(14)으로 형성하고, 상기 제1매립영역(13a)상의 상기 에피택셜층의 부분을 상기 제1웰영역(14)의 불순물농도보다도 불순물농도가 높은 제2웰영역(15)으로 형성하며, 상기 제2매립영역(16a)상의 상기 에피택셜층부분을 제3웰영역(16)으로 형성하는 단계 및, 상기 제1웰영역(14)에 바이폴라 트랜지스터를, 상기 제2, 제3웰영역(15, 16)에 CMOS트랜지스터를 각각 1050℃의 온도 이상에서 10분 이하의 열처리를 수행함으로써 형성하는 단계를 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  11. 제10항에 있어서, 상기 제1고농도 매립영역(16a)에 함유되는 불순물로서 보론(B)를 사용하는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890005546A 1988-04-27 1989-04-27 반도체장치와 그 제조방법 KR920005511B1 (ko)

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Application Number Priority Date Filing Date Title
JP63-104861 1988-04-27
JP63104861A JP2889246B2 (ja) 1988-04-27 1988-04-27 半導体装置
JP63-170683 1988-07-08
JP63170683A JP2573319B2 (ja) 1988-07-08 1988-07-08 半導体装置の製造方法

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KR900017202A true KR900017202A (ko) 1990-11-15
KR920005511B1 KR920005511B1 (ko) 1992-07-06

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JP3282172B2 (ja) * 1994-07-29 2002-05-13 ソニー株式会社 ＢｉＭＯＳ半導体装置の製造方法
JPH03296260A (ja) * 1990-04-16 1991-12-26 Toshiba Corp Ｍｏｓ型半導体装置
US5001073A (en) * 1990-07-16 1991-03-19 Sprague Electric Company Method for making bipolar/CMOS IC with isolated vertical PNP
EP0809286B1 (en) * 1996-05-14 2003-10-01 STMicroelectronics S.r.l. A process for the fabrication of semiconductor devices having various buried regions
GB2374456A (en) * 2000-12-09 2002-10-16 Esm Ltd High-voltage metal oxide semiconductor device and method of forming the device
JP2003197908A (ja) * 2001-09-12 2003-07-11 Seiko Instruments Inc 半導体素子及びその製造方法

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DE68929131D1 (de) 2000-02-10
DE68929131T2 (de) 2000-06-15
EP0339637B1 (en) 2000-01-05
EP0339637A3 (en) 1992-09-23
DE68929415T2 (de) 2003-01-16
EP0339637A2 (en) 1989-11-02
EP0723295B1 (en) 2002-07-10
KR920005511B1 (ko) 1992-07-06
EP0723295A1 (en) 1996-07-24
US5093707A (en) 1992-03-03
DE68929415D1 (de) 2002-08-14

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