JPH0671067B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0671067B2
JPH0671067B2 JP60258506A JP25850685A JPH0671067B2 JP H0671067 B2 JPH0671067 B2 JP H0671067B2 JP 60258506 A JP60258506 A JP 60258506A JP 25850685 A JP25850685 A JP 25850685A JP H0671067 B2 JPH0671067 B2 JP H0671067B2
Authority
JP
Japan
Prior art keywords
semiconductor device
conductivity type
impurity layer
voltage
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60258506A
Other languages
English (en)
Other versions
JPS62119958A (ja
Inventor
五郎 橘川
清男 伊藤
陵一 堀
隆夫 渡部
勝博 下東
紀之 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP60258506A priority Critical patent/JPH0671067B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to SG1996009506A priority patent/SG59995A1/en
Priority to EP86906927A priority patent/EP0245515B1/en
Priority to KR1019870700554A priority patent/KR950007573B1/ko
Priority to PCT/JP1986/000579 priority patent/WO1987003423A1/ja
Priority to DE3650613T priority patent/DE3650613T2/de
Priority to KR1019910701145A priority patent/KR950002273B1/ko
Priority to KR1019910701144A priority patent/KR950007575B1/ko
Publication of JPS62119958A publication Critical patent/JPS62119958A/ja
Priority to US07/645,351 priority patent/US5148255A/en
Priority to US07/769,680 priority patent/US5324982A/en
Priority to US08/229,340 priority patent/US5386135A/en
Publication of JPH0671067B2 publication Critical patent/JPH0671067B2/ja
Priority to US08/352,238 priority patent/US5497023A/en
Priority to US08/574,110 priority patent/US6208010B1/en
Priority to HK98102615A priority patent/HK1003586A1/xx
Priority to US10/115,101 priority patent/US6740958B2/en
Priority to US10/377,717 priority patent/US6864559B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は素子相互間がそれぞれの素子の形成されている
不純物層によって電気的に分離され、それぞれの不純物
層に異なる電圧を印加する半導体装置に関するものであ
る。
〔従来の技術〕
LSIの入出力端子は外部回路と直接接続されるため、電
源電圧以上もしくは0V以下（外部電源電圧範囲外）の外
来雑音、例えばサージ雑音が入力される。このような外
来雑音がチップの入出力端子に接続されるMOSトランジ
スタに印加されると、そのドレインと基板又はウェル間
に順バイアスがかかることになり、少数キャリアが基板
又はウェルに注入される。この少数キャリアの平均自由
行程は通常数百μｍにも達するため、他の素子に到達す
る確率が高い。その結果、SRAMやDRAMのメモリセル記憶
情報が破壊される問題が生じる。
このような問題を解決したものとして、例えば特開昭59
−22359号公報に記載がある。これを第７図に示す。
第７図では基板に複数のウェルを形成してそれぞれのウ
ェルに異なる電圧を印加している。具体的にはメモリセ
ルマトリックス用のウェルと入出力制御回路等のメモリ
セル駆動回路用のウェルを具備し、メモリセルマトリッ
クス用にウェルに0Vを、メモリセル駆動回路用のウェル
に−２〜−3Vを印加する記載がある。これにより、 メモリセルマトリックス用のウェルに形成されたメモ
リセルを構成するMOSFETは、そのドレインとウェル間の
接合容量が大きく、リーク電流の基になる再結合電流が
少ない、従ってメモリ保持時間が長くなる、 メモリセル駆動回路用のウェルに形成されたメモリセ
ル駆動回路を構成するMOSFETは、その入力端子にサージ
電圧が印加されても、少数キャリアがウェルに注入され
ない、 という互いに相反する効果を持つ２つのMOSトランジス
タを同時に得ることができる。
すなわち、 ′リーク電流の基になる再結合電流が少ないMOSトラ
ンジスタと、 ′入力端子にサージ電圧が印加されても、少数キャリ
アがウェルに注入されないMOSトランジスタを同時に得
ることができる。
〔発明が解決しようとする課題〕
ところが、第７図に示す構造では例えば基板の導電型を
ｎ型、ウェルの導電型をｐ型とすると、それぞれのウェ
ルの電圧を変えることにより上述の′のチャネルMOS
トランジスタと上述の′のｎチャネルMOSトランジス
タを同時に形成することができるが、ｐチャネルMOSト
ランジスタについてはｎ型基板にのみ形成されるので上
述の′′のどちらか一方のものしか形成できないと
いう問題があることが発明者らの検討により明らかにさ
れた。
そこで本発明では、２つのｐチャネルMOSトランジスタ
及び２つのｎチャネルMOSトランジスタのそれぞれで最
適な特性を発揮しうる半導体装置を提供することを目的
とする。
〔課題を解決するための手段〕
そこで本発明では、例えば第１図に示すように、基板
（ｐ−Sub）と、該基板の主表面の第１の領域に設けら
れた第１の導電型の第１の不純物層（nW1）と、上記基
板の主表面の上記第１の領域と異なる第２の領域に設け
られた上記第１の導電型の第２の不純物層（nW2）と、
上記第１の不純物層内の第３の領域に形成された上記第
１の導電型と異なる第２の導電型の第３の不純物層（nW
1）と、上記基板の主表面の上記第１の領域及び上記第
２の領域と異なる第４の領域に形成された上記第２の導
電型の第４の不純物層Yp−Sub）と、上記第１の不純物
層（nW1）に形成された第２導電型チャネルの第１のMOS
トランジスタ（pMOS1）と、上記第２の不純物層（nW2）
に形成された上記第２導電型チャネルの第２のMOSトラ
ンジスタ（pMOS2）と、上記第３の不純物層（pW1）に形
成された第１導電型チャネルの第３のMOSトランジスタ
（nMOS1）と、上記第４の領域に形成された上記第１導
電型チャネルの第４のMOSトランジスタ（nMOS3）とを有
し、 上記第１の不純物層（nW1）に印加される第１の電圧（V
BB3）と上記第２の不純物層（nW2）に印加される第２の
電圧（VBB5）と上記第３の不純物層（pW1）に印加され
る第３の電圧（VBB2）と上記第４の不純物層（ｐ−Su
b）に印加される第４の電圧（VBB1）がそれぞれ互いに
異なる構造とした。
〔作用〕
第１、第２のMOSトランジスタが異なる不純物層に形成
され、また同様に第３、第４のMOSトランジスタが異な
る不純物層に形成され、かつ不純物層ごとに異なる電圧
が印加されているので、ｐチャネル及びｎチャネルMOS
トランジスタのいずれについても、それぞれ目的に応じ
て最適な特性のMOSトランジスタが得られる。
一例として、不純物層に印加する電圧によって、第１の
MOSトランジスタはリーク電流の基になる再結合電流が
少なく、第２のMOSトランジスタは少数キャリアの注入
が起こりにくいという特性となる。さらにそれぞれのMO
Sトランジスタが異なる不純物層に形成されているの
で、第１のMOSトランジスタ又は第２のMOSトランジスタ
の一方から発生したノイズは他方のMOSトランジスタの
出力にほとんど混入しない。同様に、第３のMOSトラン
ジスタ又は第４のMOSトランジスタの一方から発生した
ノイズは他方のMOSトランジスタの出力にほとんど混入
しない。
〔実施例〕
以下、本発明の詳細を実施例により説明する。
第１図は本発明の実施例の一つである。この図ではｐ型
基板（ｐ−Sub）上に３個のｎウェル（nW1,nW2,nW3）を
作り、さらにnW1,nW2内にｐウェル（pW1,pW2）を作る。
その後ｐウェル（pW1,pW2）とｐ−Sub内にｎチャネルMO
Sトランジスタ（nMOS1,nMOS2,nMOS3）を作る。またｎウ
ェル（nW1,nW2,nW3）内にｐチャネルMOSトランジスタ
（pMOS1,pMOS2,pMOS3）を作る。この構成においてnMOS
用のｐ型分離層に電圧ＶBB2,VBB4,VBB1を印加する。ま
たpMOS用のｎ型分離層に電圧ＶBB3,VBB5,VBB6を印加す
る。これらＶBB2,VBB4,VBB1あるいはＶBB3,VBB5,VBB6に
は使用回路に応じて相異なる２値以上の電圧を印加す
る。例えばＶBB2,VBB4,VBB1としてはGND（0V），−3V
を、またＶBB3,VBB5,VBB6にはVCC（＋5V）,VCC＋α（＋
7V）を印加する。こうしてnMOS,pMOSの各々の分離層に
任意の電圧を印加する。なお第１図では各々のウェル内
には１個のMOSトランジスタのみを図示したが、必要に
応じて複数のトランジスタを設けてもよい。またウェル
の数も必要に応じて増減すれば良い。さらに基板やウェ
ルの極性を反転して、ｎ−Sub上にｐウェルをつくり、
その中にｎウェルを形成する構成にも適用できることは
明らかである。
第２図は一般的なメモリ（ダイナミックRAM,スタティッ
クRAM,ROM等を含む）のブロック図である。ADRはアドレ
ス入力、CSはチップセレクト入力、WEはライトイネーブ
ル入力、DIはデータ入力、DOはデータ出力である。ブロ
ックＩはアドレスバッファとデコーダ、ドライバ回路を
示す。ブロックＣは制御回路、書き込み信号発生回路を
示す。ブロックMCはメモリセルアレーを示す。
第３図に示した破線は第２図で示した破線に対応してお
り、ブロックMCとその他のブロックに分離している。チ
ップ内に基板にバイアス回路を内蔵し、その２出力Ｖ
BBM1,VBBM2をブロックMC以外の周辺回路に印加し、メモ
リセルアレーにはVCCとGND電位をＶBBM3,VBBM4として印
加する。基板バイアス発生回路構成は既に1976 ISSCC p
p.138〜139あるいは特開昭51−11584号に開示されてい
る。これにより、周辺回路のpMOSの分離領域（ｎウェ
ル）にはＶBBM1（＋7V）、nMOSの分離領域（ｐウェル）
にはＶBBM2（−3V）、またメモリセルアレーのpMOSのｎ
ウェルにはVCCを、メモリセルアレーのnMOSのｐウェル
には0Vを印加する。こうして入出力回路の分離領域には
絶対値の大きい電圧を供給することにより、入出力信号
のオーバーシュート、アンダーシュートにも安定で、ま
た接合容量（MOSトランジスタのソース、ドレイン−基
板間容量）を減少でき、またメモリセルアレーではリー
ク電流を少なくできる。
以後、第４図〜第６図においてもその役割に従って第３
図のＶBBM1,VBBM2,VBBM3,VBBM4の記号を用いる。
第４図〜第６図にMOSダイナミックRAMの入力回路とダイ
ナミックメモリセルの断面構造を示す。なおここではメ
モリセルをダイナミック型セルとしたが、MOSスタティ
ック型メモリセルにも同様に適用できる。
第４図の実施例では、入力保護回路（ｎ型拡散抵抗とnM
OSダイオード）と入力回路のnMOSをｐウェル（pW）の中
に、入力回路のpMOSをｎウェル（nW）の中に形成し、nM
OSのメモリセルはｐ−Sub上に形成している。そのた
め、例えば入力回路の仕様を満たすためにＶBBM2を−3V
に、メモリセルの耐ソフトエラーのためにＶBBM4を0Vに
する。入力保護回路とメモリセルがｎウェルによって分
離されているので、入力保護回路で生じる雑音がメモリ
セルに届くことはない。
なお、メモリセルの下部の破線は、耐α線のためのｐ型
の高濃度層である。
第５図では、入力保護回路のみをｐウェル（pW）内に設
けたものを示す。
第６図では、メモリセルをｐウェル（pW）内に設けたも
のを示す。
第４図〜第６図では、製造のしやすさなど必要に応じて
いずれかのデバイス構造をとればよい。
〔発明の効果〕
以上、本発明によれば、同一基板上にｐチャネル及びｎ
チャネルMOSトランジスタのいずれについても、それぞ
れ目的に応じて最適な特性のMOSトランジスタが得られ
る。
【図面の簡単な説明】
第１図は本発明をCMOS回路に用いた実施例、第２図はメ
モリのブロック図、第３図はメモリへの基板分離電圧の
印加を示す実施例、第４図〜第６図は本発明をMOSダイ
ナミックメモリに用いた実施例、第７図は従来の技術を
示す図である。
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡部 隆夫 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 下東 勝博 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 本間 紀之 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭49−128684（ＪＰ，Ａ)

Claims (11)

    【特許請求の範囲】
  1. 【請求項１】基板と、該基板の主表面の第１の領域に設
    けられた第１の導電型の第１の不純物層と、上記基板の
    主表面の上記第１の領域と異なる第２の領域に設けられ
    た上記第１の導電型の第２の不純物層と、上記第１の不
    純物層内の第３の領域に形成された上記第１の導電型と
    異なる第２の導電型の第３の不純物層と、上記基板の主
    表面の上記第１の領域及び上記第２の領域と異なる第４
    の領域に形成された上記第２の導電型の第４の不純物層
    と、上記第１の不純物層に形成された第２導電型チャネ
    ルの第１のMOSトランジスタと、上記第２の不純物層に
    形成された上記第２導電型チャネルの第２のMOSトラン
    ジスタと、上記第３の不純物層に形成された第１の導電
    型チャネルの第３のMOSトランジスタと、上記第４の領
    域に形成された上記第１導電型チャネルの第４のMOSト
    ランジスタとを有し、 上記第１の不純物層に印加される第１の電圧と上記第２
    の不純物層に印加される第２の電圧と上記第３の不純物
    層に印加される第３の電圧と上記第４の不純物層に印加
    される第４の電圧はそれぞれ互いに異なる電圧であるこ
    とを特徴とする半導体装置。
  2. 【請求項２】特許請求の範囲第１項に記載の半導体装置
    において、 上記第３のトランジスタは外部から入力される雑音電圧
    による誤動作を防ぐ入力保護回路を構成することを特徴
    とする半導体装置。
  3. 【請求項３】特許請求の範囲第２項に記載の半導体装置
    において、 上記第３のトランジスタのゲートとソースは短絡され、
    そのドレインには抵抗を介して上記外部からの雑音電圧
    が入力されることを特徴とする半導体装置。
  4. 【請求項４】特許請求の範囲第２項又は第３項の何れか
    に記載の半導体装置において、 上記第３の電圧は外部電源電圧範囲とは異なる電圧であ
    り、かつ上記基板上の電圧変換手段により発生されるこ
    とを特徴とする半導体装置。
  5. 【請求項５】特許請求の範囲第１項に記載の半導体装置
    において、 上記第４のトランジスタは外部から入力される雑音電圧
    による誤動作を防ぐ入力保護回路を構成することを特徴
    とする半導体装置。
  6. 【請求項６】特許請求の範囲第５項に記載の半導体装置
    において、 上記第４のトランジスタのゲートとソースは短絡され、
    そのドレインには抵抗を介して上記外部からの雑音電圧
    が入力されることを特徴とする半導体装置。
  7. 【請求項７】特許請求の範囲第５項又は第６項の何れか
    に記載の半導体装置において、 上記第４の電圧は外部電源電圧範囲とは異なる電圧であ
    り、かつ上記基板上の電圧変換手段により発生されるこ
    とを特徴とする半導体装置。
  8. 【請求項８】特許請求の範囲第１項、第５項乃至第７項
    の何れかに記載の半導体装置において、 上記第３のトランジスタのソース又はドレインが容量と
    接続されてメモリセルを構成することを特徴とする半導
    体装置。
  9. 【請求項９】特許請求の範囲第１項乃至第４項の何れか
    に記載の半導体装置において、 上記第４のトランジスタのソース又はトレイソが容量と
    接続されてメモリセルを構成することを特徴とする半導
    体装置。
  10. 【請求項１０】特許請求の範囲第１項乃至第９項の何れ
    かに記載の半導体装置において、 上記第１の導電型はｐ型であり、上記第２の導電型はｎ
    型であることを特徴とする半導体装置。
  11. 【請求項１１】特許請求の範囲第１項乃至第９項の何れ
    かに記載の半導体装置において、 上記第１の導電型はｎ型であり、上記第２の導電型はｐ
    型であることを特徴とする半導体装置。
JP60258506A 1985-09-25 1985-11-20 半導体装置 Expired - Lifetime JPH0671067B2 (ja)

Priority Applications (16)

Application Number Priority Date Filing Date Title
JP60258506A JPH0671067B2 (ja) 1985-11-20 1985-11-20 半導体装置
SG1996009506A SG59995A1 (en) 1985-11-20 1986-11-12 Semiconductor device
EP86906927A EP0245515B1 (en) 1985-11-20 1986-11-12 Semiconductor device
KR1019870700554A KR950007573B1 (ko) 1985-11-20 1986-11-12 회로를 웰로 분리한 반도체장치
PCT/JP1986/000579 WO1987003423A1 (en) 1985-11-20 1986-11-12 Semiconductor device
DE3650613T DE3650613T2 (de) 1985-11-20 1986-11-12 Halbleiteranordnung
KR1019910701145A KR950002273B1 (ko) 1985-11-20 1986-11-12 회로를 웰로 분리한 반도체장치
KR1019910701144A KR950007575B1 (ko) 1985-11-20 1986-11-12 회로를 웰로 분리한 반도체장치
US07/645,351 US5148255A (en) 1985-09-25 1991-01-23 Semiconductor memory device
US07/769,680 US5324982A (en) 1985-09-25 1991-10-02 Semiconductor memory device having bipolar transistor and structure to avoid soft error
US08/229,340 US5386135A (en) 1985-09-25 1994-04-12 Semiconductor CMOS memory device with separately biased wells
US08/352,238 US5497023A (en) 1985-09-25 1994-12-08 Semiconductor memory device having separately biased wells for isolation
US08/574,110 US6208010B1 (en) 1985-09-25 1995-12-18 Semiconductor memory device
HK98102615A HK1003586A1 (en) 1985-11-20 1998-03-27 Semiconductor device
US10/115,101 US6740958B2 (en) 1985-09-25 2002-04-04 Semiconductor memory device
US10/377,717 US6864559B2 (en) 1985-09-25 2003-03-04 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60258506A JPH0671067B2 (ja) 1985-11-20 1985-11-20 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4311665A Division JPH0740591B2 (ja) 1992-11-20 1992-11-20 半導体装置

Publications (2)

Publication Number Publication Date
JPS62119958A JPS62119958A (ja) 1987-06-01
JPH0671067B2 true JPH0671067B2 (ja) 1994-09-07

Family

ID=17321153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60258506A Expired - Lifetime JPH0671067B2 (ja) 1985-09-25 1985-11-20 半導体装置

Country Status (7)

Country Link
EP (1) EP0245515B1 (ja)
JP (1) JPH0671067B2 (ja)
KR (1) KR950007573B1 (ja)
DE (1) DE3650613T2 (ja)
HK (1) HK1003586A1 (ja)
SG (1) SG59995A1 (ja)
WO (1) WO1987003423A1 (ja)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173294A (en) * 1986-11-18 1992-12-22 Research Foundation Of State University Of New York Dna probe for the identification of haemophilus influenzae
GB2199695B (en) * 1987-01-06 1990-07-25 Samsung Semiconductor Inc Dynamic random access memory with selective well biasing
GB8713388D0 (en) * 1987-06-08 1987-07-15 Philips Electronic Associated Semiconductor device
JPH01129451A (ja) * 1987-11-16 1989-05-22 Fujitsu Ltd 半導体装置
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法
US5093707A (en) * 1988-04-27 1992-03-03 Kabushiki Kaisha Toshiba Semiconductor device with bipolar and cmos transistors
US5297097A (en) 1988-06-17 1994-03-22 Hitachi Ltd. Large scale integrated circuit for low voltage operation
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
JP2845493B2 (ja) * 1988-06-24 1999-01-13 株式会社東芝 半導体装置
JPH0744231B2 (ja) * 1989-11-10 1995-05-15 株式会社東芝 半導体集積回路およびその製造方法
JPH03153070A (ja) * 1989-11-10 1991-07-01 Seiko Epson Corp 半導体装置
JPH07109860B2 (ja) * 1990-01-19 1995-11-22 株式会社東芝 電荷転送デバイスを含む半導体装置およびその製造方法
JPH07109861B2 (ja) * 1990-01-19 1995-11-22 株式会社東芝 電荷転送デバイスを含む半導体装置およびその製造方法
US5260228A (en) * 1990-01-19 1993-11-09 Kabushiki Kaisha Toshiba Method of making a semiconductor device having a charge transfer device, MOSFETs, and bipolar transistors
WO1991016728A1 (en) * 1990-04-13 1991-10-31 Kabushiki Kaisha Toshiba Substrate structure of a semiconductor device
JPH03296260A (ja) * 1990-04-16 1991-12-26 Toshiba Corp Ｍｏｓ型半導体装置
JPH0423147U (ja) * 1990-06-20 1992-02-26
JP2609743B2 (ja) * 1990-06-28 1997-05-14 三菱電機株式会社 半導体装置
KR940009357B1 (ko) * 1991-04-09 1994-10-07 삼성전자주식회사 반도체 장치 및 그 제조방법
US5248624A (en) * 1991-08-23 1993-09-28 Exar Corporation Method of making isolated vertical pnp transistor in a complementary bicmos process with eeprom memory
JPH05129425A (ja) * 1991-10-30 1993-05-25 Nec Kansai Ltd 半導体装置およびその製造方法
US5595925A (en) * 1994-04-29 1997-01-21 Texas Instruments Incorporated Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein
JP4037470B2 (ja) 1994-06-28 2008-01-23 エルピーダメモリ株式会社 半導体装置
TW362275B (en) * 1996-09-05 1999-06-21 Matsushita Electronics Corp Semiconductor device and method for producing the same
US6107672A (en) * 1997-09-04 2000-08-22 Matsushita Electronics Corporation Semiconductor device having a plurality of buried wells
US6901006B1 (en) 1999-07-14 2005-05-31 Hitachi, Ltd. Semiconductor integrated circuit device including first, second and third gates
JP4012341B2 (ja) 1999-07-14 2007-11-21 株式会社ルネサステクノロジ 半導体集積回路装置
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
TWI230392B (en) 2001-06-18 2005-04-01 Innovative Silicon Sa Semiconductor device
JP2004311684A (ja) * 2003-04-07 2004-11-04 Sanyo Electric Co Ltd 半導体装置
US20040228168A1 (en) 2003-05-13 2004-11-18 Richard Ferrant Semiconductor memory device and method of operating same
US7335934B2 (en) 2003-07-22 2008-02-26 Innovative Silicon S.A. Integrated circuit device, and method of fabricating same
US7606066B2 (en) 2005-09-07 2009-10-20 Innovative Silicon Isi Sa Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US7683430B2 (en) 2005-12-19 2010-03-23 Innovative Silicon Isi Sa Electrically floating body memory cell and array, and method of operating or controlling same
US7492632B2 (en) 2006-04-07 2009-02-17 Innovative Silicon Isi Sa Memory array having a programmable word length, and method of operating same
US7933142B2 (en) 2006-05-02 2011-04-26 Micron Technology, Inc. Semiconductor memory cell and array using punch-through to program and read same
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7542340B2 (en) 2006-07-11 2009-06-02 Innovative Silicon Isi Sa Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
KR101406604B1 (ko) 2007-01-26 2014-06-11 마이크론 테크놀로지, 인코포레이티드 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 ｄｒａｍ 트랜지스터
WO2009031052A2 (en) 2007-03-29 2009-03-12 Innovative Silicon S.A. Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8085594B2 (en) 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US8194487B2 (en) 2007-09-17 2012-06-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8349662B2 (en) 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells
US8014195B2 (en) 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8189376B2 (en) 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US7957206B2 (en) 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7933140B2 (en) 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7924630B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US8223574B2 (en) 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
US8213226B2 (en) 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8319294B2 (en) 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
WO2010102106A2 (en) 2009-03-04 2010-09-10 Innovative Silicon Isi Sa Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
CN102365628B (zh) 2009-03-31 2015-05-20 美光科技公司 用于提供半导体存储器装置的技术
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8508994B2 (en) 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8498157B2 (en) 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9076543B2 (en) 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8199595B2 (en) 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8174881B2 (en) 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US8416636B2 (en) 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8411513B2 (en) 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8369177B2 (en) 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
KR20130007609A (ko) 2010-03-15 2013-01-18 마이크론 테크놀로지, 인크. 반도체 메모리 장치를 제공하기 위한 기술들
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916430A (en) * 1973-03-14 1975-10-28 Rca Corp System for eliminating substrate bias effect in field effect transistor circuits
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
JPS57194565A (en) * 1981-05-25 1982-11-30 Toshiba Corp Semiconductor memory device
JPS5922359A (ja) * 1982-07-29 1984-02-04 Nec Corp 集積化半導体記憶装置
JPS59143359A (ja) * 1983-01-31 1984-08-16 ストレイジ、テクノロジ−、パ−トナ−ズ Ｃｍｏｓ集積回路
JPS59144168A (ja) * 1983-02-07 1984-08-18 Hitachi Ltd バイポ−ラｍｏｓ半導体装置及びその製造法

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Publication number Publication date
KR950007573B1 (ko) 1995-07-12
WO1987003423A1 (en) 1987-06-04
KR880700468A (ko) 1988-03-15
JPS62119958A (ja) 1987-06-01
SG59995A1 (en) 1999-02-22
EP0245515A1 (en) 1987-11-19
EP0245515B1 (en) 1997-04-16
EP0245515A4 (en) 1990-12-27
DE3650613D1 (de) 1997-05-22
DE3650613T2 (de) 1997-10-23
HK1003586A1 (en) 1998-10-30

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