DE68929415T2 - Verfahren zur Herstellung eines BiCMOS-Halbleiterbauteils mit vergrabener Schicht - Google Patents

Verfahren zur Herstellung eines BiCMOS-Halbleiterbauteils mit vergrabener Schicht

Info

Publication number
DE68929415T2
DE68929415T2 DE68929415T DE68929415T DE68929415T2 DE 68929415 T2 DE68929415 T2 DE 68929415T2 DE 68929415 T DE68929415 T DE 68929415T DE 68929415 T DE68929415 T DE 68929415T DE 68929415 T2 DE68929415 T2 DE 68929415T2
Authority
DE
Germany
Prior art keywords
producing
semiconductor component
buried layer
bicmos semiconductor
bicmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929415T
Other languages
English (en)
Other versions
DE68929415D1 (de
Inventor
Takeo Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63104861A external-priority patent/JP2889246B2/ja
Priority claimed from JP63170683A external-priority patent/JP2573319B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68929415D1 publication Critical patent/DE68929415D1/de
Publication of DE68929415T2 publication Critical patent/DE68929415T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE68929415T 1988-04-27 1989-04-27 Verfahren zur Herstellung eines BiCMOS-Halbleiterbauteils mit vergrabener Schicht Expired - Fee Related DE68929415T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63104861A JP2889246B2 (ja) 1988-04-27 1988-04-27 半導体装置
JP63170683A JP2573319B2 (ja) 1988-07-08 1988-07-08 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE68929415D1 DE68929415D1 (de) 2002-08-14
DE68929415T2 true DE68929415T2 (de) 2003-01-16

Family

ID=26445235

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68929415T Expired - Fee Related DE68929415T2 (de) 1988-04-27 1989-04-27 Verfahren zur Herstellung eines BiCMOS-Halbleiterbauteils mit vergrabener Schicht
DE68929131T Expired - Fee Related DE68929131T2 (de) 1988-04-27 1989-04-27 LSI-Halbleiteranordnung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE68929131T Expired - Fee Related DE68929131T2 (de) 1988-04-27 1989-04-27 LSI-Halbleiteranordnung

Country Status (4)

Country Link
US (1) US5093707A (de)
EP (2) EP0339637B1 (de)
KR (1) KR920005511B1 (de)
DE (2) DE68929415T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3282172B2 (ja) * 1994-07-29 2002-05-13 ソニー株式会社 ＢｉＭＯＳ半導体装置の製造方法
JPH03296260A (ja) * 1990-04-16 1991-12-26 Toshiba Corp Ｍｏｓ型半導体装置
US5001073A (en) * 1990-07-16 1991-03-19 Sprague Electric Company Method for making bipolar/CMOS IC with isolated vertical PNP
EP0809286B1 (de) * 1996-05-14 2003-10-01 STMicroelectronics S.r.l. Verfahren zur Herstellung von Halbleiterbauteilen mit verschiedenartigen vergrabenen Dotierungsgebieten
GB2374456A (en) * 2000-12-09 2002-10-16 Esm Ltd High-voltage metal oxide semiconductor device and method of forming the device
JP2003197908A (ja) * 2001-09-12 2003-07-11 Seiko Instruments Inc 半導体素子及びその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155562A (en) * 1980-05-06 1981-12-01 Nec Corp Manufacture of semiconductor device
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPS59177960A (ja) * 1983-03-28 1984-10-08 Hitachi Ltd 半導体装置およびその製造方法
JPS6080267A (ja) * 1983-10-07 1985-05-08 Toshiba Corp 半導体集積回路装置の製造方法
EP0197948A4 (de) * 1984-09-28 1988-01-07 Motorola Inc Schutz gegen die entladung einer verarmungszone eines ladungsspeichers.
JPH073811B2 (ja) * 1985-04-12 1995-01-18 株式会社日立製作所 半導体記憶装置
JPH0834244B2 (ja) * 1985-06-19 1996-03-29 三洋電機株式会社 半導体集積回路装置
JPH0671067B2 (ja) * 1985-11-20 1994-09-07 株式会社日立製作所 半導体装置
JPH0628296B2 (ja) * 1985-10-17 1994-04-13 日本電気株式会社 半導体装置の製造方法
JPH0770606B2 (ja) * 1985-11-29 1995-07-31 株式会社日立製作所 半導体装置
JPS62291165A (ja) * 1986-06-11 1987-12-17 Nec Corp 半導体装置
US4929570A (en) * 1986-10-06 1990-05-29 National Semiconductor Corporation Selective epitaxy BiCMOS process
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法
JPS6410656A (en) * 1987-07-03 1989-01-13 Hitachi Ltd Complementary type semiconductor device

Also Published As

Publication number Publication date
DE68929131D1 (de) 2000-02-10
DE68929131T2 (de) 2000-06-15
EP0339637B1 (de) 2000-01-05
EP0339637A3 (de) 1992-09-23
EP0339637A2 (de) 1989-11-02
EP0723295B1 (de) 2002-07-10
KR920005511B1 (ko) 1992-07-06
KR900017202A (ko) 1990-11-15
EP0723295A1 (de) 1996-07-24
US5093707A (en) 1992-03-03
DE68929415D1 (de) 2002-08-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee