JPS56155562A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56155562A JPS56155562A JP5974780A JP5974780A JPS56155562A JP S56155562 A JPS56155562 A JP S56155562A JP 5974780 A JP5974780 A JP 5974780A JP 5974780 A JP5974780 A JP 5974780A JP S56155562 A JPS56155562 A JP S56155562A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion
- transistor
- diffused
- linear
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title 1
- 238000009792 diffusion process Methods 0.000 abstract 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 229910020489 SiO3 Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To contrive the mass-production of epitaxial wafers having no outward diffusion by diffusing impurities with slow diffusion speed after diffusing impurities having a high diffusion factor. CONSTITUTION:An opening is provided at an SiO3 3 on a P type Si substrate 1 and P (high diffusion speed) is diffused to make an N layer 2. Then, Sb (low diffusion speed) is diffused by applying a predetermined mask and an N layer 4 is stacked on the N layer 2 to push in the N layer 2. At that time, the buried layer 4a of a bipolar transistor for a linear circuit is simultaneously formed. The SiO2 3 is removed by HF to stack an expitaxial layer 5 on the buried layer 4a and an N-P-N transistor in an I<2>L section 21 and an N-P-N transistor in a linear circuit section 22 are formed by a conventional method. In this way, a surface concentration can equally be controlled at a low level by slowly diffusing P at a relatively low temperature prior to As diffusion. And in epitaxial formation, outward diffusion can be reduced at the same extent for ion implantation and the linear and digital circuits having few crystal dettect and good characteristics are provided on one chip easily by using a bipolar element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5974780A JPS56155562A (en) | 1980-05-06 | 1980-05-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5974780A JPS56155562A (en) | 1980-05-06 | 1980-05-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56155562A true JPS56155562A (en) | 1981-12-01 |
Family
ID=13122130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5974780A Pending JPS56155562A (en) | 1980-05-06 | 1980-05-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56155562A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0723295A1 (en) * | 1988-04-27 | 1996-07-24 | Kabushiki Kaisha Toshiba | BICMOS semiconductor device with buried layer |
-
1980
- 1980-05-06 JP JP5974780A patent/JPS56155562A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0723295A1 (en) * | 1988-04-27 | 1996-07-24 | Kabushiki Kaisha Toshiba | BICMOS semiconductor device with buried layer |
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