KR860006137A - 반도체 집적회로 - Google Patents

반도체 집적회로

Info

Publication number
KR860006137A
KR860006137A KR1019860000085A KR860000085A KR860006137A KR 860006137 A KR860006137 A KR 860006137A KR 1019860000085 A KR1019860000085 A KR 1019860000085A KR 860000085 A KR860000085 A KR 860000085A KR 860006137 A KR860006137 A KR 860006137A
Authority
KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
semiconductor
circuit
integrated
Prior art date
Application number
KR1019860000085A
Other languages
English (en)
Other versions
KR890004958B1 (ko
Inventor
다까야스 사꾸라이
데즈야 이즈까
Original Assignee
가부시끼가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 도오시바 filed Critical 가부시끼가이샤 도오시바
Publication of KR860006137A publication Critical patent/KR860006137A/ko
Application granted granted Critical
Publication of KR890004958B1 publication Critical patent/KR890004958B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
KR1019860000085A 1985-01-26 1986-01-09 반도체 집적회로 KR890004958B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60013068A JPH0738583B2 (ja) 1985-01-26 1985-01-26 半導体集積回路
JP60-13068 1985-01-26

Publications (2)

Publication Number Publication Date
KR860006137A true KR860006137A (ko) 1986-08-18
KR890004958B1 KR890004958B1 (ko) 1989-12-02

Family

ID=11822824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000085A KR890004958B1 (ko) 1985-01-26 1986-01-09 반도체 집적회로

Country Status (5)

Country Link
US (2) US4740713A (ko)
EP (1) EP0190027B1 (ko)
JP (1) JPH0738583B2 (ko)
KR (1) KR890004958B1 (ko)
DE (1) DE3688088T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113835007A (zh) * 2020-06-08 2021-12-24 长鑫存储技术有限公司 热载流效应耐受度的测试方法

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JPH0738583B2 (ja) * 1985-01-26 1995-04-26 株式会社東芝 半導体集積回路
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US6411140B1 (en) 1995-12-20 2002-06-25 Cypress Semiconductor Corporation Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113835007A (zh) * 2020-06-08 2021-12-24 长鑫存储技术有限公司 热载流效应耐受度的测试方法
CN113835007B (zh) * 2020-06-08 2022-09-20 长鑫存储技术有限公司 热载流效应耐受度的测试方法

Also Published As

Publication number Publication date
US4857763A (en) 1989-08-15
DE3688088D1 (de) 1993-04-29
JPS61172435A (ja) 1986-08-04
US4740713A (en) 1988-04-26
KR890004958B1 (ko) 1989-12-02
EP0190027A3 (en) 1988-09-28
EP0190027A2 (en) 1986-08-06
JPH0738583B2 (ja) 1995-04-26
DE3688088T2 (de) 1993-07-29
EP0190027B1 (en) 1993-03-24

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