DE3650638D1 - Integrierte Halbleiterschaltung mit Isolationszone - Google Patents

Integrierte Halbleiterschaltung mit Isolationszone

Info

Publication number
DE3650638D1
DE3650638D1 DE3650638T DE3650638T DE3650638D1 DE 3650638 D1 DE3650638 D1 DE 3650638D1 DE 3650638 T DE3650638 T DE 3650638T DE 3650638 T DE3650638 T DE 3650638T DE 3650638 D1 DE3650638 D1 DE 3650638D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
isolation zone
isolation
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3650638T
Other languages
English (en)
Other versions
DE3650638T2 (de
Inventor
Michio Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3650638D1 publication Critical patent/DE3650638D1/de
Publication of DE3650638T2 publication Critical patent/DE3650638T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE3650638T 1985-03-22 1986-03-24 Integrierte Halbleiterschaltung mit Isolationszone Expired - Lifetime DE3650638T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5780185 1985-03-22

Publications (2)

Publication Number Publication Date
DE3650638D1 true DE3650638D1 (de) 1997-08-14
DE3650638T2 DE3650638T2 (de) 1998-02-12

Family

ID=13066009

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3650638T Expired - Lifetime DE3650638T2 (de) 1985-03-22 1986-03-24 Integrierte Halbleiterschaltung mit Isolationszone

Country Status (3)

Country Link
US (2) US4748489A (de)
EP (1) EP0195460B1 (de)
DE (1) DE3650638T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4990983A (en) * 1986-10-31 1991-02-05 Rockwell International Corporation Radiation hardened field oxides for NMOS and CMOS-bulk and process for forming
JPS63262873A (ja) * 1987-04-21 1988-10-31 Fuji Xerox Co Ltd 半導体装置
US4949162A (en) * 1987-06-05 1990-08-14 Hitachi, Ltd. Semiconductor integrated circuit with dummy pedestals
JP2644776B2 (ja) * 1987-11-02 1997-08-25 株式会社日立製作所 半導体装置及びその製造方法
US5670816A (en) * 1989-04-07 1997-09-23 Kabushiki Kaisha Toshiba Semiconductor device
JP2553723B2 (ja) * 1989-12-25 1996-11-13 三菱電機株式会社 化合物半導体集積回路装置
JPH0555566A (ja) * 1991-08-28 1993-03-05 Nec Corp 半導体装置
DE4225489A1 (de) * 1992-07-30 1994-02-03 Michael Prof Dr Rer Na Dittgen Verfahren zur Herstellung bioadhäsiver Augentropfen
JP2825068B2 (ja) * 1995-04-20 1998-11-18 日本電気株式会社 半導体装置
KR0149256B1 (ko) * 1995-08-25 1998-10-01 김주용 씨모스 트랜지스터 제조방법
JP3689505B2 (ja) * 1995-11-01 2005-08-31 キヤノン株式会社 半導体装置の作製方法
US7045437B1 (en) * 2005-06-27 2006-05-16 The Regents Of The University Of California Method for fabricating shallow trenches
WO2007001297A1 (en) * 2005-06-27 2007-01-04 The Regents Of The University Of California Method for fabricating shallow trenches
US7309636B2 (en) * 2005-11-07 2007-12-18 United Microelectronics Corp. High-voltage metal-oxide-semiconductor device and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
US4114255A (en) * 1976-08-16 1978-09-19 Intel Corporation Floating gate storage device and method of fabrication
US4095251A (en) * 1976-08-19 1978-06-13 International Business Machines Corporation Field effect transistors and fabrication of integrated circuits containing the transistors
US4378565A (en) * 1980-10-01 1983-03-29 General Electric Company Integrated circuit and method of making same
US4519849A (en) * 1980-10-14 1985-05-28 Intel Corporation Method of making EPROM cell with reduced programming voltage
US4466174A (en) * 1981-12-28 1984-08-21 Texas Instruments Incorporated Method for fabricating MESFET device using a double LOCOS process
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法
JPS58171832A (ja) * 1982-03-31 1983-10-08 Toshiba Corp 半導体装置の製造方法
DE3312648A1 (de) * 1982-04-12 1983-10-27 N.V. Philips' Gloeilampenfabrieken, 5621 Eindhoven Programmierbarer lesespeicher und verfahren zum herstellen desselben
US4546536A (en) * 1983-08-04 1985-10-15 International Business Machines Corporation Fabrication methods for high performance lateral bipolar transistors

Also Published As

Publication number Publication date
US4853340A (en) 1989-08-01
DE3650638T2 (de) 1998-02-12
EP0195460A2 (de) 1986-09-24
EP0195460B1 (de) 1997-07-09
US4748489A (en) 1988-05-31
EP0195460A3 (de) 1991-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP