KR20010104626A - 반도체장치 및 그 제조방법 - Google Patents
반도체장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR20010104626A KR20010104626A KR1020010022093A KR20010022093A KR20010104626A KR 20010104626 A KR20010104626 A KR 20010104626A KR 1020010022093 A KR1020010022093 A KR 1020010022093A KR 20010022093 A KR20010022093 A KR 20010022093A KR 20010104626 A KR20010104626 A KR 20010104626A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor
- bumps
- adhesive layer
- semiconductor chip
- forming
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 553
- 238000004519 manufacturing process Methods 0.000 title claims description 75
- 239000012790 adhesive layer Substances 0.000 claims abstract description 169
- 238000000034 method Methods 0.000 claims abstract description 70
- 230000001070 adhesive effect Effects 0.000 claims abstract description 21
- 239000000853 adhesive Substances 0.000 claims abstract description 20
- 229920005989 resin Polymers 0.000 claims description 79
- 239000011347 resin Substances 0.000 claims description 79
- 239000010410 layer Substances 0.000 claims description 65
- 230000001681 protective effect Effects 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 239000002184 metal Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 46
- 230000004907 flux Effects 0.000 claims description 43
- 239000011888 foil Substances 0.000 claims description 42
- 229910000679 solder Inorganic materials 0.000 claims description 31
- 229920001187 thermosetting polymer Polymers 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 28
- 238000005520 cutting process Methods 0.000 claims description 18
- 238000003825 pressing Methods 0.000 claims description 17
- 229920005992 thermoplastic resin Polymers 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 36
- 239000011889 copper foil Substances 0.000 abstract description 14
- 239000004840 adhesive resin Substances 0.000 abstract description 5
- 229920006223 adhesive resin Polymers 0.000 abstract description 5
- 229920001169 thermoplastic Polymers 0.000 abstract description 5
- 239000004416 thermosoftening plastic Substances 0.000 abstract description 5
- 239000010931 gold Substances 0.000 description 55
- 230000008901 benefit Effects 0.000 description 29
- 229910052802 copper Inorganic materials 0.000 description 24
- 239000010949 copper Substances 0.000 description 24
- 238000007747 plating Methods 0.000 description 24
- 239000011295 pitch Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 14
- 238000007789 sealing Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 7
- 230000005855 radiation Effects 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000005304 joining Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 description 2
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 2
- 241000482268 Zea mays subsp. mays Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/05573—Single external layer
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/13001—Core members of the bump connector
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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Abstract
Description
Claims (25)
- 반도체칩;상기 반도체칩의 전극 위에 제공된 스터드범프; 및상기 반도체칩의 상기 전극이 형성되는 표면에 제공된 접착층을 포함하며,상기 스터드범프는 상기 접착층의 표면으로부터 돌출한 반도체장치.
- 제1항에 있어서, 열압착을 통해 접합된 개재기를 더 포함하는 반도체장치.
- 반도체칩;상기 반도체칩의 전극이 형성되는 표면에 제공된 보호수지층;상기 반도체칩의 상기 전극 위에 제공되며 상기 보호수지층의 표면에서는 노출되는 범프; 및경화플럭스를 통해 상기 보호수지층의 상기 표면에 접착되고, 상기 범프에 전기적으로 접속되는 개재기를 포함하는 반도체장치.
- 제2항에 있어서, 상기 개재기에는 장치홀이 제공된 반도체장치.
- 반도체칩;상기 반도체칩의 전극이 형성되는 표면에 제공된 접착층;상기 반도체칩의 상기 전극 위에 제공되고 상기 접착층의 표면에서는 노출되는 범프;상기 접착층의 상기 표면에 접착되고 상기 범프에 부분적으로 접착된 배선패턴; 및상기 배선패턴을 절연하고 덮으며 선택적으로 개구되어 외부접속부를 형성하는 절연덮개층을 포함하는 반도체장치.
- 반도체칩;상기 반도체칩의 전극이 형성되는 표면에 제공된 보호수지층;상기 반도체칩의 상기 전극 위에 제공되고 상기 보호수지층의 표면에서는 노출되는 범프;경화된 플럭스를 통해 상기 보호수지층의 상기 표면에 접착되고 상기 범프에 부분적으로 접착되는 배선패턴; 및상기 배선패턴을 절연하고 덮으며 선택적으로 개구되어 외부접속부를 형성하는 절연덮개층을 포함하는 반도체장치.
- 각각의 반도체디바이스가 반도체칩, 상기 반도체칩의 전극이 형성되는 표면에 제공된 접착층, 상기 반도체칩의 상기 전극 위에 제공되며 상기 접착층의 표면에서는 부분적으로 노출되는 범프를 구비한 두 개 이상의 반도체디바이스들을 포함하고,상기 반도체디바이스들 중의 하나의 상기 접착층이 제공된 표면의 일부는 상기 반도체디바이스들 중의 다른 하나의 상기 접착층이 제공된 표면의 일부 또는 전부에 접합되고, 그것들은 접착면에서 상기 범프들을 사용하여 서로 전기적으로 접속되는 반도체장치.
- 각각의 반도체디바이스가 앞면 및 뒷면에 전극들이 형성된 반도체칩, 상기 반도체칩의 앞면 및 뒷면에 제공된 접착층, 및 상기 반도체칩의 상기 전극 위에 제공되며 상기 접착층의 표면에서는 부분적으로 노출되는 범프를 구비한 두 개 이상의 반도체디바이스들을 포함하고,상기 반도체디바이스들 중의 하나는 아래쪽에 있는 상기 반도체디바이스들 중의 하나에 상기 접착층을 통해 접착되고, 그 전극들은 상기 범프를 통해 서로 접속되는 반도체장치.
- 제1항에 있어서, 상기 접착층은 접착성을 갖는 열가소성수지인 반도체장치.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계; 및상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체웨이퍼를 절단하는단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체웨이퍼를 절단하는 단계; 및하나 또는 둘 이상의 상기 반도체칩들을 단일 배선기판 위에 실장하고, 상기 접착층을 이용한 상기 배선기판에 대한 접착과 상기 범프를 이용한 상기 배선기판에 대한 전기접속을 위해 가열 및 프레싱을 수행하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 보호수지층을 형성하는 단계;상기 보호수지층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체웨이퍼를 절단하는 단계; 및하나 또는 둘 이상의 상기 반도체칩들에 대해, 상기 범프 및 상기 보호수지층 또는 대응하는 배선기판에 열경화플럭스를 도포하는 단계;상기 범프를 상기 배선기판의 배선 위에 배치시키는 단계; 및가열을 수행하여 상기 범프를 상기 배선에 납땜하고 상기 열경화플럭스를 경화시키는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계; 및상기 반도체웨이퍼를 상기 접착층을 통해 배선기판에 접합하고 상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 접착층을 이용하여 상기 반도체웨이퍼를 배선기판과 정렬하고, 상기 접착층을 이용하여 상기 배선기판에 대한 접착과 상기 범프를 이용한 상기 배선기판 위의 배선에 대한 전기접속을 위해 가열 및 프레싱을 수행하는 단계; 및상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 보호수지층을 형성하는 단계;상기 보호수지층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 범프 및 상기 보호수지층 또는 대응하는 배선기판에 열경화플럭스를 도포하는 단계;상기 범프를 상기 배선기판의 배선 위에 배치시키는 단계; 및상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 범프를 반도체칩의 전극 위에 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 반도체칩을 상기 접착층을 통해 금속박(metal foil)에 접합하는 단계; 및상기 금속박을 배선패턴으로 형성하는 단계를 포함하는 반도체장치 제조방법.
- 범프를 반도체칩의 전극 위에 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 접착층을 통해 상기 반도체웨이퍼를 금속박과 정렬하고, 상기 접착층을 이용한 상기 금속박에 대한 접착과 상기 범프를 이용한 상기 금속박에 대한 전기접속을 위해 가열 및 프레싱을 수행하는 단계; 및상기 금속박을 배선패턴으로 형성하는 단계를 포함하는 반도체장치 제조방법.
- 범프를 반도체칩의 전극 위에 제공하는 단계;상기 범프가 제공된 표면에 보호수지층을 형성하는 단계;상기 보호수지층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 보호수지층을 통하여 상기 반도체웨이퍼를 금속박과 정렬하는 단계;가열을 수행하여 상기 범프를 상기 금속박에 납땜하고 열경화플럭스를 경화시키는 단계; 및상기 금속박을 배선패턴으로 형성하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 반도체웨이퍼를 상기 접착층을 통해 금속박에 접합하는 단계;상기 금속박을 배선패턴으로 형성하는 단계; 및그 후, 상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의 각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 접착층을 형성하는 단계;상기 접착층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 접착층을 통해 상기 반도체웨이퍼를 금속박과 정렬하고, 상기 접착층을 이용한 상기 금속박에 대한 접착과 상기 범프를 이용한 상기 금속박에 대한 전기접속을 위해 가열 및 프레싱을 수행하는 단계;상기 금속박을 배선패턴으로 형성하는 단계; 및그 후, 상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 기설정된 수의 반도체칩들을 반도체웨이퍼 위에 형성하고 상기 반도체칩들의각각의 전극 위에 범프를 제공하는 단계;상기 범프가 제공된 표면에 보호수지층을 형성하는 단계;상기 보호수지층의 전체 표면을 상기 범프가 돌출할 때까지 식각하는 단계;상기 보호수지층을 통해 상기 반도체웨이퍼를 금속박과 정렬하는 단계;가열을 수행하여 상기 범프를 상기 금속박에 납땜하고 상기 보호수지층을 경화시키는 단계;상기 금속박을 배선패턴으로 형성하는 단계; 및그 후, 상기 반도체칩들의 각각으로 분리하기 위해 상기 반도체칩을 그것의 외부경계를 따라 절단하는 단계를 포함하는 반도체장치 제조방법.
- 제16항에 있어서, 상기 금속박이 배선패턴으로 형성된 후, 상기 배선패턴 위에 절연덮개층을 선택적으로 형성하는 단계를 더 포함하는 반도체장치 제조방법.
- 제22항에 있어서, 상기 절연덮개층이 상기 배선패턴 위에 선택적으로 형성된 후, 상기 절연덮개층의 개구를 통해 노출된 상기 배선패턴의 랜드부 위에 땜납볼을 제공하는 단계를 더 포함하는 반도체장치 제조방법.
- 제10항에 있어서, 상기 접착층은 접착성을 갖는 열가소성 수지인 반도체장치 제조방법.
- 반도체칩;상기 반도체칩의 전극이 형성된 표면에 제공된 접착층;상기 반도체칩의 상기 전극 위에 제공되며 상기 접착층의 표면에서는 노출된 범프;테이프기판; 및개재기를 포함하고,상기 반도체칩은 상기 테이기판의 앞면에 상기 접착층을 이용하여 접착되며, 상기 반도체칩은 상기 범프를 이용하여 상기 테이프기판에 전기적으로 접속되고, 상기 개재기는 전기접속 가능하도록 상기 테이프기판의 뒷면에 접속되는 반도체장치 제조방법.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160084914A (ko) * | 2015-01-06 | 2016-07-15 | 매그나칩 반도체 유한회사 | 방열 반도체 소자 패키지 및 그 제조 방법 |
Families Citing this family (128)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI112121B (fi) * | 2000-12-11 | 2003-10-31 | Rafsec Oy | Älytarraraina, menetelmä sen valmistamiseksi, menetelmä kantorainan valmistamiseksi ja älytarrarainan älytarran rakenneosa |
SG95637A1 (en) | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
US6441483B1 (en) | 2001-03-30 | 2002-08-27 | Micron Technology, Inc. | Die stacking scheme |
SG108245A1 (en) * | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
US20020173077A1 (en) * | 2001-05-03 | 2002-11-21 | Ho Tzong Da | Thermally enhanced wafer-level chip scale package and method of fabricating the same |
JP2002353369A (ja) * | 2001-05-28 | 2002-12-06 | Sharp Corp | 半導体パッケージおよびその製造方法 |
US6794751B2 (en) * | 2001-06-29 | 2004-09-21 | Intel Corporation | Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies |
KR20030018204A (ko) * | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | 스페이서를 갖는 멀티 칩 패키지 |
JP2003068928A (ja) * | 2001-08-28 | 2003-03-07 | Kyocera Corp | 高周波用配線基板の実装構造 |
JP3875077B2 (ja) * | 2001-11-16 | 2007-01-31 | 富士通株式会社 | 電子デバイス及びデバイス接続方法 |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
SG115456A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG111935A1 (en) * | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
AU2003225724A1 (en) * | 2002-03-11 | 2003-09-29 | Momenta Pharmaceuticals, Inc. | Analysis of sulfated polysaccharides |
US6639302B2 (en) * | 2002-03-20 | 2003-10-28 | International Business Machines Corporation | Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries |
JP3717899B2 (ja) | 2002-04-01 | 2005-11-16 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6906415B2 (en) * | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
US7573136B2 (en) * | 2002-06-27 | 2009-08-11 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor device components |
US20040036170A1 (en) * | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US6881613B2 (en) * | 2002-10-08 | 2005-04-19 | Agere Systems Inc | Electronic component package |
JP3566957B2 (ja) * | 2002-12-24 | 2004-09-15 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2004247530A (ja) * | 2003-02-14 | 2004-09-02 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US6936929B1 (en) * | 2003-03-17 | 2005-08-30 | National Semiconductor Corporation | Multichip packages with exposed dice |
TW200507218A (en) * | 2003-03-31 | 2005-02-16 | North Corp | Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module |
JP3947525B2 (ja) * | 2003-04-16 | 2007-07-25 | 沖電気工業株式会社 | 半導体装置の放熱構造 |
US7126228B2 (en) * | 2003-04-23 | 2006-10-24 | Micron Technology, Inc. | Apparatus for processing semiconductor devices in a singulated form |
US7129590B2 (en) * | 2003-05-14 | 2006-10-31 | Intel Corporation | Stencil and method for depositing material onto a substrate |
US7047633B2 (en) * | 2003-05-23 | 2006-05-23 | National Starch And Chemical Investment Holding, Corporation | Method of using pre-applied underfill encapsulant |
US7547975B2 (en) * | 2003-07-30 | 2009-06-16 | Tdk Corporation | Module with embedded semiconductor IC and method of fabricating the module |
JP2005064239A (ja) * | 2003-08-12 | 2005-03-10 | Lintec Corp | 半導体装置の製造方法 |
DE10339609A1 (de) * | 2003-08-28 | 2005-03-24 | Forschungszentrum Karlsruhe Gmbh | Oligonukleotid, Verfahren und System zur Detektion von Antibiotikaresistenz-vermittelnden Genen in Mikroorganismen mittels der Echtzeit-PCR |
EP1542272B1 (en) * | 2003-10-06 | 2016-07-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP4130167B2 (ja) * | 2003-10-06 | 2008-08-06 | 日東電工株式会社 | 半導体ウエハの剥離方法 |
JP4260617B2 (ja) * | 2003-12-24 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US20050147489A1 (en) * | 2003-12-24 | 2005-07-07 | Tian-An Chen | Wafer supporting system for semiconductor wafers |
US7303400B2 (en) * | 2004-01-27 | 2007-12-04 | United Microelectronics Corp. | Package of a semiconductor device with a flexible wiring substrate and method for the same |
US20050161815A1 (en) * | 2004-01-27 | 2005-07-28 | Joseph Sun | Package of a semiconductor device with a flexible wiring substrate and method for the same |
US7160758B2 (en) * | 2004-03-31 | 2007-01-09 | Intel Corporation | Electronic packaging apparatus and method |
KR100604848B1 (ko) * | 2004-04-30 | 2006-07-31 | 삼성전자주식회사 | 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법 |
US7217597B2 (en) | 2004-06-22 | 2007-05-15 | Micron Technology, Inc. | Die stacking scheme |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI237370B (en) * | 2004-07-30 | 2005-08-01 | Advanced Semiconductor Eng | Chip package structure and process for fabricating the same |
JP2008252132A (ja) * | 2004-09-15 | 2008-10-16 | Seiko Epson Corp | 半導体装置の実装方法 |
TW200618705A (en) * | 2004-09-16 | 2006-06-01 | Tdk Corp | Multilayer substrate and manufacturing method thereof |
JP4246132B2 (ja) * | 2004-10-04 | 2009-04-02 | シャープ株式会社 | 半導体装置およびその製造方法 |
TWI267151B (en) * | 2004-10-14 | 2006-11-21 | Advanced Semiconductor Eng | Processing method during a package process |
US20060211233A1 (en) * | 2005-03-21 | 2006-09-21 | Skyworks Solutions, Inc. | Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure |
US7576426B2 (en) * | 2005-04-01 | 2009-08-18 | Skyworks Solutions, Inc. | Wafer level package including a device wafer integrated with a passive component |
JP4345705B2 (ja) * | 2005-04-19 | 2009-10-14 | エルピーダメモリ株式会社 | メモリモジュール |
US20060270104A1 (en) * | 2005-05-03 | 2006-11-30 | Octavio Trovarelli | Method for attaching dice to a package and arrangement of dice in a package |
JP4191167B2 (ja) * | 2005-05-16 | 2008-12-03 | エルピーダメモリ株式会社 | メモリモジュールの製造方法 |
US7777313B2 (en) * | 2005-06-07 | 2010-08-17 | Analog Devices, Inc. | Electronic package structures and methods |
KR100621438B1 (ko) | 2005-08-31 | 2006-09-08 | 삼성전자주식회사 | 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법 |
TWI305404B (en) * | 2005-09-14 | 2009-01-11 | Advanced Semiconductor Eng | Die package and method for making the same |
JP4535002B2 (ja) * | 2005-09-28 | 2010-09-01 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
US20070093000A1 (en) * | 2005-10-21 | 2007-04-26 | Stats Chippac Ltd. | Pre-molded leadframe and method therefor |
JP2007173371A (ja) * | 2005-12-20 | 2007-07-05 | Shinko Electric Ind Co Ltd | フレキシブル配線基板の製造方法及び電子部品実装構造体の製造方法 |
US7684205B2 (en) * | 2006-02-22 | 2010-03-23 | General Dynamics Advanced Information Systems, Inc. | System and method of using a compliant lead interposer |
TWI294677B (en) * | 2006-03-31 | 2008-03-11 | Ind Tech Res Inst | Interconnect structure with stress buffering ability and the manufacturing method thereof |
DE102006025960B4 (de) * | 2006-06-02 | 2011-04-07 | Infineon Technologies Ag | Verfahren zur Herstellung einer integrierten Halbleitereinrichtung |
KR100748558B1 (ko) | 2006-06-19 | 2007-08-10 | 삼성전자주식회사 | 칩 사이즈 패키지 및 그 제조 방법 |
JP2008004741A (ja) * | 2006-06-22 | 2008-01-10 | Matsushita Electric Ind Co Ltd | 半導体集積回路及びそれを備えた情報機器、通信機器、av機器及び移動体 |
US7635606B2 (en) * | 2006-08-02 | 2009-12-22 | Skyworks Solutions, Inc. | Wafer level package with cavities for active devices |
US7504713B2 (en) * | 2007-01-16 | 2009-03-17 | Texas Instruments Incorporated | Plastic semiconductor packages having improved metal land-locking features |
US20080217708A1 (en) * | 2007-03-09 | 2008-09-11 | Skyworks Solutions, Inc. | Integrated passive cap in a system-in-package |
US7659151B2 (en) * | 2007-04-12 | 2010-02-09 | Micron Technology, Inc. | Flip chip with interposer, and methods of making same |
US20080290502A1 (en) * | 2007-05-25 | 2008-11-27 | Zafer Kutlu | Integrated circuit package with soldered lid for improved thermal performance |
JP2008294367A (ja) * | 2007-05-28 | 2008-12-04 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7982137B2 (en) * | 2007-06-27 | 2011-07-19 | Hamilton Sundstrand Corporation | Circuit board with an attached die and intermediate interposer |
US8043893B2 (en) * | 2007-09-14 | 2011-10-25 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
EP2215655A4 (en) | 2007-11-30 | 2014-07-30 | Skyworks Solutions Inc | CAPACITATION AT WAFBERBENE USING FLIP-CHIP ATTACHMENT |
US8900931B2 (en) * | 2007-12-26 | 2014-12-02 | Skyworks Solutions, Inc. | In-situ cavity integrated circuit package |
JP2010010368A (ja) * | 2008-06-26 | 2010-01-14 | Sumitomo Bakelite Co Ltd | 半導体装置および半導体装置の製造方法 |
WO2009099191A1 (ja) | 2008-02-07 | 2009-08-13 | Sumitomo Bakelite Company Limited | 半導体用フィルム、半導体装置の製造方法および半導体装置 |
KR100959604B1 (ko) | 2008-03-10 | 2010-05-27 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 반도체 패키지 및 이의 제조 방법 |
US8018043B2 (en) | 2008-03-10 | 2011-09-13 | Hynix Semiconductor Inc. | Semiconductor package having side walls and method for manufacturing the same |
JPWO2009118925A1 (ja) * | 2008-03-27 | 2011-07-21 | イビデン株式会社 | 電子部品内蔵配線板及びその製造方法 |
TW200947569A (en) * | 2008-05-13 | 2009-11-16 | Richtek Technology Corp | Package structure and method |
JP2009302212A (ja) | 2008-06-11 | 2009-12-24 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
US8624370B2 (en) * | 2009-03-20 | 2014-01-07 | Stats Chippac Ltd. | Integrated circuit packaging system with an interposer and method of manufacture thereof |
JP2010245383A (ja) * | 2009-04-08 | 2010-10-28 | Elpida Memory Inc | 半導体装置および半導体装置の製造方法 |
JP5732652B2 (ja) * | 2009-11-04 | 2015-06-10 | ボンドテック株式会社 | 接合システムおよび接合方法 |
JP5581064B2 (ja) * | 2010-01-14 | 2014-08-27 | パナソニック株式会社 | 半導体装置 |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US8698322B2 (en) * | 2010-03-24 | 2014-04-15 | Oracle International Corporation | Adhesive-bonded substrates in a multi-chip module |
US8174108B2 (en) * | 2010-03-24 | 2012-05-08 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Method for facilitating the stacking of integrated circuits having different areas and an integrated circuit package constructed by the method |
JP5246215B2 (ja) * | 2010-07-21 | 2013-07-24 | 株式会社村田製作所 | セラミック電子部品及び配線基板 |
TW201208007A (en) * | 2010-08-02 | 2012-02-16 | Advanced Semiconductor Eng | Semiconductor package |
US8445990B2 (en) * | 2010-12-10 | 2013-05-21 | Stats Chippac, Ltd. | Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die |
US8344493B2 (en) * | 2011-01-06 | 2013-01-01 | Texas Instruments Incorporated | Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips |
US10446530B2 (en) * | 2011-08-16 | 2019-10-15 | Intel Corporation | Offset interposers for large-bottom packages and large-die package-on-package structures |
US20130154106A1 (en) | 2011-12-14 | 2013-06-20 | Broadcom Corporation | Stacked Packaging Using Reconstituted Wafers |
US9484319B2 (en) * | 2011-12-23 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate |
US9548251B2 (en) | 2012-01-12 | 2017-01-17 | Broadcom Corporation | Semiconductor interposer having a cavity for intra-interposer die |
US20130187284A1 (en) | 2012-01-24 | 2013-07-25 | Broadcom Corporation | Low Cost and High Performance Flip Chip Package |
US8558395B2 (en) | 2012-02-21 | 2013-10-15 | Broadcom Corporation | Organic interface substrate having interposer with through-semiconductor vias |
US8587132B2 (en) | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US8749072B2 (en) * | 2012-02-24 | 2014-06-10 | Broadcom Corporation | Semiconductor package with integrated selectively conductive film interposer |
US9275976B2 (en) | 2012-02-24 | 2016-03-01 | Broadcom Corporation | System-in-package with integrated socket |
US8928128B2 (en) | 2012-02-27 | 2015-01-06 | Broadcom Corporation | Semiconductor package with integrated electromagnetic shielding |
US9263412B2 (en) | 2012-03-09 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and packaged semiconductor devices |
US20130234317A1 (en) | 2012-03-09 | 2013-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging Methods and Packaged Semiconductor Devices |
JP5965185B2 (ja) * | 2012-03-30 | 2016-08-03 | デクセリアルズ株式会社 | 回路接続材料、及びこれを用いた半導体装置の製造方法 |
US9202714B2 (en) * | 2012-04-24 | 2015-12-01 | Micron Technology, Inc. | Methods for forming semiconductor device packages |
CN103426780A (zh) * | 2012-05-14 | 2013-12-04 | 万国半导体(开曼)股份有限公司 | 焊球阵列用作高度垫块及焊料固定物 |
CN104716056B (zh) * | 2013-12-17 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | 一种晶圆键合方法 |
US10026671B2 (en) | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9768090B2 (en) | 2014-02-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9653443B2 (en) * | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9935090B2 (en) | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
JP2016033969A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社東芝 | 電子部品、及び電子ユニット |
JP6361374B2 (ja) * | 2014-08-25 | 2018-07-25 | 日亜化学工業株式会社 | 発光装置及びその製造方法 |
JP6623508B2 (ja) * | 2014-09-30 | 2019-12-25 | 日亜化学工業株式会社 | 光源及びその製造方法、実装方法 |
US9564416B2 (en) | 2015-02-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US10679866B2 (en) | 2015-02-13 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor package and method of fabricating the interconnect structure |
JP6754938B2 (ja) * | 2016-03-11 | 2020-09-16 | パナソニックIpマネジメント株式会社 | 電極接合方法 |
US10734350B2 (en) * | 2016-05-09 | 2020-08-04 | Hitachi Chemical Company, Ltd. | Method for manufacturing semiconductor device |
JP2019012714A (ja) * | 2017-06-29 | 2019-01-24 | 株式会社ディスコ | 半導体パッケージの製造方法 |
JP6956313B2 (ja) * | 2017-07-27 | 2021-11-02 | パナソニックIpマネジメント株式会社 | 半導体装置の製造方法 |
CN112750796A (zh) * | 2019-10-30 | 2021-05-04 | 新光电气工业株式会社 | 半导体装置以及半导体装置的制造方法 |
CN110783254B (zh) * | 2019-11-08 | 2022-10-04 | 京东方科技集团股份有限公司 | 一种芯片转移方法及半导体器件 |
KR102643424B1 (ko) * | 2019-12-13 | 2024-03-06 | 삼성전자주식회사 | 반도체 패키지 |
CN114664784B (zh) * | 2022-03-15 | 2024-07-23 | 广东汇芯半导体有限公司 | 一种方便布线的智能功率模组及其制造方法 |
CN115116860A (zh) * | 2022-06-17 | 2022-09-27 | 北京比特大陆科技有限公司 | 芯片封装方法及芯片 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6130059A (ja) * | 1984-07-20 | 1986-02-12 | Nec Corp | 半導体装置の製造方法 |
JP2701589B2 (ja) | 1991-06-26 | 1998-01-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH06204290A (ja) | 1992-12-28 | 1994-07-22 | Canon Inc | 回路基板の製造方法及び前記電気接続部材と電気的回路部品との接続方法 |
JP2581017B2 (ja) | 1994-09-30 | 1997-02-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5579573A (en) * | 1994-10-11 | 1996-12-03 | Ford Motor Company | Method for fabricating an undercoated chip electrically interconnected to a substrate |
JP3655338B2 (ja) | 1995-02-28 | 2005-06-02 | シチズン時計株式会社 | 樹脂封止型半導体装置及びその製造方法 |
US5783870A (en) * | 1995-03-16 | 1998-07-21 | National Semiconductor Corporation | Method for connecting packages of a stacked ball grid array structure |
JP2735022B2 (ja) | 1995-03-22 | 1998-04-02 | 日本電気株式会社 | バンプ製造方法 |
JP3505328B2 (ja) | 1995-12-18 | 2004-03-08 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
JP3279470B2 (ja) | 1996-02-20 | 2002-04-30 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
JPH1126642A (ja) | 1997-07-07 | 1999-01-29 | Fujitsu Ltd | 半導体装置及びその製造方法及びその実装構造 |
US5854514A (en) * | 1996-08-05 | 1998-12-29 | International Buisness Machines Corporation | Lead-free interconnection for electronic devices |
US6114187A (en) * | 1997-01-11 | 2000-09-05 | Microfab Technologies, Inc. | Method for preparing a chip scale package and product produced by the method |
JP3604250B2 (ja) | 1997-02-19 | 2004-12-22 | 株式会社リコー | 半導体装置実装体 |
JP3695890B2 (ja) | 1997-02-19 | 2005-09-14 | ジャパンゴアテックス株式会社 | Icチップ実装用インターポーザ及びicチップパッケージ |
JPH10242333A (ja) | 1997-03-01 | 1998-09-11 | Nitto Denko Corp | 半導体装置及び半導体装置の製造方法 |
WO1999004430A1 (en) | 1997-07-21 | 1999-01-28 | Aguila Technologies, Inc. | Semiconductor flip-chip package and method for the fabrication thereof |
JP3421548B2 (ja) | 1997-09-10 | 2003-06-30 | 富士通株式会社 | 半導体ベアチップ、半導体ベアチップの製造方法、及び半導体ベアチップの実装構造 |
JPH11135577A (ja) | 1997-10-28 | 1999-05-21 | Hitachi Cable Ltd | Bga用tabテープ |
JPH11168185A (ja) | 1997-12-03 | 1999-06-22 | Rohm Co Ltd | 積層基板体および半導体装置 |
JP3065010B2 (ja) | 1997-12-26 | 2000-07-12 | 日本電気株式会社 | 半導体装置 |
JP3547303B2 (ja) | 1998-01-27 | 2004-07-28 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JP3417292B2 (ja) | 1998-04-08 | 2003-06-16 | 松下電器産業株式会社 | 半導体装置 |
JP3339422B2 (ja) | 1998-04-20 | 2002-10-28 | ソニーケミカル株式会社 | 配線基板及びその製造方法 |
JP2000022027A (ja) | 1998-06-29 | 2000-01-21 | Sony Corp | 半導体装置、その製造方法およびパッケージ用基板 |
JP2000058587A (ja) | 1998-08-12 | 2000-02-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
US6285081B1 (en) * | 1999-07-13 | 2001-09-04 | Micron Technology, Inc. | Deflectable interconnect |
JP2001284382A (ja) | 2000-03-28 | 2001-10-12 | Nec Corp | はんだバンプ形成方法、フリップチップ実装方法及び実装構造体 |
-
2000
- 2000-04-24 JP JP2000123306A patent/JP3597754B2/ja not_active Expired - Lifetime
-
2001
- 2001-04-19 EP EP01109690A patent/EP1150347A2/en not_active Withdrawn
- 2001-04-23 US US09/839,298 patent/US6791195B2/en not_active Expired - Lifetime
- 2001-04-24 CN CN01109597A patent/CN1320964A/zh active Pending
- 2001-04-24 KR KR10-2001-0022093A patent/KR100384260B1/ko active IP Right Grant
- 2001-04-24 SG SG200102293A patent/SG100674A1/en unknown
- 2001-04-24 TW TW090109843A patent/TW501208B/zh not_active IP Right Cessation
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160084914A (ko) * | 2015-01-06 | 2016-07-15 | 매그나칩 반도체 유한회사 | 방열 반도체 소자 패키지 및 그 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
US6791195B2 (en) | 2004-09-14 |
US20020132463A1 (en) | 2002-09-19 |
TW501208B (en) | 2002-09-01 |
KR100384260B1 (ko) | 2003-05-16 |
JP3597754B2 (ja) | 2004-12-08 |
EP1150347A2 (en) | 2001-10-31 |
US20010036711A1 (en) | 2001-11-01 |
SG100674A1 (en) | 2003-12-26 |
JP2001308140A (ja) | 2001-11-02 |
CN1320964A (zh) | 2001-11-07 |
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